#include <gpu_tlb.hh>

Inheritance diagram for X86ISA::GpuTLB:

Classes
struct	AccessInfo
	This hash map will use the virtual page address as a key and will keep track of total number of accesses per page. More...

class	CpuSidePort

class	MemSidePort
	MemSidePort is the TLB Port closer to the memory side If this is a last level TLB then this port will not be connected. More...

class	TLBEvent

class	Translation

struct	TranslationState
	TLB TranslationState: this currently is a somewhat bastardization of the usage of SenderState, whereby the receiver of a packet is not usually supposed to need to look at the contents of the senderState, you're really only supposed to look at what you pushed on, pop it off, and send it back. More...

Public Types
enum	tlbOutcome { TLB_HIT, TLB_MISS, PAGE_WALK, MISS_RETURN }

typedef X86GPUTLBParams	Params

typedef enum BaseTLB::Mode	Mode

typedef std::unordered_map < Addr, AccessInfo >	AccessPatternTable

Public Types inherited from MemObject
typedef MemObjectParams	Params

Public Types inherited from ClockedObject
typedef ClockedObjectParams	Params
	Parameters of ClockedObject. More...

Public Types inherited from SimObject
typedef SimObjectParams	Params

Public Member Functions
Tick	frequency () const

Tick	ticks (int numCycles) const

Tick	curCycle () const

Tick	tickToCycles (Tick val) const

	GpuTLB (const Params *p)

	~GpuTLB ()

void	dumpAll ()

GpuTlbEntry *	lookup (Addr va, bool update_lru=true)

void	setConfigAddress (uint32_t addr)

Walker *	getWalker ()

void	invalidateAll ()

void	invalidateNonGlobal ()

void	demapPage (Addr va, uint64_t asn)

void	regStats ()
	Register statistics for this object. More...

void	updatePageFootprint (Addr virt_page_addr)

void	printAccessPattern ()

Fault	translateAtomic (RequestPtr req, ThreadContext *tc, Mode mode, int &latency)

void	translateTiming (RequestPtr req, ThreadContext tc, Translation translation, Mode mode, int &latency)

Tick	doMmuRegRead (ThreadContext tc, Packet pkt)

Tick	doMmuRegWrite (ThreadContext tc, Packet pkt)

GpuTlbEntry *	insert (Addr vpn, GpuTlbEntry &entry)

virtual void	serialize (CheckpointOut &cp) const
	Serialize an object. More...

virtual void	unserialize (CheckpointIn &cp)
	Unserialize an object. More...

void	issueTranslation ()

bool	tlbLookup (RequestPtr req, ThreadContext *tc, bool update_stats)
	TLB_lookup will only perform a TLB lookup returning true on a TLB hit and false on a TLB miss. More...

void	handleTranslationReturn (Addr addr, tlbOutcome outcome, PacketPtr pkt)
	handleTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault returns. More...

void	handleFuncTranslationReturn (PacketPtr pkt, tlbOutcome outcome)
	handleFuncTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault returns. More...

void	pagingProtectionChecks (ThreadContext tc, PacketPtr pkt, GpuTlbEntry tlb_entry, Mode mode)
	Do Paging protection checks. More...

void	updatePhysAddresses (Addr virt_page_addr, GpuTlbEntry *tlb_entry, Addr phys_page_addr)

void	issueTLBLookup (PacketPtr pkt)
	Do the TLB lookup for this coalesced request and schedule another event <TLB access="" latency>=""> cycles later. More...

BaseMasterPort &	getMasterPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a master port with a given name and index. More...

BaseSlavePort &	getSlavePort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a slave port with a given name and index. More...

void	translationReturn (Addr virtPageAddr, tlbOutcome outcome, PacketPtr pkt)
	A TLBEvent is scheduled after the TLB lookup and helps us take the appropriate actions: (e.g., update TLB on a hit, send request to lower level TLB on a miss, or start a page walk if this was the last-level TLB). More...

void	cleanup ()

void	exitCallback ()

Public Member Functions inherited from MemObject
const Params *	params () const

	MemObject (const Params *params)

Public Member Functions inherited from ClockedObject
	ClockedObject (const ClockedObjectParams *p)

const Params *	params () const

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Enums::PwrState	pwrState () const

std::string	pwrStateName () const

std::vector< double >	pwrStateWeights () const
	Returns the percentage residency for each power state. More...

void	computeStats ()
	Record stats values like state residency by computing the time difference from previous update. More...

void	pwrState (Enums::PwrState)

void	regStats () override
	Register statistics for this object. More...

Public Member Functions inherited from SimObject
const Params *	params () const

	SimObject (const Params *_params)

virtual	~SimObject ()

virtual const std::string	name () const

virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	resetStats ()
	Reset statistics associated with this object. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from EventManager
	EventManager (EventManager &em)

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick)-1)

void	setCurTick (Tick newVal)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from Clocked
void	updateClockPeriod () const
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Public Attributes
int	hitLatency

int	missLatency1

int	missLatency2

Stats::Scalar	localNumTLBAccesses

Stats::Scalar	localNumTLBHits

Stats::Scalar	localNumTLBMisses

Stats::Formula	localTLBMissRate

Stats::Scalar	globalNumTLBAccesses

Stats::Scalar	globalNumTLBHits

Stats::Scalar	globalNumTLBMisses

Stats::Formula	globalTLBMissRate

Stats::Scalar	accessCycles

Stats::Scalar	pageTableCycles

Stats::Scalar	numUniquePages

Stats::Scalar	localCycles

Stats::Formula	localLatency

Stats::Scalar	avgReuseDistance

std::vector< CpuSidePort * >	cpuSidePort

std::vector< MemSidePort * >	memSidePort

int	maxCoalescedReqs

int	outstandingReqs

std::unordered_map< Addr, TLBEvent * >	translationReturnEvent

std::queue< Addr >	cleanupQueue

EventWrapper< GpuTLB,&GpuTLB::cleanup >	cleanupEvent

AccessPatternTable	TLBFootprint

EventWrapper< GpuTLB,&GpuTLB::exitCallback >	exitEvent

Protected Types
typedef std::list< GpuTlbEntry * >	EntryList

Protected Member Functions
EntryList::iterator	lookupIt (Addr va, bool update_lru=true)

Fault	translateInt (RequestPtr req, ThreadContext *tc)

Fault	translate (RequestPtr req, ThreadContext tc, Translation translation, Mode mode, bool &delayedResponse, bool timing, int &latency)

Protected Member Functions inherited from Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

Protected Attributes
uint32_t	configAddress

int	clock

Walker *	walker

int	size

int	assoc

int	numSets

bool	FA
	true if this is a fully-associative TLB More...

Addr	setMask

bool	allocationPolicy
	Allocation Policy: true if we always allocate on a hit, false otherwise. More...

bool	hasMemSidePort
	if true, then this is not the last level TLB More...

bool	accessDistance
	Print out accessDistance stats. More...

std::vector< GpuTlbEntry >	tlb

std::vector< EntryList >	freeList

std::vector< EntryList >	entryList
	An entryList per set is the equivalent of an LRU stack; it's used to guide replacement decisions. More...

Protected Attributes inherited from ClockedObject
Enums::PwrState	_currPwrState
	To keep track of the current power state. More...

Tick	prvEvalTick

Stats::Scalar	numPwrStateTransitions

Stats::Distribution	pwrStateClkGateDist

Stats::Vector	pwrStateResidencyTicks

Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Friends
class	Walker

Additional Inherited Members
Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Get the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)

static void	unserializeGlobals (CheckpointIn &cp)

Static Public Attributes inherited from Serializable
static int	ckptCount = 0

static int	ckptMaxCount = 0

static int	ckptPrevCount = -1

Detailed Description

Definition at line 76 of file gpu_tlb.hh.

Member Typedef Documentation

typedef std::unordered_map<Addr, AccessInfo> X86ISA::GpuTLB::AccessPatternTable

Definition at line 455 of file gpu_tlb.hh.

typedef std::list<GpuTlbEntry*> X86ISA::GpuTLB::EntryList

protected

Definition at line 81 of file gpu_tlb.hh.

typedef enum BaseTLB::Mode X86ISA::GpuTLB::Mode

Definition at line 109 of file gpu_tlb.hh.

typedef X86GPUTLBParams X86ISA::GpuTLB::Params

Definition at line 105 of file gpu_tlb.hh.

Member Enumeration Documentation

enum X86ISA::GpuTLB::tlbOutcome

Enumerator
TLB_HIT
TLB_MISS
PAGE_WALK
MISS_RETURN

Definition at line 252 of file gpu_tlb.hh.

Constructor & Destructor Documentation

X86ISA::GpuTLB::GpuTLB ( const Params * p )

Warning: : the set-associative version assumes you have a fixed page size of 4KB. If the page size is greather than 4KB (as defined in the TheISA::PageBytes), then there are various issues w/ the current implementation (you'd have the same 8KB page being replicated in different sets etc)

Definition at line 62 of file gpu_tlb.cc.

References accessDistance, allocationPolicy, assoc, clock, cprintf(), cpuSidePort, csprintf(), entryList, FA, freeList, hasMemSidePort, hitLatency, ArmISA::i, maxCoalescedReqs, memSidePort, missLatency1, missLatency2, SimObject::name(), numSets, outstandingReqs, setMask, X86ISA::Walker::setTLB(), size, tlb, walker, and X86ISA::x.

X86ISA::GpuTLB::~GpuTLB ( )

Definition at line 131 of file gpu_tlb.cc.

References translationReturnEvent.

Member Function Documentation

void X86ISA::GpuTLB::cleanup ( )

the higher level coalescer should retry if it has any pending requests.

Definition at line 1642 of file gpu_tlb.cc.

References cleanupQueue, cpuSidePort, ArmISA::i, outstandingReqs, and translationReturnEvent.

Tick X86ISA::GpuTLB::curCycle ( ) const

inline

Definition at line 102 of file gpu_tlb.hh.

References clock, and curTick().

void X86ISA::GpuTLB::demapPage	(	Addr	va,
		uint64_t	asn
	)

Definition at line 275 of file gpu_tlb.cc.

References entryList, freeList, lookupIt(), AlphaISA::PageShift, and setMask.

Tick X86ISA::GpuTLB::doMmuRegRead	(	ThreadContext *	tc,
		Packet *	pkt
	)

Tick X86ISA::GpuTLB::doMmuRegWrite	(	ThreadContext *	tc,
		Packet *	pkt
	)

void X86ISA::GpuTLB::dumpAll ( )

void X86ISA::GpuTLB::exitCallback ( )

Definition at line 1701 of file gpu_tlb.cc.

References accessDistance, avgReuseDistance, OutputDirectory::create(), ArmISA::i, SimObject::name(), simout, OutputStream::stream(), and TLBFootprint.

Tick X86ISA::GpuTLB::frequency ( ) const

inline

Definition at line 94 of file gpu_tlb.hh.

References clock, and SimClock::Frequency.

BaseMasterPort & X86ISA::GpuTLB::getMasterPort	(	const std::string &	if_name,
		PortID	idx = `InvalidPortID`
	)

virtual

Get a master port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic base master port.

Parameters

if_name	Port name
idx	Index in the case of a VectorPort

Returns: A reference to the given port

Reimplemented from MemObject.

Definition at line 152 of file gpu_tlb.cc.

References hasMemSidePort, memSidePort, and panic.

BaseSlavePort & X86ISA::GpuTLB::getSlavePort	(	const std::string &	if_name,
		PortID	idx = `InvalidPortID`
	)

virtual

Get a slave port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic base master port.

Parameters

if_name	Port name
idx	Index in the case of a VectorPort

Returns: A reference to the given port

Reimplemented from MemObject.

Definition at line 138 of file gpu_tlb.cc.

References cpuSidePort, and panic.

Walker * X86ISA::GpuTLB::getWalker ( )

Definition at line 938 of file gpu_tlb.cc.

References walker.

void X86ISA::GpuTLB::handleFuncTranslationReturn	(	PacketPtr	pkt,
		tlbOutcome	tlb_outcome
	)

handleFuncTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault returns.

It updates LRU, inserts the TLB entry on a miss depending on the allocation policy and does the required protection checks. It does NOT create a new packet to update the packet's addr; this is done in hsail-gpu code.

Definition at line 1416 of file gpu_tlb.cc.

References allocationPolicy, DPRINTF, Request::getVaddr(), insert(), ArmISA::mode, AlphaISA::PageBytes, pagingProtectionChecks(), X86ISA::GpuTLB::TranslationState::prefetch, Packet::req, roundDown(), safe_cast(), Packet::senderState, Request::setFlags(), Request::setPaddr(), X86ISA::GpuTLB::TranslationState::tc, TLB_HIT, X86ISA::GpuTLB::TranslationState::tlbEntry, X86ISA::GpuTLB::TranslationState::tlbMode, Request::UNCACHEABLE, X86ISA::vaddr, and X86ISA::GpuTlbEntry::valid.

void X86ISA::GpuTLB::handleTranslationReturn	(	Addr	virt_page_addr,
		tlbOutcome	tlb_outcome,
		PacketPtr	pkt
	)

handleTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault returns.

The latter calls handelHit with TLB miss as tlbOutcome.

At this point the packet carries an up-to-date tlbEntry pointer in its senderState. Next step is to do the paging protection checks.

Definition at line 1167 of file gpu_tlb.cc.

References allocationPolicy, cleanupEvent, cleanupQueue, cpuSidePort, curTick(), DPRINTF, Request::getVaddr(), insert(), Packet::isRequest(), Packet::makeTimingResponse(), ArmISA::mode, pagingProtectionChecks(), Packet::req, safe_cast(), EventManager::schedule(), Packet::senderState, Request::setFlags(), Request::setPaddr(), X86ISA::GpuTLB::TranslationState::tc, TLB_HIT, X86ISA::GpuTLB::TranslationState::tlbEntry, X86ISA::GpuTLB::TranslationState::tlbMode, Request::UNCACHEABLE, and X86ISA::vaddr.

Referenced by translationReturn().

GpuTlbEntry * X86ISA::GpuTLB::insert	(	Addr	vpn,
		GpuTlbEntry &	entry
	)

vpn holds the virtual page address The least significant bits are simply masked

Definition at line 168 of file gpu_tlb.cc.

References entryList, freeList, AlphaISA::PageShift, and setMask.

Referenced by handleFuncTranslationReturn(), handleTranslationReturn(), and translate().

void X86ISA::GpuTLB::invalidateAll ( )

Definition at line 237 of file gpu_tlb.cc.

References DPRINTF, entryList, freeList, ArmISA::i, and numSets.

void X86ISA::GpuTLB::invalidateNonGlobal ( )

Definition at line 257 of file gpu_tlb.cc.

References DPRINTF, entryList, freeList, ArmISA::i, and numSets.

void X86ISA::GpuTLB::issueTLBLookup ( PacketPtr pkt )

Do the TLB lookup for this coalesced request and schedule another event <TLB access="" latency>=""> cycles later.

Definition at line 1043 of file gpu_tlb.cc.

References accessCycles, curTick(), DPRINTF, Request::getVaddr(), globalNumTLBAccesses, globalNumTLBHits, globalNumTLBMisses, hitLatency, localCycles, lookup(), AlphaISA::PageBytes, panic, X86ISA::GpuTLB::TranslationState::prefetch, Packet::req, roundDown(), safe_cast(), EventManager::schedule(), Packet::senderState, ticks(), TLB_HIT, TLB_MISS, tlbLookup(), translationReturnEvent, updatePageFootprint(), and X86ISA::GpuTlbEntry::valid.

void X86ISA::GpuTLB::issueTranslation ( )

GpuTlbEntry * X86ISA::GpuTLB::lookup	(	Addr	va,
		bool	update_lru = `true`
	)

Definition at line 224 of file gpu_tlb.cc.

References entryList, lookupIt(), AlphaISA::PageShift, and setMask.

Referenced by issueTLBLookup(), tlbLookup(), and translate().

GpuTLB::EntryList::iterator X86ISA::GpuTLB::lookupIt	(	Addr	va,
		bool	update_lru = `true`
	)

protected

Definition at line 194 of file gpu_tlb.cc.

References DPRINTF, entryList, FA, AlphaISA::PageShift, and setMask.

Referenced by demapPage(), and lookup().

void X86ISA::GpuTLB::pagingProtectionChecks	(	ThreadContext *	tc,
		PacketPtr	pkt,
		GpuTlbEntry *	tlb_entry,
		Mode	mode
	)

Do Paging protection checks.

If we encounter a page fault, then an assertion is fired.

Definition at line 1133 of file gpu_tlb.cc.

References X86ISA::CPL0FlagBit, X86ISA::FlagShift, Request::getFlags(), X86ISA::MISCREG_CR0, X86ISA::MISCREG_M5_REG, ThreadContext::readMiscRegNoEffect(), Packet::req, X86ISA::StoreCheck, and BaseTLB::Write.

Referenced by handleFuncTranslationReturn(), and handleTranslationReturn().

void X86ISA::GpuTLB::printAccessPattern ( )

void X86ISA::GpuTLB::regStats ( )

virtual

Register statistics for this object.

Reimplemented from SimObject.

Definition at line 955 of file gpu_tlb.cc.

References accessCycles, avgReuseDistance, Stats::DataWrap< Derived, InfoProxyType >::desc(), globalNumTLBAccesses, globalNumTLBHits, globalNumTLBMisses, globalTLBMissRate, localCycles, localLatency, localNumTLBAccesses, localNumTLBHits, localNumTLBMisses, localTLBMissRate, SimObject::name(), Stats::DataWrap< Derived, InfoProxyType >::name(), numUniquePages, pageTableCycles, and ClockedObject::regStats().

void X86ISA::GpuTLB::serialize ( CheckpointOut & cp ) const

virtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 945 of file gpu_tlb.cc.

void X86ISA::GpuTLB::setConfigAddress ( uint32_t addr )

Definition at line 251 of file gpu_tlb.cc.

References X86ISA::addr, and configAddress.

Tick X86ISA::GpuTLB::ticks ( int numCycles ) const

inline

Definition at line 97 of file gpu_tlb.hh.

References clock.

Referenced by issueTLBLookup(), and translationReturn().

Tick X86ISA::GpuTLB::tickToCycles ( Tick val ) const

inline

Definition at line 103 of file gpu_tlb.hh.

References clock.

bool X86ISA::GpuTLB::tlbLookup	(	RequestPtr	req,
		ThreadContext *	tc,
		bool	update_stats
	)

TLB_lookup will only perform a TLB lookup returning true on a TLB hit and false on a TLB miss.

Many of the checks about different modes have been converted to assertions, since these parts of the code are not really used. On a hit it will update the LRU stack.

Definition at line 663 of file gpu_tlb.cc.

References DPRINTF, Request::getFlags(), Request::getVaddr(), localNumTLBAccesses, localNumTLBHits, localNumTLBMisses, lookup(), X86ISA::MISCREG_M5_REG, ThreadContext::readMiscRegNoEffect(), X86ISA::seg, X86ISA::SEGMENT_REG_MS, X86ISA::SegmentFlagMask, and X86ISA::vaddr.

Referenced by issueTLBLookup().

Fault X86ISA::GpuTLB::translate	(	RequestPtr	req,
		ThreadContext *	tc,
		Translation *	translation,
		Mode	mode,
		bool &	delayedResponse,
		bool	timing,
		int &	latency
	)

protected

Definition at line 711 of file gpu_tlb.cc.

References X86ISA::AddrSizeFlagBit, ArmISA::attr, X86ISA::base, bits(), ThreadContext::contextId(), X86ISA::CPL0FlagBit, DPRINTF, BaseTLB::Execute, X86ISA::expandDown, fatal, X86ISA::FlagShift, FullSystem, Request::getFlags(), Request::getPaddr(), ThreadContext::getProcessPtr(), Request::getSize(), Request::getVaddr(), hitLatency, insert(), ThreadContext::instAddr(), localNumTLBAccesses, localNumTLBHits, localNumTLBMisses, lookup(), X86ISA::MISCREG_APIC_BASE, X86ISA::MISCREG_CR0, X86ISA::MISCREG_CS_ATTR, X86ISA::MISCREG_M5_REG, X86ISA::MISCREG_SEG_ATTR(), X86ISA::MISCREG_SEG_BASE(), X86ISA::MISCREG_SEG_LIMIT(), X86ISA::MISCREG_SEG_SEL(), missLatency1, missLatency2, ArmISA::mode, NoFault, X86ISA::offset, X86ISA::p, X86ISA::PageBytes, BaseTLB::Read, ThreadContext::readMiscRegNoEffect(), X86ISA::seg, X86ISA::SEGMENT_REG_ES, X86ISA::SEGMENT_REG_HS, X86ISA::SEGMENT_REG_LS, X86ISA::SEGMENT_REG_MS, X86ISA::SEGMENT_REG_TSG, X86ISA::SegmentFlagMask, Request::setFlags(), Request::setPaddr(), size, X86ISA::StoreCheck, X86ISA::SYS_SEGMENT_REG_IDTR, translateInt(), Request::UNCACHEABLE, X86ISA::vaddr, X86ISA::GpuTlbEntry::valid, warn_once, BaseTLB::Write, and X86ISA::x86LocalAPICAddress().

Referenced by translateAtomic(), and translateTiming().

Fault X86ISA::GpuTLB::translateAtomic	(	RequestPtr	req,
		ThreadContext *	tc,
		Mode	mode,
		int &	latency
	)

Definition at line 914 of file gpu_tlb.cc.

References translate().

Fault X86ISA::GpuTLB::translateInt	(	RequestPtr	req,
		ThreadContext *	tc
	)

protected

Definition at line 288 of file gpu_tlb.cc.

Referenced by translate().

void X86ISA::GpuTLB::translateTiming	(	RequestPtr	req,
		ThreadContext *	tc,
		Translation *	translation,
		Mode	mode,
		int &	latency
	)

Definition at line 924 of file gpu_tlb.cc.

References X86ISA::GpuTLB::Translation::finish(), and translate().

void X86ISA::GpuTLB::translationReturn	(	Addr	virtPageAddr,
		tlbOutcome	outcome,
		PacketPtr	pkt
	)

A TLBEvent is scheduled after the TLB lookup and helps us take the appropriate actions: (e.g., update TLB on a hit, send request to lower level TLB on a miss, or start a page walk if this was the last-level TLB).

Here we take the appropriate actions based on the result of the TLB lookup.

There is a TLB below. Send the coalesced request. We actually send the very first packet of all the pending packets for this virtual page address.

we add an extra cycle in the return path of the translation requests in between the various TLB levels.

Definition at line 1252 of file gpu_tlb.cc.

References accessCycles, curTick(), DPRINTF, BaseTLB::Execute, ThreadContext::getProcessPtr(), Request::getVaddr(), handleTranslationReturn(), hasMemSidePort, localCycles, memSidePort, MISS_RETURN, missLatency2, X86ISA::p, PAGE_WALK, pageTableCycles, X86ISA::GpuTLB::TranslationState::prefetch, Packet::req, X86ISA::GpuTLB::TranslationState::reqCnt, safe_cast(), EventManager::schedule(), Packet::senderState, X86ISA::GpuTLB::TranslationState::tc, ticks(), TLB_HIT, TLB_MISS, X86ISA::TlbEntry(), X86ISA::GpuTLB::TranslationState::tlbEntry, X86ISA::GpuTLB::TranslationState::tlbMode, translationReturnEvent, X86ISA::GpuTLB::TLBEvent::updateOutcome(), and X86ISA::vaddr.

void X86ISA::GpuTLB::unserialize ( CheckpointIn & cp )

virtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 950 of file gpu_tlb.cc.

void X86ISA::GpuTLB::updatePageFootprint ( Addr virt_page_addr )

Definition at line 1666 of file gpu_tlb.cc.

References accessDistance, X86ISA::GpuTLB::AccessInfo::accessesPerPage, curTick(), X86ISA::GpuTLB::AccessInfo::lastTimeAccessed, localNumTLBAccesses, X86ISA::GpuTLB::AccessInfo::meanDistance, numUniquePages, X86ISA::GpuTLB::AccessInfo::sumDistance, TLBFootprint, X86ISA::GpuTLB::AccessInfo::totalReuseDistance, and Stats::ScalarBase< Derived, Stor >::value().

Referenced by issueTLBLookup().

void X86ISA::GpuTLB::updatePhysAddresses	(	Addr	virt_page_addr,
		GpuTlbEntry *	tlb_entry,
		Addr	phys_page_addr
	)

Friends And Related Function Documentation

friend class Walker

friend

Definition at line 79 of file gpu_tlb.hh.

Member Data Documentation

Stats::Scalar X86ISA::GpuTLB::accessCycles

Definition at line 219 of file gpu_tlb.hh.

Referenced by issueTLBLookup(), regStats(), and translationReturn().

bool X86ISA::GpuTLB::accessDistance

protected

Print out accessDistance stats.

One stat file per TLB.

Definition at line 171 of file gpu_tlb.hh.

Referenced by exitCallback(), GpuTLB(), and updatePageFootprint().

bool X86ISA::GpuTLB::allocationPolicy

protected

Allocation Policy: true if we always allocate on a hit, false otherwise.

Default is true.

Definition at line 160 of file gpu_tlb.hh.

Referenced by GpuTLB(), handleFuncTranslationReturn(), and handleTranslationReturn().

int X86ISA::GpuTLB::assoc

protected

Definition at line 147 of file gpu_tlb.hh.

Referenced by GpuTLB().

Stats::Scalar X86ISA::GpuTLB::avgReuseDistance

Definition at line 229 of file gpu_tlb.hh.

Referenced by exitCallback(), and regStats().

EventWrapper<GpuTLB, &GpuTLB::cleanup> X86ISA::GpuTLB::cleanupEvent

Definition at line 428 of file gpu_tlb.hh.

Referenced by handleTranslationReturn().

std::queue<Addr> X86ISA::GpuTLB::cleanupQueue

Definition at line 422 of file gpu_tlb.hh.

Referenced by cleanup(), and handleTranslationReturn().

int X86ISA::GpuTLB::clock

protected

Definition at line 89 of file gpu_tlb.hh.

Referenced by curCycle(), frequency(), GpuTLB(), ticks(), and tickToCycles().

uint32_t X86ISA::GpuTLB::configAddress

protected

Definition at line 83 of file gpu_tlb.hh.

Referenced by setConfigAddress(), and translateInt().

std::vector<CpuSidePort*> X86ISA::GpuTLB::cpuSidePort

Definition at line 317 of file gpu_tlb.hh.

Referenced by cleanup(), getSlavePort(), GpuTLB(), and handleTranslationReturn().

std::vector<EntryList> X86ISA::GpuTLB::entryList

protected

An entryList per set is the equivalent of an LRU stack; it's used to guide replacement decisions.

The head of the list contains the MRU TLB entry of the given set. If the freeList for this set is empty, the last element of the list is evicted (i.e., dropped on the floor).

Definition at line 189 of file gpu_tlb.hh.

Referenced by demapPage(), GpuTLB(), insert(), invalidateAll(), invalidateNonGlobal(), lookup(), and lookupIt().