40 #ifndef __ARCH_X86_PAGE_TABLE_WALKER_HH__
41 #define __ARCH_X86_PAGE_TABLE_WALKER_HH__
50 #include "params/X86PagetableWalker.hh"
116 RequestPtr _req,
bool _isFunctional =
false) :
125 bool _isTiming =
false);
213 #endif // __ARCH_X86_PAGE_TABLE_WALKER_HH__
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
void setupWalk(Addr vaddr)
bool sendTiming(WalkerState *sendingState, PacketPtr pkt)
void recvReqRetry()
Called by the slave port if sendTimingReq was called on this master port (causing recvTimingReq to be...
bool recvPacket(PacketPtr pkt)
const PortID InvalidPortID
X86PagetableWalkerParams Params
Walker(const Params *params)
const Params * params() const
WalkerSenderState(WalkerState *_senderWalk)
WalkerPort(const std::string &_name, Walker *_walker)
TLB::Translation * translation
ThreadContext is the external interface to all thread state for anything outside of the CPU...
void initState(ThreadContext *_tc, BaseTLB::Mode _mode, bool _isTiming=false)
Fault startFunctional(ThreadContext *_tc, Addr &addr, unsigned &logBytes, BaseTLB::Mode mode)
Fault start(ThreadContext *_tc, BaseTLB::Translation *translation, RequestPtr req, BaseTLB::Mode mode)
Fault startFunctional(Addr &addr, unsigned &logBytes)
TlbEntry(Addr asn, Addr _vaddr, Addr _paddr, bool uncacheable, bool read_only)
EventWrapper< Walker,&Walker::startWalkWrapper > startWalkWrapperEvent
Event used to call startWalkWrapper.
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
A virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a MemObject that sees the packet.
std::vector< PacketPtr > writes
virtual const std::string name() const
Declaration of the Packet class.
BaseMasterPort & getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a master port with a given name and index.
EndBitUnion(PageTableEntry) struct TlbEntry Addr vaddr
Fault stepWalk(PacketPtr &write)
The MemObject class extends the ClockedObject with accessor functions to get its master and slave por...
A BaseMasterPort is a protocol-agnostic master port, responsible only for the structural connection t...
std::list< WalkerState * > currStates
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the slave port.
const SimObjectParams * _params
Cached copy of the object parameters.
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
WalkerState(Walker *_walker, BaseTLB::Translation *_translation, RequestPtr _req, bool _isFunctional=false)
Fault pageFault(bool present)
std::shared_ptr< FaultBase > Fault
bool recvTimingResp(PacketPtr pkt)