#include <iostream>
#include <string>
#include <vector>
#include "base/bitunion.hh"
#include "base/types.hh"
#include "base/trie.hh"
#include "arch/x86/system.hh"
#include "debug/MMU.hh"
Go to the source code of this file.
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| X86ISA |
| This is exposed globally, independent of the ISA.
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| X86ISA::longl1 |
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Bitfield< 29, 21 > | X86ISA::longl2 |
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Bitfield< 38, 30 > | X86ISA::longl3 |
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Bitfield< 47, 39 > | X86ISA::longl4 |
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Bitfield< 20, 12 > | X86ISA::pael1 |
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Bitfield< 29, 21 > | X86ISA::pael2 |
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Bitfield< 31, 30 > | X86ISA::pael3 |
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Bitfield< 21, 12 > | X86ISA::norml1 |
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Bitfield< 31, 22 > | X86ISA::norml2 |
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Bitfield< 51, 12 > | X86ISA::base |
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Bitfield< 11, 9 > | X86ISA::avl |
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Bitfield< 8 > | X86ISA::g |
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Bitfield< 7 > | X86ISA::ps |
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Bitfield< 6 > | X86ISA::d |
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Bitfield< 5 > | X86ISA::a |
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Bitfield< 4 > | X86ISA::pcd |
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Bitfield< 3 > | X86ISA::pwt |
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Bitfield< 2 > | X86ISA::u |
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Bitfield< 1 > | X86ISA::w |
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Bitfield< 0 > | X86ISA::p |
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EndBitUnion(PageTableEntry)
struct TlbEntry Addr | X86ISA::vaddr |
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unsigned | X86ISA::logBytes |
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bool | X86ISA::writable |
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bool | X86ISA::user |
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bool | X86ISA::uncacheable |
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bool | X86ISA::global |
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bool | X86ISA::patBit |
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bool | X86ISA::noExec |
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uint64_t | X86ISA::lruSeq |
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TlbEntryTrie::Handle | X86ISA::trieHandle |
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const std::vector< uint8_t > | X86ISA::PageTableLayout = {9, 9, 9, 9} |
| The size of each level of the page table expressed in base 2 logarithmic values. More...
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