gem5
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Page table operations specific to x86 ISA. More...
#include <pagetable.hh>
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void | setPTEFields (PageTableEntry &PTE, uint64_t flags=0) |
Addr | getBasePtr (ThreadContext *tc) |
returns the physical memory address of the page table More... | |
Addr | getPnum (PageTableEntry PTE) |
returns the page number out of a page table entry More... | |
bool | isUncacheable (const PageTableEntry PTE) |
bool | isReadOnly (PageTableEntry PTE) |
void | setPnum (PageTableEntry &PTE, Addr paddr) |
sets the page number in a page table entry More... | |
std::vector< uint64_t > | getOffsets (Addr vaddr) |
returns the offsets to index in every level of a page table, contained in a virtual address More... | |
Page table operations specific to x86 ISA.
Indended to be used as parameter of MultiLevelPageTable.
Definition at line 171 of file pagetable.hh.
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returns the physical memory address of the page table
Definition at line 183 of file pagetable.hh.
References DPRINTF, and X86ISA::pageTablePhysAddr.
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returns the offsets to index in every level of a page table, contained in a virtual address
Definition at line 215 of file pagetable.hh.
References X86ISA::addr.
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returns the page number out of a page table entry
Definition at line 191 of file pagetable.hh.
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Definition at line 201 of file pagetable.hh.
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Definition at line 196 of file pagetable.hh.
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sets the page number in a page table entry
Definition at line 207 of file pagetable.hh.
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Definition at line 174 of file pagetable.hh.
References X86ISA::PTE_NotPresent, X86ISA::PTE_ReadOnly, X86ISA::PTE_Supervisor, and X86ISA::PTE_Uncacheable.