This class implements an in-memory multi-level page table that can be configured to follow ISA specifications. More...

#include <multi_level_page_table.hh>

Inheritance diagram for MultiLevelPageTable< ISAOps >:

Public Member Functions
	MultiLevelPageTable (const std::string &__name, uint64_t _pid, System *_sys)

	~MultiLevelPageTable ()

void	initState (ThreadContext *tc) override

void	map (Addr vaddr, Addr paddr, int64_t size, uint64_t flags=0) override
	Maps a virtual memory region to a physical memory region. More...

void	remap (Addr vaddr, int64_t size, Addr new_vaddr) override

void	unmap (Addr vaddr, int64_t size) override

bool	isUnmapped (Addr vaddr, int64_t size) override
	Check if any pages in a region are already allocated. More...

bool	lookup (Addr vaddr, TheISA::TlbEntry &entry) override
	Lookup function. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from PageTableBase
	PageTableBase (const std::string &__name, uint64_t _pid, Addr _pageSize=TheISA::PageBytes)

virtual	~PageTableBase ()

const std::string	name () const

Addr	pageAlign (Addr a)

Addr	pageOffset (Addr a)

bool	translate (Addr vaddr, Addr &paddr)
	Translate function. More...

bool	translate (Addr vaddr)
	Simplified translate function (just check for translation) More...

Fault	translate (RequestPtr req)
	Perform a translation on the memory request, fills in paddr field of req. More...

void	updateCache (Addr vaddr, TheISA::TlbEntry entry)
	Update the page table cache. More...

void	eraseCacheEntry (Addr vaddr)
	Erase an entry from the page table cache. More...

virtual void	getMappings (std::vector< std::pair< Addr, Addr >> *addr_mappings)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Private Member Functions
bool	walk (Addr vaddr, bool allocate, Addr &PTE_addr)
	Method for walking the page table. More...

Private Attributes
ISAOps	pTableISAOps
	ISA specific operations. More...

System *	system
	Pointer to System object. More...

Addr	basePtr
	Physical address to the last level of the page table. More...

const std::vector< uint8_t >	logLevelSize
	Vector with sizes of all levels in base 2 logarithmic. More...

const uint64_t	numLevels
	Number of levels contained by the page table. More...

Additional Inherited Members
Public Types inherited from PageTableBase
enum	MappingFlags : uint32_t { Zero = 0, Clobber = 1, NotPresent = 2, Uncacheable = 4, ReadOnly = 8 }

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Get the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)

static void	unserializeGlobals (CheckpointIn &cp)

Static Public Attributes inherited from Serializable
static int	ckptCount = 0

static int	ckptMaxCount = 0

static int	ckptPrevCount = -1

Protected Attributes inherited from PageTableBase
struct cacheElement	pTableCache [3]

const Addr	pageSize

const Addr	offsetMask

const uint64_t	pid

const std::string	_name

Detailed Description

template<class ISAOps>
class MultiLevelPageTable< ISAOps >

This class implements an in-memory multi-level page table that can be configured to follow ISA specifications.

It can be used instead of the PageTable class in SE mode to allow CPU models (e.g. X86KvmCPU) to do a normal page table walk.

To reduce memory required to store the page table, a multi-level page table stores its translations similarly with a radix tree. Let n be the number of levels and {Ln, Ln-1, ..., L1, L0} a set that specifies the number of entries for each level as base 2 logarithm values. A multi-level page table will store its translations at level 0 (the leaves of the tree) and it will be layed out in memory in the following way:

                         +------------------------------+

level n |Ln-1_E0|Ln-1_E1|...|Ln-1_E2^Ln| +---------------------------—+ / \ +---------------------—+ +---------------------—+ level n-1 |Ln-2_E0|...|Ln-2_E2^Ln-1| |Ln-2_E0|...|Ln-2_E2^Ln-1| +---------------------—+ +---------------------—+ / \ / \ / / \ +---------------—+ +---------—+ +---------—+ level 1 |L0_E1|...|L0_E2^L1| |...|L0_E2^L1| ... |...|L0_E2^L1| +---------------—+ +---------—+ +---------—+ , where +---------------------------—+ |Lk-1_E0|Lk-1_E1|...|Lk-1_E2^Lk| +---------------------------—+ is a level k entry that holds 2^Lk entries in Lk-1 level.

Essentially, a level n entry will contain 2^Ln level n-1 entries, a level n-1 entry will hold 2^Ln-1 level n-2 entries etc.

The virtual address is split into offsets that index into the different levels of the page table.

+-----------------------------—+ |LnOffset|...|L1Offset|PageOffset| +-----------------------------—+

For example L0Offset will be formed by the bits in range [log2(PageOffset), log2(PageOffset)+L0].

For every level of the page table, from n to 1, the base address of the entry is loaded, the offset in the virtual address for that particular level is used to index into the entry which will reveal the memory address of the entry in the next level.

See Also: MultiLevelPageTable

Definition at line 104 of file multi_level_page_table.hh.

Constructor & Destructor Documentation

template<class ISAOps >

MultiLevelPageTable< ISAOps >::MultiLevelPageTable	(	const std::string &	__name,
		uint64_t	_pid,
		System *	_sys
	)

Definition at line 49 of file multi_level_page_table_impl.hh.

template<class ISAOps >

MultiLevelPageTable< ISAOps >::~MultiLevelPageTable ( )

Definition at line 58 of file multi_level_page_table_impl.hh.

Member Function Documentation

template<class ISAOps >

void MultiLevelPageTable< ISAOps >::initState ( ThreadContext * tc )

overridevirtual

Implements PageTableBase.

Definition at line 64 of file multi_level_page_table_impl.hh.

References DPRINTF, floorLog2(), PortProxy::memsetBlob(), MipsISA::p, AlphaISA::PageShift, and ArmISA::system.

template<class ISAOps >

bool MultiLevelPageTable< ISAOps >::isUnmapped	(	Addr	vaddr,
		int64_t	size
	)

overridevirtual

Check if any pages in a region are already allocated.

Parameters

vaddr	The starting virtual address of the region.
size	The length of the region.

Returns: True if no pages in the region are mapped.

Implements PageTableBase.

Definition at line 256 of file multi_level_page_table_impl.hh.

References MipsISA::p, PortProxy::read(), and ArmISA::system.

template<class ISAOps>

bool MultiLevelPageTable< ISAOps >::lookup	(	Addr	vaddr,
		TheISA::TlbEntry &	entry
	)

overridevirtual

Lookup function.

Parameters

vaddr The virtual address.

Returns: entry The page table entry corresponding to vaddr.

Implements PageTableBase.

Definition at line 276 of file multi_level_page_table_impl.hh.

References DPRINTF, MipsISA::p, AlphaISA::PageShift, PortProxy::read(), ArmISA::system, and X86ISA::TlbEntry().

template<class ISAOps >

void MultiLevelPageTable< ISAOps >::map	(	Addr	vaddr,
		Addr	paddr,
		int64_t	size,
		uint64_t	flags = `0`
	)

overridevirtual

Maps a virtual memory region to a physical memory region.

Parameters

vaddr	The starting virtual address of the region.
paddr	The starting physical address where the region is mapped.
size	The length of the region.
flags	Generic mapping flags that can be set by or-ing values from MappingFlags enum.

Implements PageTableBase.

Definition at line 136 of file multi_level_page_table_impl.hh.

References DPRINTF, fatal, MipsISA::p, AlphaISA::PageShift, X86ISA::PTE_NotPresent, X86ISA::PTE_ReadOnly, X86ISA::PTE_Uncacheable, PortProxy::read(), ArmISA::system, X86ISA::TlbEntry(), and PortProxy::write().