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gem5
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#include <deriv.hh>
Public Member Functions | |
| DerivO3CPU (DerivO3CPUParams *p) | |
 Public Member Functions inherited from FullO3CPU< O3CPUImpl > | |
| FullO3CPU (DerivO3CPUParams *params) | |
| Constructs a CPU with the given parameters. More... | |
| ~FullO3CPU () | |
| Destructor. More... | |
| void | regStats () override |
| Registers statistics. More... | |
| void | regProbePoints () override |
| Register probe points. More... | |
| void | demapPage (Addr vaddr, uint64_t asn) |
| void | demapInstPage (Addr vaddr, uint64_t asn) |
| void | demapDataPage (Addr vaddr, uint64_t asn) |
| void | tick () |
| Ticks CPU, calling tick() on each stage, and checking the overall activity to see if the CPU should deschedule itself. More... | |
| void | init () override |
| Initialize the CPU. More... | |
| void | startup () override |
| int | numActiveThreads () |
| Returns the Number of Active Threads in the CPU. More... | |
| void | activateThread (ThreadID tid) |
| Add Thread to Active Threads List. More... | |
| void | deactivateThread (ThreadID tid) |
| Remove Thread from Active Threads List. More... | |
| void | insertThread (ThreadID tid) |
| Setup CPU to insert a thread's context. More... | |
| void | removeThread (ThreadID tid) |
| Remove all of a thread's context from CPU. More... | |
| Counter | totalInsts () const override |
| Count the Total Instructions Committed in the CPU. More... | |
| Counter | totalOps () const override |
| Count the Total Ops (including micro ops) committed in the CPU. More... | |
| void | activateContext (ThreadID tid) override |
| Add Thread to Active Threads List. More... | |
| void | suspendContext (ThreadID tid) override |
| Remove Thread from Active Threads List. More... | |
| void | haltContext (ThreadID tid) override |
| Remove Thread from Active Threads List && Remove Thread Context from CPU. More... | |
| void | updateThreadPriority () |
| Update The Order In Which We Process Threads. More... | |
| bool | isDraining () const |
| Is the CPU draining? More... | |
| void | serializeThread (CheckpointOut &cp, ThreadID tid) const override |
| void | unserializeThread (CheckpointIn &cp, ThreadID tid) override |
| void | syscall (int64_t callnum, ThreadID tid, Fault *fault) |
| Executes a syscall. More... | |
| DrainState | drain () override |
| Starts draining the CPU's pipeline of all instructions in order to stop all memory accesses. More... | |
| void | drainResume () override |
| Resumes execution after a drain. More... | |
| void | commitDrained (ThreadID tid) |
| Commit has reached a safe point to drain a thread. More... | |
| void | switchOut () override |
| Switches out this CPU. More... | |
| void | takeOverFrom (BaseCPU *oldCPU) override |
| Takes over from another CPU. More... | |
| void | verifyMemoryMode () const override |
| InstSeqNum | getAndIncrementInstSeq () |
| Get the current instruction sequence number, and increment it. More... | |
| void | trap (const Fault &fault, ThreadID tid, const StaticInstPtr &inst) |
| Traps to handle given fault. More... | |
| Fault | hwrei (ThreadID tid) |
| HW return from error interrupt. More... | |
| bool | simPalCheck (int palFunc, ThreadID tid) |
| Fault | getInterrupts () |
| Returns the Fault for any valid interrupt. More... | |
| void | processInterrupts (const Fault &interrupt) |
| Processes any an interrupt fault. More... | |
| void | halt () |
| Halts the CPU. More... | |
| TheISA::MiscReg | readMiscRegNoEffect (int misc_reg, ThreadID tid) const |
| Register accessors. More... | |
| TheISA::MiscReg | readMiscReg (int misc_reg, ThreadID tid) |
| Reads a misc. More... | |
| void | setMiscRegNoEffect (int misc_reg, const TheISA::MiscReg &val, ThreadID tid) |
| Sets a miscellaneous register. More... | |
| void | setMiscReg (int misc_reg, const TheISA::MiscReg &val, ThreadID tid) |
| Sets a misc. More... | |
| uint64_t | readIntReg (int reg_idx) |
| TheISA::FloatReg | readFloatReg (int reg_idx) |
| TheISA::FloatRegBits | readFloatRegBits (int reg_idx) |
| TheISA::CCReg | readCCReg (int reg_idx) |
| void | setIntReg (int reg_idx, uint64_t val) |
| void | setFloatReg (int reg_idx, TheISA::FloatReg val) |
| void | setFloatRegBits (int reg_idx, TheISA::FloatRegBits val) |
| void | setCCReg (int reg_idx, TheISA::CCReg val) |
| uint64_t | readArchIntReg (int reg_idx, ThreadID tid) |
| float | readArchFloatReg (int reg_idx, ThreadID tid) |
| uint64_t | readArchFloatRegInt (int reg_idx, ThreadID tid) |
| TheISA::CCReg | readArchCCReg (int reg_idx, ThreadID tid) |
| void | setArchIntReg (int reg_idx, uint64_t val, ThreadID tid) |
| Architectural register accessors. More... | |
| void | setArchFloatReg (int reg_idx, float val, ThreadID tid) |
| void | setArchFloatRegInt (int reg_idx, uint64_t val, ThreadID tid) |
| void | setArchCCReg (int reg_idx, TheISA::CCReg val, ThreadID tid) |
| void | pcState (const TheISA::PCState &newPCState, ThreadID tid) |
| Sets the commit PC state of a specific thread. More... | |
| TheISA::PCState | pcState (ThreadID tid) |
| Reads the commit PC state of a specific thread. More... | |
| Addr | instAddr (ThreadID tid) |
| Reads the commit PC of a specific thread. More... | |
| MicroPC | microPC (ThreadID tid) |
| Reads the commit micro PC of a specific thread. More... | |
| Addr | nextInstAddr (ThreadID tid) |
| Reads the next PC of a specific thread. More... | |
| void | squashFromTC (ThreadID tid) |
| Initiates a squash of all in-flight instructions for a given thread. More... | |
| ListIt | addInst (DynInstPtr &inst) |
| Function to add instruction onto the head of the list of the instructions. More... | |
| void | instDone (ThreadID tid, DynInstPtr &inst) |
| Function to tell the CPU that an instruction has completed. More... | |
| void | removeFrontInst (DynInstPtr &inst) |
| Remove an instruction from the front end of the list. More... | |
| void | removeInstsNotInROB (ThreadID tid) |
| Remove all instructions that are not currently in the ROB. More... | |
| void | removeInstsUntil (const InstSeqNum &seq_num, ThreadID tid) |
| Remove all instructions younger than the given sequence number. More... | |
| void | squashInstIt (const ListIt &instIt, ThreadID tid) |
| Removes the instruction pointed to by the iterator. More... | |
| void | cleanUpRemovedInsts () |
| Cleans up all instructions on the remove list. More... | |
| void | dumpInsts () |
| Debug function to print all instructions on the list. More... | |
| void | activityThisCycle () |
| Records that there was time buffer activity this cycle. More... | |
| void | activateStage (const StageIdx idx) |
| Changes a stage's status to active within the activity recorder. More... | |
| void | deactivateStage (const StageIdx idx) |
| Changes a stage's status to inactive within the activity recorder. More... | |
| void | wakeCPU () |
| Wakes the CPU, rescheduling the CPU if it's not already active. More... | |
| virtual void | wakeup (ThreadID tid) override |
| ThreadID | getFreeTid () |
| Gets a free thread id. More... | |
| ThreadContext * | tcBase (ThreadID tid) |
| Returns a pointer to a thread context. More... | |
| Fault | read (RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, int load_idx) |
| CPU read function, forwards read to LSQ. More... | |
| Fault | write (RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, uint8_t *data, int store_idx) |
| CPU write function, forwards write to LSQ. More... | |
| MasterPort & | getInstPort () override |
| Used by the fetch unit to get a hold of the instruction port. More... | |
| MasterPort & | getDataPort () override |
| Get the dcache port (used to find block size for translations). More... | |
| Public Member Functions inherited from BaseO3CPU | |
| BaseO3CPU (BaseCPUParams *params) | |
| void | regStats () |
Additional Inherited Members | |
| Public Types inherited from FullO3CPU< O3CPUImpl > | |
| enum | Status |
| enum | StageIdx |
| Enum to give each stage a specific index, so when calling activateStage() or deactivateStage(), they can specify which stage is being activated/deactivated. More... | |
| typedef O3CPUImpl::CPUPol | CPUPolicy |
| typedef O3CPUImpl::DynInstPtr | DynInstPtr |
| typedef O3CPUImpl::O3CPU | O3CPU |
| typedef O3ThreadState< O3CPUImpl > | ImplState |
| typedef O3ThreadState< O3CPUImpl > | Thread |
| typedef std::list< DynInstPtr > ::iterator | ListIt |
| typedef CPUPolicy::TimeStruct | TimeStruct |
| Typedefs from the Impl to get the structs that each of the time buffers should use. More... | |
| typedef CPUPolicy::FetchStruct | FetchStruct |
| typedef CPUPolicy::DecodeStruct | DecodeStruct |
| typedef CPUPolicy::RenameStruct | RenameStruct |
| typedef CPUPolicy::IEWStruct | IEWStruct |
| Static Public Member Functions inherited from BaseCPU | |
| static int | numSimulatedInsts () |
| static int | numSimulatedOps () |
| static void | wakeup (ThreadID tid) |
| Public Attributes inherited from FullO3CPU< O3CPUImpl > | |
| TheISA::TLB * | itb |
| TheISA::TLB * | dtb |
| Status | _status |
| Overall CPU status. More... | |
| ProbePointArg< PacketPtr > * | ppInstAccessComplete |
| ProbePointArg< std::pair < DynInstPtr, PacketPtr > > * | ppDataAccessComplete |
| int | instcount |
| Count of total number of dynamic instructions in flight. More... | |
| std::list< DynInstPtr > | instList |
| List of all the instructions in flight. More... | |
| std::queue< ListIt > | removeList |
| List of all the instructions that will be removed at the end of this cycle. More... | |
| bool | removeInstsThisCycle |
| Records if instructions need to be removed this cycle due to being retired or squashed. More... | |
| TimeBuffer< TimeStruct > | timeBuffer |
| The main time buffer to do backwards communication. More... | |
| TimeBuffer< FetchStruct > | fetchQueue |
| The fetch stage's instruction queue. More... | |
| TimeBuffer< DecodeStruct > | decodeQueue |
| The decode stage's instruction queue. More... | |
| TimeBuffer< RenameStruct > | renameQueue |
| The rename stage's instruction queue. More... | |
| TimeBuffer< IEWStruct > | iewQueue |
| The IEW stage's instruction queue. More... | |
| InstSeqNum | globalSeqNum |
| The global sequence number counter. More... | |
| Checker< O3CPUImpl > * | checker |
| Pointer to the checker, which can dynamically verify instruction results at run time. More... | |
| System * | system |
| Pointer to the system. More... | |
| std::vector< Thread * > | thread |
| Pointers to all of the threads in the CPU. More... | |
| std::list< int > | cpuWaitList |
| Threads Scheduled to Enter CPU. More... | |
| Cycles | lastRunningCycle |
| The cycle that the CPU was last running, used for statistics. More... | |
| Tick | lastActivatedCycle |
| The cycle that the CPU was last activated by a new thread. More... | |
| std::map< ThreadID, unsigned > | threadMap |
| Mapping for system thread id to cpu id. More... | |
| std::vector< ThreadID > | tids |
| Available thread ids in the cpu. More... | |
| Stats::Scalar | timesIdled |
| Stat for total number of times the CPU is descheduled. More... | |
| Stats::Scalar | idleCycles |
| Stat for total number of cycles the CPU spends descheduled. More... | |
| Stats::Scalar | quiesceCycles |
| Stat for total number of cycles the CPU spends descheduled due to a quiesce operation or waiting for an interrupt. More... | |
| Stats::Vector | committedInsts |
| Stat for the number of committed instructions per thread. More... | |
| Stats::Vector | committedOps |
| Stat for the number of committed ops (including micro ops) per thread. More... | |
| Stats::Formula | cpi |
| Stat for the CPI per thread. More... | |
| Stats::Formula | totalCpi |
| Stat for the total CPI. More... | |
| Stats::Formula | ipc |
| Stat for the IPC per thread. More... | |
| Stats::Formula | totalIpc |
| Stat for the total IPC. More... | |
| Stats::Scalar | intRegfileReads |
| Stats::Scalar | intRegfileWrites |
| Stats::Scalar | fpRegfileReads |
| Stats::Scalar | fpRegfileWrites |
| Stats::Scalar | ccRegfileReads |
| Stats::Scalar | ccRegfileWrites |
| Stats::Scalar | miscRegfileReads |
| Stats::Scalar | miscRegfileWrites |
| Protected Attributes inherited from FullO3CPU< O3CPUImpl > | |
| CPUPolicy::Fetch | fetch |
| The fetch stage. More... | |
| CPUPolicy::Decode | decode |
| The decode stage. More... | |
| CPUPolicy::Rename | rename |
| The dispatch stage. More... | |
| CPUPolicy::IEW | iew |
| The issue/execute/writeback stages. More... | |
| CPUPolicy::Commit | commit |
| The commit stage. More... | |
| PhysRegFile | regFile |
| The register file. More... | |
| CPUPolicy::FreeList | freeList |
| The free list. More... | |
| CPUPolicy::RenameMap | renameMap [O3CPUImpl::MaxThreads] |
| The rename map. More... | |
| CPUPolicy::RenameMap | commitRenameMap [O3CPUImpl::MaxThreads] |
| The commit rename map. More... | |
| CPUPolicy::ROB | rob |
| The re-order buffer. More... | |
| std::list< ThreadID > | activeThreads |
| Active Threads List. More... | |
| Scoreboard | scoreboard |
| Integer Register Scoreboard. More... | |
| std::vector< TheISA::ISA * > | isa |
| IcachePort | icachePort |
| Instruction port. More... | |
| DcachePort | dcachePort |
| Data port. More... | |