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gem5
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The memory-side port extends the base cache master port with access functions for functional, atomic and timing snoops. More...
#include <cache.hh>
Public Member Functions | |
| MemSidePort (const std::string &_name, Cache *_cache, const std::string &_label) | |
Protected Member Functions | |
| virtual void | recvTimingSnoopReq (PacketPtr pkt) |
| virtual bool | recvTimingResp (PacketPtr pkt) |
| virtual Tick | recvAtomicSnoop (PacketPtr pkt) |
| virtual void | recvFunctionalSnoop (PacketPtr pkt) |
Private Attributes | |
| CacheReqPacketQueue | _reqQueue |
| The cache-specific queue. More... | |
| SnoopRespPacketQueue | _snoopRespQueue |
| Cache * | cache |
The memory-side port extends the base cache master port with access functions for functional, atomic and timing snoops.
| Cache::MemSidePort::MemSidePort | ( | const std::string & | _name, |
| Cache * | _cache, | ||
| const std::string & | _label | ||
| ) |
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