gem5
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The CPU-side port extends the base cache slave port with access functions for functional, atomic and timing requests. More...
#include <cache.hh>
Public Member Functions | |
CpuSidePort (const std::string &_name, Cache *_cache, const std::string &_label) | |
Protected Member Functions | |
virtual bool | recvTimingSnoopResp (PacketPtr pkt) |
virtual bool | recvTimingReq (PacketPtr pkt) |
virtual Tick | recvAtomic (PacketPtr pkt) |
virtual void | recvFunctional (PacketPtr pkt) |
virtual AddrRangeList | getAddrRanges () const |
Private Attributes | |
Cache * | cache |
The CPU-side port extends the base cache slave port with access functions for functional, atomic and timing requests.
Cache::CpuSidePort::CpuSidePort | ( | const std::string & | _name, |
Cache * | _cache, | ||
const std::string & | _label | ||
) |
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protectedvirtual |
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protectedvirtual |
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protectedvirtual |
Definition at line 2539 of file cache.cc.
References BaseCache::blocked, Packet::isExpressSnoop(), and M5_VAR_USED.
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protectedvirtual |
Definition at line 2201 of file cache.cc.
References cache, and Cache::recvTimingSnoopResp().
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private |
Definition at line 87 of file cache.hh.
Referenced by recvTimingSnoopResp().