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| | MicroIntRegOp (const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, RegIndex _urc, int32_t _shiftAmt, ArmShiftType _shiftType) |
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| | MicroOp (const char *mnem, ExtMachInst machInst, OpClass __opClass) |
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| | PredOp (const char *mnem, ExtMachInst _machInst, OpClass __opClass) |
| | Constructor. More...
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| int32_t | shift_rm_imm (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const |
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| int32_t | shift_rm_rs (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const |
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| bool | shift_carry_imm (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const |
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| bool | shift_carry_rs (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const |
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| int64_t | shiftReg64 (uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) const |
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| int64_t | extendReg64 (uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) const |
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| | ArmStaticInst (const char *mnem, ExtMachInst _machInst, OpClass __opClass) |
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| void | printReg (std::ostream &os, int reg) const |
| | Print a register name for disassembly given the unique dependence tag number (FP or int). More...
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| void | printMnemonic (std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const |
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| void | printTarget (std::ostream &os, Addr target, const SymbolTable *symtab) const |
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| void | printCondition (std::ostream &os, unsigned code, bool noImplicit=false) const |
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| void | printMemSymbol (std::ostream &os, const SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const |
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| void | printShiftOperand (std::ostream &os, IntRegIndex rm, bool immShift, uint32_t shiftAmt, IntRegIndex rs, ArmShiftType type) const |
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| void | printExtendOperand (bool firstOperand, std::ostream &os, IntRegIndex rm, ArmExtendType type, int64_t shiftAmt) const |
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| void | printDataInst (std::ostream &os, bool withImm) const |
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| void | printDataInst (std::ostream &os, bool withImm, bool immShift, bool s, IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, uint64_t imm) const |
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| void | advancePC (PCState &pcState) const |
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| std::string | generateDisassembly (Addr pc, const SymbolTable *symtab) const |
| | Internal function to generate disassembly string. More...
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| Fault | disabledFault () const |
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| Fault | advSIMDFPAccessTrap64 (ExceptionLevel el) const |
| | Trap an access to Advanced SIMD or FP registers due to access control bits. More...
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| Fault | checkFPAdvSIMDTrap64 (ThreadContext *tc, CPSR cpsr) const |
| | Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3. More...
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| Fault | checkFPAdvSIMDEnabled64 (ThreadContext *tc, CPSR cpsr, CPACR cpacr) const |
| | Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and CPTR_EL3. More...
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| Fault | checkAdvSIMDOrFPEnabled32 (ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) const |
| | Check if a VFP/SIMD access from aarch32 should be allowed. More...
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| CPSR | getPSTATEFromPSR (ThreadContext *tc, CPSR cpsr, CPSR spsr) const |
| | Get the new PSTATE from a SPSR register in preparation for an exception return. More...
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| | StaticInst (const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) |
| | Constructor. More...
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| enum | { MaxInstSrcRegs = TheISA::MaxInstSrcRegs,
MaxInstDestRegs = TheISA::MaxInstDestRegs
} |
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| typedef TheISA::ExtMachInst | ExtMachInst |
| | Binary extended machine instruction type. More...
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| typedef TheISA::RegIndex | RegIndex |
| | Logical register index type. More...
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| void | advancePC (PCState &pcState) const |
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| virtual void | annotateFault (ArmFault *fault) |
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| int8_t | numCCDestRegs () const |
| | Number of coprocesor destination regs. More...
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| void | setFirstMicroop () |
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| void | setLastMicroop () |
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| void | setDelayedCommit () |
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| void | setFlag (Flags f) |
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| OpClass | opClass () const |
| | Operation class. Used to select appropriate function unit in issue. More...
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| RegIndex | destRegIdx (int i) const |
| | Return logical index (architectural reg num) of i'th destination reg. More...
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| RegIndex | srcRegIdx (int i) const |
| | Return logical index (architectural reg num) of i'th source reg. More...
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| virtual const StaticInstPtr & | eaCompInst () const |
| | Memory references only: returns "fake" instruction representing the effective address part of the memory operation. More...
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| virtual const StaticInstPtr & | memAccInst () const |
| | Memory references only: returns "fake" instruction representing the memory access part of the memory operation. More...
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| virtual | ~StaticInst () |
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| virtual Fault | execute (ExecContext *xc, Trace::InstRecord *traceData) const =0 |
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| virtual Fault | eaComp (ExecContext *xc, Trace::InstRecord *traceData) const |
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| virtual Fault | initiateAcc (ExecContext *xc, Trace::InstRecord *traceData) const |
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| virtual Fault | completeAcc (Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const |
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| virtual void | advancePC (TheISA::PCState &pcState) const =0 |
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| virtual StaticInstPtr | fetchMicroop (MicroPC upc) const |
| | Return the microop that goes with a particular micropc. More...
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| virtual TheISA::PCState | branchTarget (const TheISA::PCState &pc) const |
| | Return the target address for a PC-relative branch. More...
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| virtual TheISA::PCState | branchTarget (ThreadContext *tc) const |
| | Return the target address for an indirect branch (jump). More...
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| bool | hasBranchTarget (const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const |
| | Return true if the instruction is a control transfer, and if so, return the target address as well. More...
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| virtual const std::string & | disassemble (Addr pc, const SymbolTable *symtab=0) const |
| | Return string representation of disassembled instruction. More...
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| void | printFlags (std::ostream &outs, const std::string &separator) const |
| | Print a separator separated list of this instruction's set flag names on the given stream. More...
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| std::string | getName () |
| | Return name of machine instruction. More...
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| int8_t | numSrcRegs () const |
| | Number of source registers. More...
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| int8_t | numDestRegs () const |
| | Number of destination registers. More...
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| int8_t | numFPDestRegs () const |
| | Number of floating-point destination regs. More...
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| int8_t | numIntDestRegs () const |
| | Number of integer destination regs. More...
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| bool | isNop () const |
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| bool | isMemRef () const |
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| bool | isLoad () const |
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| bool | isStore () const |
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| bool | isStoreConditional () const |
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| bool | isInstPrefetch () const |
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| bool | isDataPrefetch () const |
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| bool | isPrefetch () const |
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| bool | isInteger () const |
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| bool | isFloating () const |
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| bool | isCC () const |
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| bool | isControl () const |
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| bool | isCall () const |
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| bool | isReturn () const |
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| bool | isDirectCtrl () const |
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| bool | isIndirectCtrl () const |
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| bool | isCondCtrl () const |
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| bool | isUncondCtrl () const |
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| bool | isCondDelaySlot () const |
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| bool | isThreadSync () const |
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| bool | isSerializing () const |
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| bool | isSerializeBefore () const |
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| bool | isSerializeAfter () const |
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| bool | isSquashAfter () const |
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| bool | isMemBarrier () const |
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| bool | isWriteBarrier () const |
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| bool | isNonSpeculative () const |
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| bool | isQuiesce () const |
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| bool | isIprAccess () const |
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| bool | isUnverifiable () const |
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| bool | isSyscall () const |
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| bool | isMacroop () const |
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| bool | isMicroop () const |
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| bool | isDelayedCommit () const |
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| bool | isLastMicroop () const |
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| bool | isFirstMicroop () const |
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| bool | isMicroBranch () const |
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| | RefCounted () |
| | We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More...
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| virtual | ~RefCounted () |
| | We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More...
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| void | incref () |
| | Increment the reference count. More...
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| void | decref () |
| | Decrement the reference count and destroy the object if all references are gone. More...
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| const ExtMachInst | machInst |
| | The binary machine instruction. More...
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| static StaticInstPtr | nullStaticInstPtr |
| | Pointer to a statically allocated "null" instruction object. More...
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| template<int width> |
| static bool | saturateOp (int32_t &res, int64_t op1, int64_t op2, bool sub=false) |
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| static bool | satInt (int32_t &res, int64_t op, int width) |
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| template<int width> |
| static bool | uSaturateOp (uint32_t &res, int64_t op1, int64_t op2, bool sub=false) |
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| static bool | uSatInt (int32_t &res, int64_t op, int width) |
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| static uint32_t | cpsrWriteByInstr (CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc) |
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| static uint32_t | spsrWriteByInstr (uint32_t spsr, uint32_t val, uint8_t byteMask, bool affectState) |
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| template<class XC > |
| static Addr | readPC (XC *xc) |
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| template<class XC > |
| static void | setNextPC (XC *xc, Addr val) |
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| template<class T > |
| static T | cSwap (T val, bool big) |
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| template<class T , class E > |
| static T | cSwap (T val, bool big) |
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| template<class XC > |
| static void | setIWNextPC (XC *xc, Addr val) |
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| template<class XC > |
| static void | setAIWNextPC (XC *xc, Addr val) |
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Microops of the form IntRegA = IntRegB op shifted IntRegC.
Definition at line 362 of file macromem.hh.
Protected Member Functions inherited from ArmISA::MicroOp