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ArmISA::ArmStaticInst Class Reference

#include <static_inst.hh>

Inheritance diagram for ArmISA::ArmStaticInst:
StaticInst RefCounted ArmISA::BranchEret64 ArmISA::BranchImm64 ArmISA::BranchImmImmReg64 ArmISA::BranchImmReg64 ArmISA::BranchReg64 ArmISA::DataX1Reg2ImmOp ArmISA::DataX1RegImmOp ArmISA::DataX1RegOp ArmISA::DataX2RegImmOp ArmISA::DataX2RegOp ArmISA::DataX3RegOp ArmISA::DataXCondCompImmOp ArmISA::DataXCondCompRegOp ArmISA::DataXCondSelOp ArmISA::DataXERegOp ArmISA::DataXImmOnlyOp ArmISA::DataXImmOp ArmISA::DataXSRegOp ArmISA::MicroOpX ArmISA::MightBeMicro64 ArmISA::PredOp ArmISA::SysDC64 DecoderFaultInst FailUnimplemented McrMrcMiscInst RegRegImmImmOp64 RegRegRegImmOp64 UnknownOp64 WarnUnimplemented

Public Member Functions

virtual void annotateFault (ArmFault *fault)
 
- Public Member Functions inherited from StaticInst
int8_t numCCDestRegs () const
 Number of coprocesor destination regs. More...
 
void setFirstMicroop ()
 
void setLastMicroop ()
 
void setDelayedCommit ()
 
void setFlag (Flags f)
 
OpClass opClass () const
 Operation class. Used to select appropriate function unit in issue. More...
 
RegIndex destRegIdx (int i) const
 Return logical index (architectural reg num) of i'th destination reg. More...
 
RegIndex srcRegIdx (int i) const
 Return logical index (architectural reg num) of i'th source reg. More...
 
virtual const StaticInstPtreaCompInst () const
 Memory references only: returns "fake" instruction representing the effective address part of the memory operation. More...
 
virtual const StaticInstPtrmemAccInst () const
 Memory references only: returns "fake" instruction representing the memory access part of the memory operation. More...
 
virtual ~StaticInst ()
 
virtual Fault execute (ExecContext *xc, Trace::InstRecord *traceData) const =0
 
virtual Fault eaComp (ExecContext *xc, Trace::InstRecord *traceData) const
 
virtual Fault initiateAcc (ExecContext *xc, Trace::InstRecord *traceData) const
 
virtual Fault completeAcc (Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const
 
virtual void advancePC (TheISA::PCState &pcState) const =0
 
virtual StaticInstPtr fetchMicroop (MicroPC upc) const
 Return the microop that goes with a particular micropc. More...
 
virtual TheISA::PCState branchTarget (const TheISA::PCState &pc) const
 Return the target address for a PC-relative branch. More...
 
virtual TheISA::PCState branchTarget (ThreadContext *tc) const
 Return the target address for an indirect branch (jump). More...
 
bool hasBranchTarget (const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const
 Return true if the instruction is a control transfer, and if so, return the target address as well. More...
 
virtual const std::string & disassemble (Addr pc, const SymbolTable *symtab=0) const
 Return string representation of disassembled instruction. More...
 
void printFlags (std::ostream &outs, const std::string &separator) const
 Print a separator separated list of this instruction's set flag names on the given stream. More...
 
std::string getName ()
 Return name of machine instruction. More...
 
int8_t numSrcRegs () const
 Number of source registers. More...
 
int8_t numDestRegs () const
 Number of destination registers. More...
 
int8_t numFPDestRegs () const
 Number of floating-point destination regs. More...
 
int8_t numIntDestRegs () const
 Number of integer destination regs. More...
 
bool isNop () const
 
bool isMemRef () const
 
bool isLoad () const
 
bool isStore () const
 
bool isStoreConditional () const
 
bool isInstPrefetch () const
 
bool isDataPrefetch () const
 
bool isPrefetch () const
 
bool isInteger () const
 
bool isFloating () const
 
bool isCC () const
 
bool isControl () const
 
bool isCall () const
 
bool isReturn () const
 
bool isDirectCtrl () const
 
bool isIndirectCtrl () const
 
bool isCondCtrl () const
 
bool isUncondCtrl () const
 
bool isCondDelaySlot () const
 
bool isThreadSync () const
 
bool isSerializing () const
 
bool isSerializeBefore () const
 
bool isSerializeAfter () const
 
bool isSquashAfter () const
 
bool isMemBarrier () const
 
bool isWriteBarrier () const
 
bool isNonSpeculative () const
 
bool isQuiesce () const
 
bool isIprAccess () const
 
bool isUnverifiable () const
 
bool isSyscall () const
 
bool isMacroop () const
 
bool isMicroop () const
 
bool isDelayedCommit () const
 
bool isLastMicroop () const
 
bool isFirstMicroop () const
 
bool isMicroBranch () const
 
- Public Member Functions inherited from RefCounted
 RefCounted ()
 We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More...
 
virtual ~RefCounted ()
 We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More...
 
void incref ()
 Increment the reference count. More...
 
void decref ()
 Decrement the reference count and destroy the object if all references are gone. More...
 

Protected Member Functions

int32_t shift_rm_imm (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
 
int32_t shift_rm_rs (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
 
bool shift_carry_imm (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
 
bool shift_carry_rs (uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
 
int64_t shiftReg64 (uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) const
 
int64_t extendReg64 (uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) const
 
 ArmStaticInst (const char *mnem, ExtMachInst _machInst, OpClass __opClass)
 
void printReg (std::ostream &os, int reg) const
 Print a register name for disassembly given the unique dependence tag number (FP or int). More...
 
void printMnemonic (std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
 
void printTarget (std::ostream &os, Addr target, const SymbolTable *symtab) const
 
void printCondition (std::ostream &os, unsigned code, bool noImplicit=false) const
 
void printMemSymbol (std::ostream &os, const SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const
 
void printShiftOperand (std::ostream &os, IntRegIndex rm, bool immShift, uint32_t shiftAmt, IntRegIndex rs, ArmShiftType type) const
 
void printExtendOperand (bool firstOperand, std::ostream &os, IntRegIndex rm, ArmExtendType type, int64_t shiftAmt) const
 
void printDataInst (std::ostream &os, bool withImm) const
 
void printDataInst (std::ostream &os, bool withImm, bool immShift, bool s, IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, uint64_t imm) const
 
void advancePC (PCState &pcState) const
 
std::string generateDisassembly (Addr pc, const SymbolTable *symtab) const
 Internal function to generate disassembly string. More...
 
Fault disabledFault () const
 
Fault advSIMDFPAccessTrap64 (ExceptionLevel el) const
 Trap an access to Advanced SIMD or FP registers due to access control bits. More...
 
Fault checkFPAdvSIMDTrap64 (ThreadContext *tc, CPSR cpsr) const
 Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3. More...
 
Fault checkFPAdvSIMDEnabled64 (ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
 Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and CPTR_EL3. More...
 
Fault checkAdvSIMDOrFPEnabled32 (ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) const
 Check if a VFP/SIMD access from aarch32 should be allowed. More...
 
CPSR getPSTATEFromPSR (ThreadContext *tc, CPSR cpsr, CPSR spsr) const
 Get the new PSTATE from a SPSR register in preparation for an exception return. More...
 
- Protected Member Functions inherited from StaticInst
 StaticInst (const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
 Constructor. More...
 

Static Protected Member Functions

template<int width>
static bool saturateOp (int32_t &res, int64_t op1, int64_t op2, bool sub=false)
 
static bool satInt (int32_t &res, int64_t op, int width)
 
template<int width>
static bool uSaturateOp (uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
 
static bool uSatInt (int32_t &res, int64_t op, int width)
 
static uint32_t cpsrWriteByInstr (CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)
 
static uint32_t spsrWriteByInstr (uint32_t spsr, uint32_t val, uint8_t byteMask, bool affectState)
 
template<class XC >
static Addr readPC (XC *xc)
 
template<class XC >
static void setNextPC (XC *xc, Addr val)
 
template<class T >
static T cSwap (T val, bool big)
 
template<class T , class E >
static T cSwap (T val, bool big)
 
template<class XC >
static void setIWNextPC (XC *xc, Addr val)
 
template<class XC >
static void setAIWNextPC (XC *xc, Addr val)
 

Protected Attributes

bool aarch64
 
uint8_t intWidth
 
- Protected Attributes inherited from StaticInst
std::bitset< Num_Flags > flags
 Flag values for this instruction. More...
 
OpClass _opClass
 See opClass(). More...
 
int8_t _numSrcRegs
 See numSrcRegs(). More...
 
int8_t _numDestRegs
 See numDestRegs(). More...
 
RegIndex _destRegIdx [MaxInstDestRegs]
 See destRegIdx(). More...
 
RegIndex _srcRegIdx [MaxInstSrcRegs]
 See srcRegIdx(). More...
 
const char * mnemonic
 Base mnemonic (e.g., "add"). More...
 
std::string * cachedDisassembly
 String representation of disassembly (lazily evaluated via disassemble()). More...
 
int8_t _numFPDestRegs
 The following are used to track physical register usage for machines with separate int & FP reg files. More...
 
int8_t _numIntDestRegs
 
int8_t _numCCDestRegs
 

Additional Inherited Members

- Public Types inherited from StaticInst
enum  { MaxInstSrcRegs = TheISA::MaxInstSrcRegs, MaxInstDestRegs = TheISA::MaxInstDestRegs }
 
typedef TheISA::ExtMachInst ExtMachInst
 Binary extended machine instruction type. More...
 
typedef TheISA::RegIndex RegIndex
 Logical register index type. More...
 
- Public Attributes inherited from StaticInst
const ExtMachInst machInst
 The binary machine instruction. More...
 
- Static Public Attributes inherited from StaticInst
static StaticInstPtr nullStaticInstPtr
 Pointer to a statically allocated "null" instruction object. More...
 

Detailed Description

Definition at line 58 of file static_inst.hh.

Constructor & Destructor Documentation

ArmISA::ArmStaticInst::ArmStaticInst ( const char *  mnem,
ExtMachInst  _machInst,
OpClass  __opClass 
)
inlineprotected

Definition at line 145 of file static_inst.hh.

References aarch64, bits(), intWidth, and StaticInst::machInst.

Member Function Documentation

void ArmISA::ArmStaticInst::advancePC ( PCState &  pcState) const
inlineprotected

Definition at line 186 of file static_inst.hh.

Fault ArmISA::ArmStaticInst::advSIMDFPAccessTrap64 ( ExceptionLevel  el) const
protected

Trap an access to Advanced SIMD or FP registers due to access control bits.

See aarch64/exceptions/traps/AArch64.AdvSIMDFPAccessTrap in the ARM ARM psueodcode library.

Parameters
elTarget EL for the trap

Definition at line 602 of file static_inst.cc.

References ArmISA::EC_TRAPPED_SIMD_FP, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, StaticInst::machInst, and panic.

Referenced by checkAdvSIMDOrFPEnabled32(), checkFPAdvSIMDEnabled64(), and checkFPAdvSIMDTrap64().

virtual void ArmISA::ArmStaticInst::annotateFault ( ArmFault fault)
inlinevirtual

Definition at line 418 of file static_inst.hh.

Referenced by ArmISA::ArmFault::invoke().

Fault ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32 ( ThreadContext tc,
CPSR  cpsr,
CPACR  cpacr,
NSACR  nsacr,
FPEXC  fpexc,
bool  fpexc_check,
bool  advsimd 
) const
protected
Fault ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64 ( ThreadContext tc,
CPSR  cpsr,
CPACR  cpacr 
) const
protected

Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.

See aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDEnabled in the ARM ARM psueodcode library.

Definition at line 642 of file static_inst.cc.

References advSIMDFPAccessTrap64(), checkFPAdvSIMDTrap64(), ArmISA::el, ArmISA::EL0, and ArmISA::EL1.

Referenced by checkAdvSIMDOrFPEnabled32().

Fault ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64 ( ThreadContext tc,
CPSR  cpsr 
) const
protected

Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3.

See aarch64/exceptions/traps/AArch64.CheckFPAdvSIMDTrap in the ARM ARM psueodcode library.

Definition at line 622 of file static_inst.cc.

References advSIMDFPAccessTrap64(), ArmISA::el, ArmISA::EL2, ArmISA::EL3, ArmSystem::haveSecurity(), ArmSystem::haveVirtualization(), ArmISA::MISCREG_CPTR_EL2, ArmISA::MISCREG_CPTR_EL3, NoFault, and ThreadContext::readMiscReg().

Referenced by checkAdvSIMDOrFPEnabled32(), and checkFPAdvSIMDEnabled64().

static uint32_t ArmISA::ArmStaticInst::cpsrWriteByInstr ( CPSR  cpsr,
uint32_t  val,
SCR  scr,
NSACR  nsacr,
uint8_t  byteMask,
bool  affectState,
bool  nmfi,
ThreadContext tc 
)
inlinestaticprotected
template<class T >
static T ArmISA::ArmStaticInst::cSwap ( val,
bool  big 
)
inlinestaticprotected

Definition at line 307 of file static_inst.hh.

References BigEndianGuest::gtobe(), and BigEndianGuest::gtole().

template<class T , class E >
static T ArmISA::ArmStaticInst::cSwap ( val,
bool  big 
)
inlinestaticprotected
Fault ArmISA::ArmStaticInst::disabledFault ( ) const
inlineprotected

Definition at line 360 of file static_inst.hh.

References StaticInst::machInst, and StaticInst::mnemonic.

Referenced by checkAdvSIMDOrFPEnabled32().

int64_t ArmISA::ArmStaticInst::extendReg64 ( uint64_t  base,
ArmExtendType  type,
uint64_t  shiftAmt,
uint8_t  width 
) const
protected
std::string ArmISA::ArmStaticInst::generateDisassembly ( Addr  pc,
const SymbolTable symtab 
) const
protectedvirtual
CPSR ArmISA::ArmStaticInst::getPSTATEFromPSR ( ThreadContext tc,
CPSR  cpsr,
CPSR  spsr 
) const
protected

Get the new PSTATE from a SPSR register in preparation for an exception return.

See shared/functions/system/SetPSTATEFromPSR in the ARM ARM psueodcode library.

Definition at line 797 of file static_inst.cc.

References ArmISA::badMode32(), ArmISA::getRestoredITBits(), and ArmISA::illegalExceptionReturn().

void ArmISA::ArmStaticInst::printCondition ( std::ostream &  os,
unsigned  code,
bool  noImplicit = false 
) const
protected
void ArmISA::ArmStaticInst::printDataInst ( std::ostream &  os,
bool  withImm 
) const
protected
void ArmISA::ArmStaticInst::printDataInst ( std::ostream &  os,
bool  withImm,
bool  immShift,
bool  s,
IntRegIndex  rd,
IntRegIndex  rn,
IntRegIndex  rm,
IntRegIndex  rs,
uint32_t  shiftAmt,
ArmShiftType  type,
uint64_t  imm 
) const
protected
void ArmISA::ArmStaticInst::printExtendOperand ( bool  firstOperand,
std::ostream &  os,
IntRegIndex  rm,
ArmExtendType  type,
int64_t  shiftAmt 
) const
protected
void ArmISA::ArmStaticInst::printMemSymbol ( std::ostream &  os,
const SymbolTable symtab,
const std::string &  prefix,
const Addr  addr,
const std::string &  suffix 
) const
protected

Definition at line 447 of file static_inst.cc.

References ccprintf(), and SymbolTable::findNearestSymbol().

void ArmISA::ArmStaticInst::printMnemonic ( std::ostream &  os,
const std::string &  suffix = "",
bool  withPred = true,
bool  withCond64 = false,
ConditionCode  cond64 = COND_UC 
) const
protected

Definition at line 345 of file static_inst.cc.

References aarch64, StaticInst::machInst, StaticInst::mnemonic, and printCondition().

Referenced by MrsOp::generateDisassembly(), RegRegImmImmOp64::generateDisassembly(), ArmISA::BranchImm64::generateDisassembly(), ArmISA::DataXImmOnlyOp::generateDisassembly(), ArmISA::BranchImmCond64::generateDisassembly(), RegRegRegImmOp64::generateDisassembly(), ArmISA::BranchReg64::generateDisassembly(), ArmISA::BranchRet64::generateDisassembly(), MrrcOp::generateDisassembly(), ArmISA::BranchEret64::generateDisassembly(), ArmISA::DataX1RegOp::generateDisassembly(), McrrOp::generateDisassembly(), ArmISA::BranchImmReg64::generateDisassembly(), ArmISA::DataX1RegImmOp::generateDisassembly(), ImmOp::generateDisassembly(), ArmISA::DataX1Reg2ImmOp::generateDisassembly(), RegImmOp::generateDisassembly(), ArmISA::BranchImmImmReg64::generateDisassembly(), ArmISA::DataX2RegOp::generateDisassembly(), RegRegOp::generateDisassembly(), ArmISA::DataX2RegImmOp::generateDisassembly(), RegImmRegOp::generateDisassembly(), generateDisassembly(), ArmISA::DataX3RegOp::generateDisassembly(), RegRegRegImmOp::generateDisassembly(), ArmISA::DataXCondCompImmOp::generateDisassembly(), RegRegRegRegOp::generateDisassembly(), ArmISA::DataXCondCompRegOp::generateDisassembly(), RegRegRegOp::generateDisassembly(), ArmISA::DataXCondSelOp::generateDisassembly(), RegRegImmOp::generateDisassembly(), ArmISA::MicroSetPCCPSR::generateDisassembly(), MiscRegRegImmOp::generateDisassembly(), ArmISA::MicroIntMov::generateDisassembly(), RegMiscRegImmOp::generateDisassembly(), ArmISA::MicroIntImmOp::generateDisassembly(), RegImmImmOp::generateDisassembly(), ArmISA::MicroIntImmXOp::generateDisassembly(), RegRegImmImmOp::generateDisassembly(), ArmISA::MicroIntOp::generateDisassembly(), RegImmRegShiftOp::generateDisassembly(), ArmISA::MicroIntRegXOp::generateDisassembly(), ArmISA::MicroMemOp::generateDisassembly(), ArmISA::MicroMemPairOp::generateDisassembly(), ArmISA::FpCondCompRegOp::generateDisassembly(), ArmISA::FpCondSelOp::generateDisassembly(), ArmISA::FpRegRegOp::generateDisassembly(), ArmISA::FpRegImmOp::generateDisassembly(), ArmISA::FpRegRegImmOp::generateDisassembly(), ArmISA::FpRegRegRegOp::generateDisassembly(), ArmISA::FpRegRegRegCondOp::generateDisassembly(), ArmISA::FpRegRegRegRegOp::generateDisassembly(), ArmISA::FpRegRegRegImmOp::generateDisassembly(), printDataInst(), and MsrBase::printMsrBase().

void ArmISA::ArmStaticInst::printReg ( std::ostream &  os,
int  reg 
) const
protected

Print a register name for disassembly given the unique dependence tag number (FP or int).

Definition at line 296 of file static_inst.cc.

References aarch64, ccprintf(), CCRegClass, ArmISA::ccRegName, FloatRegClass, ArmISA::FramePointerReg, ArmISA::INTREG_SPX, ArmISA::INTREG_UREG0, ArmISA::INTREG_X31, IntRegClass, intWidth, MiscRegClass, ArmISA::miscRegName, ArmISA::NUM_MISCREGS, ArmISA::PCReg, regIdxToClass(), ArmISA::ReturnAddressReg, and ArmISA::StackPointerReg.

Referenced by MrsOp::generateDisassembly(), RegRegImmImmOp64::generateDisassembly(), ArmISA::DataXImmOnlyOp::generateDisassembly(), RegRegRegImmOp64::generateDisassembly(), ArmISA::BranchReg64::generateDisassembly(), MsrRegOp::generateDisassembly(), ArmISA::BranchRet64::generateDisassembly(), MrrcOp::generateDisassembly(), ArmISA::DataX1RegOp::generateDisassembly(), McrrOp::generateDisassembly(), ArmISA::BranchImmReg64::generateDisassembly(), ArmISA::DataX1RegImmOp::generateDisassembly(), ArmISA::DataX1Reg2ImmOp::generateDisassembly(), RegImmOp::generateDisassembly(), ArmISA::BranchImmImmReg64::generateDisassembly(), ArmISA::DataX2RegOp::generateDisassembly(), RegRegOp::generateDisassembly(), ArmISA::DataX2RegImmOp::generateDisassembly(), RegImmRegOp::generateDisassembly(), ArmISA::DataX3RegOp::generateDisassembly(), RegRegRegImmOp::generateDisassembly(), ArmISA::DataXCondCompImmOp::generateDisassembly(), RegRegRegRegOp::generateDisassembly(), ArmISA::DataXCondCompRegOp::generateDisassembly(), RegRegRegOp::generateDisassembly(), ArmISA::DataXCondSelOp::generateDisassembly(), RegRegImmOp::generateDisassembly(), MiscRegRegImmOp::generateDisassembly(), ArmISA::MicroIntMov::generateDisassembly(), RegMiscRegImmOp::generateDisassembly(), ArmISA::MicroIntImmOp::generateDisassembly(), RegImmImmOp::generateDisassembly(), ArmISA::MicroIntImmXOp::generateDisassembly(), RegRegImmImmOp::generateDisassembly(), ArmISA::MicroIntOp::generateDisassembly(), RegImmRegShiftOp::generateDisassembly(), ArmISA::MicroIntRegXOp::generateDisassembly(), ArmISA::MicroMemOp::generateDisassembly(), ArmISA::MicroMemPairOp::generateDisassembly(), ArmISA::FpCondCompRegOp::generateDisassembly(), ArmISA::FpCondSelOp::generateDisassembly(), ArmISA::FpRegRegOp::generateDisassembly(), ArmISA::FpRegImmOp::generateDisassembly(), ArmISA::FpRegRegImmOp::generateDisassembly(), ArmISA::FpRegRegRegOp::generateDisassembly(), ArmISA::FpRegRegRegCondOp::generateDisassembly(), ArmISA::FpRegRegRegRegOp::generateDisassembly(), ArmISA::FpRegRegRegImmOp::generateDisassembly(), printDataInst(), ArmISA::Memory::printDest(), ArmISA::MemoryExImm::printDest(), ArmISA::MemoryDImm::printDest(), ArmISA::MemoryExDImm::printDest(), ArmISA::MemoryDReg::printDest(), printExtendOperand(), and printShiftOperand().

void ArmISA::ArmStaticInst::printShiftOperand ( std::ostream &  os,
IntRegIndex  rm,
bool  immShift,
uint32_t  shiftAmt,
IntRegIndex  rs,
ArmShiftType  type 
) const
protected
void ArmISA::ArmStaticInst::printTarget ( std::ostream &  os,
Addr  target,
const SymbolTable symtab 
) const
protected
template<class XC >
static Addr ArmISA::ArmStaticInst::readPC ( XC *  xc)
inlinestaticprotected

Definition at line 291 of file static_inst.hh.

static bool ArmISA::ArmStaticInst::satInt ( int32_t &  res,
int64_t  op,
int  width 
)
inlinestaticprotected

Definition at line 97 of file static_inst.hh.

References LL, X86ISA::op, and ArmISA::width.

template<int width>
static bool ArmISA::ArmStaticInst::saturateOp ( int32_t &  res,
int64_t  op1,
int64_t  op2,
bool  sub = false 
)
inlinestaticprotected

Definition at line 81 of file static_inst.hh.

References bits(), LL, and ArmISA::width.

template<class XC >
static void ArmISA::ArmStaticInst::setAIWNextPC ( XC *  xc,
Addr  val 
)
inlinestaticprotected

Definition at line 352 of file static_inst.hh.

References pc.

template<class XC >
static void ArmISA::ArmStaticInst::setIWNextPC ( XC *  xc,
Addr  val 
)
inlinestaticprotected

Definition at line 341 of file static_inst.hh.

References pc.

template<class XC >
static void ArmISA::ArmStaticInst::setNextPC ( XC *  xc,
Addr  val 
)
inlinestaticprotected

Definition at line 298 of file static_inst.hh.

References pc.

bool ArmISA::ArmStaticInst::shift_carry_imm ( uint32_t  base,
uint32_t  shamt,
uint32_t  type,
uint32_t  cfval 
) const
protected

Definition at line 216 of file static_inst.cc.

References ArmISA::ASR, ccprintf(), X86ISA::exit, ArmISA::LSL, ArmISA::LSR, and ArmISA::ROR.

bool ArmISA::ArmStaticInst::shift_carry_rs ( uint32_t  base,
uint32_t  shamt,
uint32_t  type,
uint32_t  cfval 
) const
protected

Definition at line 256 of file static_inst.cc.

References ArmISA::ASR, ccprintf(), X86ISA::exit, ArmISA::LSL, ArmISA::LSR, and ArmISA::ROR.

int32_t ArmISA::ArmStaticInst::shift_rm_imm ( uint32_t  base,
uint32_t  shamt,
uint32_t  type,
uint32_t  cfval 
) const
protected

Definition at line 56 of file static_inst.cc.

References ArmISA::ASR, ccprintf(), X86ISA::exit, ArmISA::LSL, ArmISA::LSR, and ArmISA::ROR.

int32_t ArmISA::ArmStaticInst::shift_rm_rs ( uint32_t  base,
uint32_t  shamt,
uint32_t  type,
uint32_t  cfval 
) const
protected
int64_t ArmISA::ArmStaticInst::shiftReg64 ( uint64_t  base,
uint64_t  shiftAmt,
ArmShiftType  type,
uint8_t  width 
) const
protected
static uint32_t ArmISA::ArmStaticInst::spsrWriteByInstr ( uint32_t  spsr,
uint32_t  val,
uint8_t  byteMask,
bool  affectState 
)
inlinestaticprotected

Definition at line 272 of file static_inst.hh.

References bits(), and ArmISA::mask.

static bool ArmISA::ArmStaticInst::uSatInt ( int32_t &  res,
int64_t  op,
int  width 
)
inlinestaticprotected

Definition at line 130 of file static_inst.hh.

References LL, X86ISA::op, and ArmISA::width.

template<int width>
static bool ArmISA::ArmStaticInst::uSaturateOp ( uint32_t &  res,
int64_t  op1,
int64_t  op2,
bool  sub = false 
)
inlinestaticprotected

Definition at line 114 of file static_inst.hh.

References LL, and ArmISA::width.

Member Data Documentation

bool ArmISA::ArmStaticInst::aarch64
protected

Definition at line 61 of file static_inst.hh.

Referenced by ArmStaticInst(), printMnemonic(), and printReg().

uint8_t ArmISA::ArmStaticInst::intWidth
protected

Definition at line 62 of file static_inst.hh.

Referenced by ArmStaticInst(), printReg(), and shiftReg64().


The documentation for this class was generated from the following files:

Generated on Fri Jun 9 2017 13:04:29 for gem5 by doxygen 1.8.6