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gem5
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#include <mem.hh>
Public Member Functions | |
| AtomicInstBase (const Brig::BrigInstBase *ib, const BrigObject *obj, const char *_opcode) | |
| int | numSrcRegOperands () |
| int | numDstRegOperands () |
| int | getNumOperands () |
| bool | isVectorRegister (int operandIndex) |
| bool | isCondRegister (int operandIndex) |
| bool | isScalarRegister (int operandIndex) |
| bool | isSrcOperand (int operandIndex) |
| bool | isDstOperand (int operandIndex) |
| int | getOperandSize (int operandIndex) |
| int | getRegisterIndex (int operandIndex, GPUDynInstPtr gpuDynInst) |
Public Member Functions inherited from HsailISA::HsailGPUStaticInst | |
| HsailGPUStaticInst (const BrigObject *obj, const std::string &opcode) | |
| void | generateDisassembly () override |
| int | instSize () const override |
| bool | isValid () const override |
Public Member Functions inherited from GPUStaticInst | |
| GPUStaticInst (const std::string &opcode) | |
| void | instAddr (int inst_addr) |
| int | instAddr () const |
| int | nextInstAddr () const |
| void | instNum (int num) |
| int | instNum () |
| void | ipdInstNum (int num) |
| int | ipdInstNum () const |
| virtual void | execute (GPUDynInstPtr gpuDynInst)=0 |
| const std::string & | disassemble () |
| bool | isALU () const |
| bool | isBranch () const |
| bool | isNop () const |
| bool | isReturn () const |
| bool | isUnconditionalJump () const |
| bool | isSpecialOp () const |
| bool | isWaitcnt () const |
| bool | isBarrier () const |
| bool | isMemFence () const |
| bool | isMemRef () const |
| bool | isFlat () const |
| bool | isLoad () const |
| bool | isStore () const |
| bool | isAtomic () const |
| bool | isAtomicNoRet () const |
| bool | isAtomicRet () const |
| bool | isScalar () const |
| bool | readsSCC () const |
| bool | writesSCC () const |
| bool | readsVCC () const |
| bool | writesVCC () const |
| bool | isAtomicAnd () const |
| bool | isAtomicOr () const |
| bool | isAtomicXor () const |
| bool | isAtomicCAS () const |
| bool | isAtomicExch () const |
| bool | isAtomicAdd () const |
| bool | isAtomicSub () const |
| bool | isAtomicInc () const |
| bool | isAtomicDec () const |
| bool | isAtomicMax () const |
| bool | isAtomicMin () const |
| bool | isArgLoad () const |
| bool | isGlobalMem () const |
| bool | isLocalMem () const |
| bool | isArgSeg () const |
| bool | isGlobalSeg () const |
| bool | isGroupSeg () const |
| bool | isKernArgSeg () const |
| bool | isPrivateSeg () const |
| bool | isReadOnlySeg () const |
| bool | isSpillSeg () const |
| bool | isWorkitemScope () const |
| bool | isWavefrontScope () const |
| bool | isWorkgroupScope () const |
| bool | isDeviceScope () const |
| bool | isSystemScope () const |
| bool | isNoScope () const |
| bool | isRelaxedOrder () const |
| bool | isAcquire () const |
| bool | isRelease () const |
| bool | isAcquireRelease () const |
| bool | isNoOrder () const |
| bool | isGloballyCoherent () const |
| Coherence domain of a memory instruction. More... | |
| bool | isSystemCoherent () const |
| virtual void | initiateAcc (GPUDynInstPtr gpuDynInst) |
| virtual void | completeAcc (GPUDynInstPtr gpuDynInst) |
| virtual uint32_t | getTargetPc () |
| void | setFlag (Flags flag) |
| virtual void | execLdAcq (GPUDynInstPtr gpuDynInst) |
| virtual void | execSt (GPUDynInstPtr gpuDynInst) |
| virtual void | execAtomic (GPUDynInstPtr gpuDynInst) |
| virtual void | execAtomicAcq (GPUDynInstPtr gpuDynInst) |
Public Attributes | |
| OperandType::DestOperand | dest |
| OperandType::SrcOperand | src [NumSrcOperands] |
| AddrOperandType | addr |
| Brig::BrigSegment | segment |
| Brig::BrigMemoryOrder | memoryOrder |
| Brig::BrigAtomicOperation | atomicOperation |
| Brig::BrigMemoryScope | memoryScope |
| Brig::BrigOpcode | opcode |
Public Attributes inherited from GPUStaticInst | |
| Enums::StorageClassType | executed_as |
Additional Inherited Members | |
Static Public Attributes inherited from GPUStaticInst | |
| static uint64_t | dynamic_id_count |
Protected Attributes inherited from HsailISA::HsailGPUStaticInst | |
| HsailCode * | hsailCode |
Protected Attributes inherited from GPUStaticInst | |
| const std::string | opcode |
| std::string | disassembly |
| int | _instNum |
| int | _instAddr |
| int | _ipdInstNum |
| Identifier of the immediate post-dominator instruction. More... | |
| std::bitset< Num_Flags > | _flags |
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inline |
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inlinevirtual |
Implements GPUStaticInst.
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inlinevirtual |
Implements GPUStaticInst.
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inlinevirtual |
Implements GPUStaticInst.
|
inlinevirtual |
Implements GPUStaticInst.
|
inlinevirtual |
Implements GPUStaticInst.
|
inlinevirtual |
Implements GPUStaticInst.
|
inlinevirtual |
Implements GPUStaticInst.
|
inlinevirtual |
Implements GPUStaticInst.
|
inlinevirtual |
Implements GPUStaticInst.
|
inlinevirtual |
Implements GPUStaticInst.
| AddrOperandType HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst >::addr |
| Brig::BrigAtomicOperation HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst >::atomicOperation |
| OperandType::DestOperand HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst >::dest |
| Brig::BrigMemoryOrder HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst >::memoryOrder |
| Brig::BrigMemoryScope HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst >::memoryScope |
| Brig::BrigOpcode HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst >::opcode |
| Brig::BrigSegment HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst >::segment |
| OperandType::SrcOperand HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst >::src[NumSrcOperands] |