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DefaultFetch class handles both single threaded and SMT fetch. More...
#include <fetch.hh>
Classes | |
| class | FetchTranslation |
| class | FinishTranslationEvent |
| struct | Stalls |
| Source of possible stalls. More... | |
Public Types | |
| enum | FetchStatus { Active, Inactive } |
| Overall fetch status. More... | |
| enum | ThreadStatus { Running, Idle, Squashing, Blocked, Fetching, TrapPending, QuiescePending, ItlbWait, IcacheWaitResponse, IcacheWaitRetry, IcacheAccessComplete, NoGoodAddr } |
| Individual thread status. More... | |
| enum | FetchPriority { SingleThread, RoundRobin, Branch, IQ, LSQ } |
| Fetching Policy, Add new policies here. More... | |
| typedef Impl::CPUPol | CPUPol |
| Typedefs from Impl. More... | |
| typedef Impl::DynInst | DynInst |
| typedef Impl::DynInstPtr | DynInstPtr |
| typedef Impl::O3CPU | O3CPU |
| typedef CPUPol::FetchStruct | FetchStruct |
| Typedefs from the CPU policy. More... | |
| typedef CPUPol::TimeStruct | TimeStruct |
| typedef TheISA::MachInst | MachInst |
| Typedefs from ISA. More... | |
| typedef TheISA::ExtMachInst | ExtMachInst |
Public Member Functions | |
| DefaultFetch (O3CPU *_cpu, DerivO3CPUParams *params) | |
| DefaultFetch constructor. More... | |
| std::string | name () const |
| Returns the name of fetch. More... | |
| void | regStats () |
| Registers statistics. More... | |
| void | regProbePoints () |
| Registers probes. More... | |
| void | setTimeBuffer (TimeBuffer< TimeStruct > *time_buffer) |
| Sets the main backwards communication time buffer pointer. More... | |
| void | setActiveThreads (std::list< ThreadID > *at_ptr) |
| Sets pointer to list of active threads. More... | |
| void | setFetchQueue (TimeBuffer< FetchStruct > *fq_ptr) |
| Sets pointer to time buffer used to communicate to the next stage. More... | |
| void | startupStage () |
| Initialize stage. More... | |
| void | recvReqRetry () |
| Handles retrying the fetch access. More... | |
| void | processCacheCompletion (PacketPtr pkt) |
| Processes cache completion event. More... | |
| void | drainResume () |
| Resume after a drain. More... | |
| void | drainSanityCheck () const |
| Perform sanity checks after a drain. More... | |
| bool | isDrained () const |
| Has the stage drained? More... | |
| void | takeOverFrom () |
| Takes over from another CPU's thread. More... | |
| void | drainStall (ThreadID tid) |
| Stall the fetch stage after reaching a safe drain point. More... | |
| void | wakeFromQuiesce () |
| Tells fetch to wake up from a quiesce instruction. More... | |
| void | deactivateThread (ThreadID tid) |
| For priority-based fetch policies, need to keep update priorityList. More... | |
| void | squash (const TheISA::PCState &newPC, const InstSeqNum seq_num, DynInstPtr squashInst, ThreadID tid) |
| Squashes a specific thread and resets the PC. More... | |
| void | tick () |
| Ticks the fetch stage, processing all inputs signals and fetching as many instructions as possible. More... | |
| bool | checkSignalsAndUpdate (ThreadID tid) |
| Checks all input signals and updates the status as necessary. More... | |
| void | fetch (bool &status_change) |
| Does the actual fetching of instructions and passing them on to the next stage. More... | |
| Addr | fetchBufferAlignPC (Addr addr) |
| Align a PC to the start of a fetch buffer block. More... | |
Public Attributes | |
| TheISA::Decoder * | decoder [Impl::MaxThreads] |
| The decoder. More... | |
Private Member Functions | |
| void | resetStage () |
| Reset this pipeline stage. More... | |
| void | switchToActive () |
| Changes the status of this stage to active, and indicates this to the CPU. More... | |
| void | switchToInactive () |
| Changes the status of this stage to inactive, and indicates this to the CPU. More... | |
| bool | lookupAndUpdateNextPC (DynInstPtr &inst, TheISA::PCState &pc) |
| Looks up in the branch predictor to see if the next PC should be either next PC+=MachInst or a branch target. More... | |
| bool | fetchCacheLine (Addr vaddr, ThreadID tid, Addr pc) |
| Fetches the cache line that contains the fetch PC. More... | |
| void | finishTranslation (const Fault &fault, RequestPtr mem_req) |
| bool | checkInterrupt (Addr pc) |
| Check if an interrupt is pending and that we need to handle. More... | |
| void | doSquash (const TheISA::PCState &newPC, const DynInstPtr squashInst, ThreadID tid) |
| Squashes a specific thread and resets the PC. More... | |
| void | squashFromDecode (const TheISA::PCState &newPC, const DynInstPtr squashInst, const InstSeqNum seq_num, ThreadID tid) |
| Squashes a specific thread and resets the PC. More... | |
| bool | checkStall (ThreadID tid) const |
| Checks if a thread is stalled. More... | |
| FetchStatus | updateFetchStatus () |
| Updates overall fetch stage status; to be called at the end of each cycle. More... | |
| DynInstPtr | buildInst (ThreadID tid, StaticInstPtr staticInst, StaticInstPtr curMacroop, TheISA::PCState thisPC, TheISA::PCState nextPC, bool trace) |
| ThreadID | getFetchingThread (FetchPriority &fetch_priority) |
| Returns the appropriate thread to fetch, given the fetch policy. More... | |
| ThreadID | roundRobin () |
| Returns the appropriate thread to fetch using a round robin policy. More... | |
| ThreadID | iqCount () |
| Returns the appropriate thread to fetch using the IQ count policy. More... | |
| ThreadID | lsqCount () |
| Returns the appropriate thread to fetch using the LSQ count policy. More... | |
| ThreadID | branchCount () |
| Returns the appropriate thread to fetch using the branch count policy. More... | |
| void | pipelineIcacheAccesses (ThreadID tid) |
| Pipeline the next I-cache access to the current one. More... | |
| void | profileStall (ThreadID tid) |
| Profile the reasons of fetch stall. More... | |
Private Attributes | |
| FetchStatus | _status |
| Fetch status. More... | |
| ThreadStatus | fetchStatus [Impl::MaxThreads] |
| Per-thread status. More... | |
| FetchPriority | fetchPolicy |
| Fetch policy. More... | |
| std::list< ThreadID > | priorityList |
| List that has the threads organized by priority. More... | |
| ProbePointArg< DynInstPtr > * | ppFetch |
| Probe points. More... | |
| ProbePointArg< RequestPtr > * | ppFetchRequestSent |
| To probe when a fetch request is successfully sent. More... | |
| O3CPU * | cpu |
| Pointer to the O3CPU. More... | |
| TimeBuffer< TimeStruct > * | timeBuffer |
| Time buffer interface. More... | |
| TimeBuffer< TimeStruct >::wire | fromDecode |
| Wire to get decode's information from backwards time buffer. More... | |
| TimeBuffer< TimeStruct >::wire | fromRename |
| Wire to get rename's information from backwards time buffer. More... | |
| TimeBuffer< TimeStruct >::wire | fromIEW |
| Wire to get iew's information from backwards time buffer. More... | |
| TimeBuffer< TimeStruct >::wire | fromCommit |
| Wire to get commit's information from backwards time buffer. More... | |
| TimeBuffer< FetchStruct >::wire | toDecode |
| Wire used to write any information heading to decode. More... | |
| BPredUnit * | branchPred |
| BPredUnit. More... | |
| TheISA::PCState | pc [Impl::MaxThreads] |
| Addr | fetchOffset [Impl::MaxThreads] |
| StaticInstPtr | macroop [Impl::MaxThreads] |
| bool | delayedCommit [Impl::MaxThreads] |
| Can the fetch stage redirect from an interrupt on this instruction? More... | |
| RequestPtr | memReq [Impl::MaxThreads] |
| Memory request used to access cache. More... | |
| bool | wroteToTimeBuffer |
| Variable that tracks if fetch has written to the time buffer this cycle. More... | |
| int | numInst |
| Tracks how many instructions has been fetched this cycle. More... | |
| Stalls | stalls [Impl::MaxThreads] |
| Tracks which stages are telling fetch to stall. More... | |
| Cycles | decodeToFetchDelay |
| Decode to fetch delay. More... | |
| Cycles | renameToFetchDelay |
| Rename to fetch delay. More... | |
| Cycles | iewToFetchDelay |
| IEW to fetch delay. More... | |
| Cycles | commitToFetchDelay |
| Commit to fetch delay. More... | |
| unsigned | fetchWidth |
| The width of fetch in instructions. More... | |
| unsigned | decodeWidth |
| The width of decode in instructions. More... | |
| bool | cacheBlocked |
| Is the cache blocked? If so no threads can access it. More... | |
| PacketPtr | retryPkt |
| The packet that is waiting to be retried. More... | |
| ThreadID | retryTid |
| The thread that is waiting on the cache to tell fetch to retry. More... | |
| unsigned int | cacheBlkSize |
| Cache block size. More... | |
| unsigned | fetchBufferSize |
| The size of the fetch buffer in bytes. More... | |
| Addr | fetchBufferMask |
| Mask to align a fetch address to a fetch buffer boundary. More... | |
| uint8_t * | fetchBuffer [Impl::MaxThreads] |
| The fetch data that is being fetched and buffered. More... | |
| Addr | fetchBufferPC [Impl::MaxThreads] |
| The PC of the first instruction loaded into the fetch buffer. More... | |
| unsigned | fetchQueueSize |
| The size of the fetch queue in micro-ops. More... | |
| std::deque< DynInstPtr > | fetchQueue [Impl::MaxThreads] |
| Queue of fetched instructions. More... | |
| bool | fetchBufferValid [Impl::MaxThreads] |
| Whether or not the fetch buffer data is valid. More... | |
| int | instSize |
| Size of instructions. More... | |
| Counter | lastIcacheStall [Impl::MaxThreads] |
| Icache stall statistics. More... | |
| std::list< ThreadID > * | activeThreads |
| List of Active Threads. More... | |
| ThreadID | numThreads |
| Number of threads. More... | |
| ThreadID | numFetchingThreads |
| Number of threads that are actively fetching. More... | |
| ThreadID | threadFetched |
| Thread ID being fetched. More... | |
| bool | interruptPending |
| Checks if there is an interrupt pending. More... | |
| bool | issuePipelinedIfetch [Impl::MaxThreads] |
| Set to true if a pipelined I-cache request should be issued. More... | |
| FinishTranslationEvent | finishTranslationEvent |
| Event used to delay fault generation of translation faults. More... | |
| Stats::Scalar | icacheStallCycles |
| Stat for total number of cycles stalled due to an icache miss. More... | |
| Stats::Scalar | fetchedInsts |
| Stat for total number of fetched instructions. More... | |
| Stats::Scalar | fetchedBranches |
| Total number of fetched branches. More... | |
| Stats::Scalar | predictedBranches |
| Stat for total number of predicted branches. More... | |
| Stats::Scalar | fetchCycles |
| Stat for total number of cycles spent fetching. More... | |
| Stats::Scalar | fetchSquashCycles |
| Stat for total number of cycles spent squashing. More... | |
| Stats::Scalar | fetchTlbCycles |
| Stat for total number of cycles spent waiting for translation. More... | |
| Stats::Scalar | fetchIdleCycles |
| Stat for total number of cycles spent blocked due to other stages in the pipeline. More... | |
| Stats::Scalar | fetchBlockedCycles |
| Total number of cycles spent blocked. More... | |
| Stats::Scalar | fetchMiscStallCycles |
| Total number of cycles spent in any other state. More... | |
| Stats::Scalar | fetchPendingDrainCycles |
| Total number of cycles spent in waiting for drains. More... | |
| Stats::Scalar | fetchNoActiveThreadStallCycles |
| Total number of stall cycles caused by no active threads to run. More... | |
| Stats::Scalar | fetchPendingTrapStallCycles |
| Total number of stall cycles caused by pending traps. More... | |
| Stats::Scalar | fetchPendingQuiesceStallCycles |
| Total number of stall cycles caused by pending quiesce instructions. More... | |
| Stats::Scalar | fetchIcacheWaitRetryStallCycles |
| Total number of stall cycles caused by I-cache wait retrys. More... | |
| Stats::Scalar | fetchedCacheLines |
| Stat for total number of fetched cache lines. More... | |
| Stats::Scalar | fetchIcacheSquashes |
| Total number of outstanding icache accesses that were dropped due to a squash. More... | |
| Stats::Scalar | fetchTlbSquashes |
| Total number of outstanding tlb accesses that were dropped due to a squash. More... | |
| Stats::Distribution | fetchNisnDist |
| Distribution of number of instructions fetched each cycle. More... | |
| Stats::Formula | idleRate |
| Rate of how often fetch was idle. More... | |
| Stats::Formula | branchRate |
| Number of branch fetches per cycle. More... | |
| Stats::Formula | fetchRate |
| Number of instruction fetched per cycle. More... | |
DefaultFetch class handles both single threaded and SMT fetch.
Its width is specified by the parameters; each cycle it tries to fetch that many instructions. It supports using a branch predictor to predict direction and targets. It supports the idling functionality of the CPU by indicating to the CPU when it is active and inactive.
| typedef Impl::CPUPol DefaultFetch< Impl >::CPUPol |
| typedef Impl::DynInst DefaultFetch< Impl >::DynInst |
| typedef Impl::DynInstPtr DefaultFetch< Impl >::DynInstPtr |
| typedef TheISA::ExtMachInst DefaultFetch< Impl >::ExtMachInst |
| typedef CPUPol::FetchStruct DefaultFetch< Impl >::FetchStruct |
| typedef TheISA::MachInst DefaultFetch< Impl >::MachInst |
| typedef Impl::O3CPU DefaultFetch< Impl >::O3CPU |
| typedef CPUPol::TimeStruct DefaultFetch< Impl >::TimeStruct |
| enum DefaultFetch::FetchPriority |
| enum DefaultFetch::FetchStatus |
| enum DefaultFetch::ThreadStatus |
| DefaultFetch< Impl >::DefaultFetch | ( | O3CPU * | _cpu, |
| DerivO3CPUParams * | params | ||
| ) |
DefaultFetch constructor.
Definition at line 81 of file fetch_impl.hh.
References DefaultFetch< Impl >::Branch, DefaultFetch< Impl >::branchPred, DefaultFetch< Impl >::cacheBlkSize, DefaultFetch< Impl >::decoder, DPRINTF, fatal, DefaultFetch< Impl >::fetchBuffer, DefaultFetch< Impl >::fetchBufferPC, DefaultFetch< Impl >::fetchBufferSize, DefaultFetch< Impl >::fetchBufferValid, DefaultFetch< Impl >::fetchPolicy, DefaultFetch< Impl >::fetchWidth, ArmISA::i, DefaultFetch< Impl >::instSize, DefaultFetch< Impl >::IQ, DefaultFetch< Impl >::LSQ, DefaultFetch< Impl >::numThreads, panic, DefaultFetch< Impl >::RoundRobin, and DefaultFetch< Impl >::SingleThread.
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Returns the appropriate thread to fetch using the branch count policy.
Definition at line 1602 of file fetch_impl.hh.
References InvalidThreadID, and panic.
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Definition at line 1096 of file fetch_impl.hh.
References curTick(), DPRINTF, and X86ISA::size().
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Check if an interrupt is pending and that we need to handle.
Definition at line 305 of file fetch.hh.
References DefaultFetch< Impl >::interruptPending.
| bool DefaultFetch< Impl >::checkSignalsAndUpdate | ( | ThreadID | tid | ) |
Checks all input signals and updates the status as necessary.
Definition at line 991 of file fetch_impl.hh.
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| void DefaultFetch< Impl >::deactivateThread | ( | ThreadID | tid | ) |
For priority-based fetch policies, need to keep update priorityList.
Definition at line 539 of file fetch_impl.hh.
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Squashes a specific thread and resets the PC.
Definition at line 752 of file fetch_impl.hh.
References DPRINTF, InvalidThreadID, and pc.
| void DefaultFetch< Impl >::drainResume | ( | ) |
| void DefaultFetch< Impl >::drainSanityCheck | ( | ) | const |
Perform sanity checks after a drain.
Definition at line 435 of file fetch_impl.hh.
References ArmISA::i, and InvalidThreadID.
| void DefaultFetch< Impl >::drainStall | ( | ThreadID | tid | ) |
Stall the fetch stage after reaching a safe drain point.
The CPU uses this method to stop fetching instructions from a thread that has been drained. The drain stall is different from all other stalls in that it is signaled instantly from the commit stage (without the normal communication delay) when it has reached a safe point to drain from.
Definition at line 493 of file fetch_impl.hh.
References DPRINTF.
| void DefaultFetch< Impl >::fetch | ( | bool & | status_change | ) |
Does the actual fetching of instructions and passing them on to the next stage.
| status_change | fetch() sets this variable if there was a status change (ie switching to IcacheMissStall). |
Definition at line 1150 of file fetch_impl.hh.
References curTick(), DPRINTF, DTRACE, StaticInst::fetchMicroop(), BigEndianGuest::gtoh(), InvalidThreadID, ISA_HAS_DELAY_SLOT, StaticInst::isLastMicroop(), StaticInst::isMacroop(), isRomMicroPC(), pc, PseudoInst::quiesce(), Running, and X86ISA::size().
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Align a PC to the start of a fetch buffer block.
Definition at line 354 of file fetch.hh.
References DefaultFetch< Impl >::fetchBufferMask.
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Fetches the cache line that contains the fetch PC.
Returns any fault that happened. Puts the data into the class variable fetchBuffer, which may not hold the entire fetched cache line.
| vaddr | The memory address that is being fetched from. |
| ret_fault | The fault reference that will be set to the result of the icache access. |
| tid | Thread id. |
| pc | The actual PC of the current instruction. |
Definition at line 593 of file fetch_impl.hh.
References DPRINTF, BaseTLB::Execute, Request::INST_FETCH, NoFault, pc, and Request::taskId().
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Definition at line 643 of file fetch_impl.hh.
References Request::contextId(), curTick(), Packet::dataDynamic(), DPRINTF, Request::getPaddr(), Request::getVaddr(), InvalidThreadID, NoFault, AlphaISA::NoopMachInst, pc, MemCmd::ReadReq, X86ISA::size(), and warn.
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Returns the appropriate thread to fetch, given the fetch policy.
Definition at line 1455 of file fetch_impl.hh.
References InvalidThreadID, and Running.
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Returns the appropriate thread to fetch using the IQ count policy.
Definition at line 1529 of file fetch_impl.hh.
References InvalidThreadID, and Running.
| bool DefaultFetch< Impl >::isDrained | ( | ) | const |
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Looks up in the branch predictor to see if the next PC should be either next PC+=MachInst or a branch target.
| next_PC | Next PC variable passed in by reference. It is expected to be set to the current PC; it will be updated with what the next PC will be. |
| next_NPC | Used for ISAs which use delay slots. |
Definition at line 550 of file fetch_impl.hh.
References AlphaISA::advancePC(), and DPRINTF.
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Returns the appropriate thread to fetch using the LSQ count policy.
Definition at line 1566 of file fetch_impl.hh.
References InvalidThreadID, and Running.
| std::string DefaultFetch< Impl >::name | ( | ) | const |
Returns the name of fetch.
Definition at line 164 of file fetch_impl.hh.
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Pipeline the next I-cache access to the current one.
Definition at line 1616 of file fetch_impl.hh.
References DPRINTF, isRomMicroPC(), and pc.
| void DefaultFetch< Impl >::processCacheCompletion | ( | PacketPtr | pkt | ) |
Processes cache completion event.
Definition at line 379 of file fetch_impl.hh.
References Request::contextId(), DPRINTF, Packet::getConstPtr(), Packet::req, and Request::setAccessLatency().
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Profile the reasons of fetch stall.
Definition at line 1646 of file fetch_impl.hh.
References DPRINTF.
| void DefaultFetch< Impl >::recvReqRetry | ( | ) |
Handles retrying the fetch access.
Definition at line 1424 of file fetch_impl.hh.
References InvalidThreadID.
| void DefaultFetch< Impl >::regProbePoints | ( | ) |
Registers probes.
Definition at line 171 of file fetch_impl.hh.
| void DefaultFetch< Impl >::regStats | ( | ) |
Registers statistics.
Definition at line 181 of file fetch_impl.hh.
References name(), Stats::pdf, and Stats::total.
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Reset this pipeline stage.
Definition at line 344 of file fetch_impl.hh.
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Returns the appropriate thread to fetch using a round robin policy.
Definition at line 1499 of file fetch_impl.hh.
References InvalidThreadID, and Running.
| void DefaultFetch< Impl >::setActiveThreads | ( | std::list< ThreadID > * | at_ptr | ) |
Sets pointer to list of active threads.
Definition at line 317 of file fetch_impl.hh.
| void DefaultFetch< Impl >::setFetchQueue | ( | TimeBuffer< FetchStruct > * | fq_ptr | ) |
Sets pointer to time buffer used to communicate to the next stage.
Definition at line 324 of file fetch_impl.hh.
References TimeBuffer< T >::getWire().
| void DefaultFetch< Impl >::setTimeBuffer | ( | TimeBuffer< TimeStruct > * | time_buffer | ) |
Sets the main backwards communication time buffer pointer.
Definition at line 304 of file fetch_impl.hh.
References TimeBuffer< T >::getWire().
| void DefaultFetch< Impl >::squash | ( | const TheISA::PCState & | newPC, |
| const InstSeqNum | seq_num, | ||
| DynInstPtr | squashInst, | ||
| ThreadID | tid | ||
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Squashes a specific thread and resets the PC.
Also tells the CPU to remove any instructions that are not in the ROB. The source of this squash should be the commit stage.
Definition at line 875 of file fetch_impl.hh.
References DPRINTF.
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Squashes a specific thread and resets the PC.
Also tells the CPU to remove any instructions between fetch and decode that should be sqaushed.
Definition at line 805 of file fetch_impl.hh.
References DPRINTF.
| void DefaultFetch< Impl >::startupStage | ( | ) |
Initialize stage.
Definition at line 332 of file fetch_impl.hh.
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Changes the status of this stage to active, and indicates this to the CPU.
Definition at line 513 of file fetch_impl.hh.
References DPRINTF.
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Changes the status of this stage to inactive, and indicates this to the CPU.
Definition at line 526 of file fetch_impl.hh.
References DPRINTF.
| void DefaultFetch< Impl >::takeOverFrom | ( | ) |
Takes over from another CPU's thread.
Definition at line 484 of file fetch_impl.hh.
| void DefaultFetch< Impl >::tick | ( | ) |
Ticks the fetch stage, processing all inputs signals and fetching as many instructions as possible.
Definition at line 889 of file fetch_impl.hh.
References DPRINTF, FullSystem, ArmISA::i, Random::random(), and random_mt.
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Updates overall fetch stage status; to be called at the end of each cycle.
Definition at line 835 of file fetch_impl.hh.
| void DefaultFetch< Impl >::wakeFromQuiesce | ( | ) |
Tells fetch to wake up from a quiesce instruction.
Definition at line 503 of file fetch_impl.hh.
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Definition at line 413 of file fetch.hh.
Referenced by DefaultFetch< Impl >::DefaultFetch().
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Cache block size.
Definition at line 472 of file fetch.hh.
Referenced by DefaultFetch< Impl >::DefaultFetch().
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| TheISA::Decoder* DefaultFetch< Impl >::decoder[Impl::MaxThreads] |
The decoder.
Definition at line 360 of file fetch.hh.
Referenced by DefaultFetch< Impl >::DefaultFetch().
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The fetch data that is being fetched and buffered.
Definition at line 483 of file fetch.hh.
Referenced by DefaultFetch< Impl >::DefaultFetch().
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Mask to align a fetch address to a fetch buffer boundary.
Definition at line 480 of file fetch.hh.
Referenced by DefaultFetch< Impl >::fetchBufferAlignPC().
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The PC of the first instruction loaded into the fetch buffer.
Definition at line 486 of file fetch.hh.
Referenced by DefaultFetch< Impl >::DefaultFetch().
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The size of the fetch buffer in bytes.
The fetch buffer itself may be smaller than a cache line.
Definition at line 477 of file fetch.hh.
Referenced by DefaultFetch< Impl >::DefaultFetch().
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Whether or not the fetch buffer data is valid.
Definition at line 495 of file fetch.hh.
Referenced by DefaultFetch< Impl >::DefaultFetch().
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Fetch policy.
Definition at line 193 of file fetch.hh.
Referenced by DefaultFetch< Impl >::DefaultFetch().
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The width of fetch in instructions.
Definition at line 457 of file fetch.hh.
Referenced by DefaultFetch< Impl >::DefaultFetch().
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Size of instructions.
Definition at line 498 of file fetch.hh.
Referenced by DefaultFetch< Impl >::DefaultFetch().
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Checks if there is an interrupt pending.
If there is, fetch must stop once it is not fetching PAL instructions.
Definition at line 518 of file fetch.hh.
Referenced by DefaultFetch< Impl >::checkInterrupt().
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Number of threads.
Definition at line 507 of file fetch.hh.
Referenced by DefaultFetch< Impl >::DefaultFetch().
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