#include <Sequencer.hh>

Inheritance diagram for Sequencer:

Classes
class	SequencerWakeupEvent

Public Types
typedef RubySequencerParams	Params

Public Types inherited from RubyPort
typedef RubyPortParams	Params

Public Types inherited from MemObject
typedef MemObjectParams	Params

Public Types inherited from ClockedObject
typedef ClockedObjectParams	Params
	Parameters of ClockedObject. More...

Public Types inherited from SimObject
typedef SimObjectParams	Params

Public Member Functions
	Sequencer (const Params *)

	~Sequencer ()

void	wakeup ()

void	resetStats ()
	Reset statistics associated with this object. More...

void	collateStats ()

void	regStats ()
	Register statistics for this object. More...

void	writeCallback (Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0))

void	readCallback (Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0))

RequestStatus	makeRequest (PacketPtr pkt)

bool	empty () const

int	outstandingCount () const

bool	isDeadlockEventScheduled () const

void	descheduleDeadlockEvent ()

void	print (std::ostream &out) const

void	checkCoherence (Addr address)

void	markRemoved ()

void	evictionCallback (Addr address)

void	invalidateSC (Addr address)

int	coreId () const

void	recordRequestType (SequencerRequestType requestType)

Stats::Histogram &	getOutstandReqHist ()

Stats::Histogram &	getLatencyHist ()

Stats::Histogram &	getTypeLatencyHist (uint32_t t)

Stats::Histogram &	getHitLatencyHist ()

Stats::Histogram &	getHitTypeLatencyHist (uint32_t t)

Stats::Histogram &	getHitMachLatencyHist (uint32_t t)

Stats::Histogram &	getHitTypeMachLatencyHist (uint32_t r, uint32_t t)

Stats::Histogram &	getMissLatencyHist ()

Stats::Histogram &	getMissTypeLatencyHist (uint32_t t)

Stats::Histogram &	getMissMachLatencyHist (uint32_t t) const

Stats::Histogram &	getMissTypeMachLatencyHist (uint32_t r, uint32_t t) const

Stats::Histogram &	getIssueToInitialDelayHist (uint32_t t) const

Stats::Histogram &	getInitialToForwardDelayHist (const MachineType t) const

Stats::Histogram &	getForwardRequestToFirstResponseHist (const MachineType t) const

Stats::Histogram &	getFirstResponseToCompletionDelayHist (const MachineType t) const

Stats::Counter	getIncompleteTimes (const MachineType t) const

Public Member Functions inherited from RubyPort
	RubyPort (const Params *p)

virtual	~RubyPort ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

BaseMasterPort &	getMasterPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a master port with a given name and index. More...

BaseSlavePort &	getSlavePort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a slave port with a given name and index. More...

void	setController (AbstractController *_cntrl)

uint32_t	getId ()

DrainState	drain () override
	Notify an object that it needs to drain its state. More...

bool	isCPUSequencer ()

Public Member Functions inherited from MemObject
const Params *	params () const

	MemObject (const Params *params)

Public Member Functions inherited from ClockedObject
	ClockedObject (const ClockedObjectParams *p)

const Params *	params () const

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Enums::PwrState	pwrState () const

std::string	pwrStateName () const

std::vector< double >	pwrStateWeights () const
	Returns the percentage residency for each power state. More...

void	computeStats ()
	Record stats values like state residency by computing the time difference from previous update. More...

void	pwrState (Enums::PwrState)

void	regStats () override
	Register statistics for this object. More...

Public Member Functions inherited from SimObject
const Params *	params () const

	SimObject (const Params *_params)

virtual	~SimObject ()

virtual const std::string	name () const

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from EventManager
	EventManager (EventManager &em)

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick)-1)

void	setCurTick (Tick newVal)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from Clocked
void	updateClockPeriod () const
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Private Types
typedef std::unordered_map < Addr, SequencerRequest * >	RequestTable

Private Member Functions
void	issueRequest (PacketPtr pkt, RubyRequestType type)

void	hitCallback (SequencerRequest *request, DataBlock &data, bool llscSuccess, const MachineType mach, const bool externalHit, const Cycles initialRequestTime, const Cycles forwardRequestTime, const Cycles firstResponseTime)

void	recordMissLatency (const Cycles t, const RubyRequestType type, const MachineType respondingMach, bool isExternalHit, Cycles issuedTime, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime, Cycles completionTime)

RequestStatus	insertRequest (PacketPtr pkt, RubyRequestType request_type)

bool	handleLlsc (Addr address, SequencerRequest *request)

	Sequencer (const Sequencer &obj)

Sequencer &	operator= (const Sequencer &obj)

Private Attributes
int	m_max_outstanding_requests

Cycles	m_deadlock_threshold

CacheMemory *	m_dataCache_ptr

CacheMemory *	m_instCache_ptr

Cycles	m_data_cache_hit_latency

Cycles	m_inst_cache_hit_latency

RequestTable	m_writeRequestTable

RequestTable	m_readRequestTable

int	m_outstanding_count

bool	m_deadlock_check_scheduled

Stats::Scalar	m_store_waiting_on_load
	Counters for recording aliasing information. More...

Stats::Scalar	m_store_waiting_on_store

Stats::Scalar	m_load_waiting_on_store

Stats::Scalar	m_load_waiting_on_load

int	m_coreId

bool	m_runningGarnetStandalone

Stats::Histogram	m_outstandReqHist
	Histogram for number of outstanding requests per cycle. More...

Stats::Histogram	m_latencyHist
	Histogram for holding latency profile of all requests. More...

std::vector< Stats::Histogram * >	m_typeLatencyHist

Stats::Histogram	m_hitLatencyHist
	Histogram for holding latency profile of all requests that hit in the controller connected to this sequencer. More...

std::vector< Stats::Histogram * >	m_hitTypeLatencyHist

std::vector< Stats::Histogram * >	m_hitMachLatencyHist
	Histograms for profiling the latencies for requests that did not required external messages. More...

std::vector< std::vector < Stats::Histogram * > >	m_hitTypeMachLatencyHist

Stats::Histogram	m_missLatencyHist
	Histogram for holding latency profile of all requests that miss in the controller connected to this sequencer. More...

std::vector< Stats::Histogram * >	m_missTypeLatencyHist

std::vector< Stats::Histogram * >	m_missMachLatencyHist
	Histograms for profiling the latencies for requests that required external messages. More...

std::vector< std::vector < Stats::Histogram * > >	m_missTypeMachLatencyHist

std::vector< Stats::Histogram * >	m_IssueToInitialDelayHist
	Histograms for recording the breakdown of miss latency. More...

std::vector< Stats::Histogram * >	m_InitialToForwardDelayHist

std::vector< Stats::Histogram * >	m_ForwardToFirstResponseDelayHist

std::vector< Stats::Histogram * >	m_FirstResponseToCompletionDelayHist

std::vector< Stats::Counter >	m_IncompleteTimes

SequencerWakeupEvent	deadlockCheckEvent

Additional Inherited Members
Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Get the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)

static void	unserializeGlobals (CheckpointIn &cp)

Static Public Attributes inherited from Serializable
static int	ckptCount = 0

static int	ckptMaxCount = 0

static int	ckptPrevCount = -1

Protected Member Functions inherited from RubyPort
void	trySendRetries ()

void	ruby_hit_callback (PacketPtr pkt)

void	testDrainComplete ()

void	ruby_eviction_callback (Addr address)

bool	recvTimingResp (PacketPtr pkt, PortID master_port_id)
	Called by the PIO port when receiving a timing response. More...

Protected Member Functions inherited from Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

Protected Attributes inherited from RubyPort
RubySystem *	m_ruby_system

uint32_t	m_version

AbstractController *	m_controller

MessageBuffer *	m_mandatory_q_ptr

bool	m_usingRubyTester

System *	system

std::vector< MemSlavePort * >	slave_ports

Protected Attributes inherited from ClockedObject
Enums::PwrState	_currPwrState
	To keep track of the current power state. More...

Tick	prvEvalTick

Stats::Scalar	numPwrStateTransitions

Stats::Distribution	pwrStateClkGateDist

Stats::Vector	pwrStateResidencyTicks

Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Detailed Description

Definition at line 57 of file Sequencer.hh.

Member Typedef Documentation

typedef RubySequencerParams Sequencer::Params

Definition at line 60 of file Sequencer.hh.

typedef std::unordered_map<Addr, SequencerRequest*> Sequencer::RequestTable

private

Definition at line 189 of file Sequencer.hh.

Constructor & Destructor Documentation

Sequencer::Sequencer ( const Params * p )

Definition at line 55 of file Sequencer.cc.

References m_coreId, m_data_cache_hit_latency, m_dataCache_ptr, m_deadlock_threshold, m_inst_cache_hit_latency, m_instCache_ptr, m_max_outstanding_requests, m_outstanding_count, and m_runningGarnetStandalone.

Sequencer::~Sequencer ( )

Definition at line 78 of file Sequencer.cc.

Sequencer::Sequencer ( const Sequencer & obj )

private

Member Function Documentation

void Sequencer::checkCoherence ( Addr address )

Definition at line 704 of file Sequencer.cc.

References RubyPort::m_ruby_system.

void Sequencer::collateStats ( )

int Sequencer::coreId ( ) const

inline

Definition at line 102 of file Sequencer.hh.

References m_coreId.

Referenced by issueRequest().

void Sequencer::descheduleDeadlockEvent ( )

inlinevirtual

Implements RubyPort.

Definition at line 93 of file Sequencer.hh.

References deadlockCheckEvent, and EventManager::deschedule().

bool Sequencer::empty ( ) const

Definition at line 531 of file Sequencer.cc.

References m_readRequestTable, and m_writeRequestTable.

void Sequencer::evictionCallback ( Addr address )

Definition at line 719 of file Sequencer.cc.

References RubyPort::ruby_eviction_callback().

Stats::Histogram& Sequencer::getFirstResponseToCompletionDelayHist ( const MachineType t ) const

inline

Definition at line 145 of file Sequencer.hh.

References m_FirstResponseToCompletionDelayHist, and ArmISA::t.

Stats::Histogram& Sequencer::getForwardRequestToFirstResponseHist ( const MachineType t ) const

inline

Definition at line 141 of file Sequencer.hh.

References m_ForwardToFirstResponseDelayHist, and ArmISA::t.

Stats::Histogram& Sequencer::getHitLatencyHist ( )

inline

Definition at line 111 of file Sequencer.hh.

References m_hitLatencyHist.

Referenced by Profiler::collateStats().

Stats::Histogram& Sequencer::getHitMachLatencyHist ( uint32_t t )

inline

Definition at line 115 of file Sequencer.hh.

References m_hitMachLatencyHist, and ArmISA::t.

Referenced by Profiler::collateStats().

Stats::Histogram& Sequencer::getHitTypeLatencyHist ( uint32_t t )

inline

Definition at line 112 of file Sequencer.hh.

References m_hitTypeLatencyHist, and ArmISA::t.

Referenced by Profiler::collateStats().

Stats::Histogram& Sequencer::getHitTypeMachLatencyHist	(	uint32_t	r,
		uint32_t	t
	)

inline

Definition at line 118 of file Sequencer.hh.

References m_hitTypeMachLatencyHist, MipsISA::r, and ArmISA::t.

Referenced by Profiler::collateStats().

Stats::Counter Sequencer::getIncompleteTimes ( const MachineType t ) const

inline

Definition at line 148 of file Sequencer.hh.

References m_IncompleteTimes, and ArmISA::t.

Referenced by Profiler::collateStats().

Stats::Histogram& Sequencer::getInitialToForwardDelayHist ( const MachineType t ) const

inline

Definition at line 137 of file Sequencer.hh.

References m_InitialToForwardDelayHist, and ArmISA::t.

Referenced by Profiler::collateStats().

Stats::Histogram& Sequencer::getIssueToInitialDelayHist ( uint32_t t ) const

inline

Definition at line 133 of file Sequencer.hh.

References m_IssueToInitialDelayHist, and ArmISA::t.

Referenced by Profiler::collateStats().

Stats::Histogram& Sequencer::getLatencyHist ( )

inline

Definition at line 107 of file Sequencer.hh.

References m_latencyHist.

Referenced by Profiler::collateStats().

Stats::Histogram& Sequencer::getMissLatencyHist ( )

inline

Definition at line 121 of file Sequencer.hh.

References m_missLatencyHist.

Referenced by Profiler::collateStats().

Stats::Histogram& Sequencer::getMissMachLatencyHist ( uint32_t t ) const

inline

Definition at line 126 of file Sequencer.hh.

References m_missMachLatencyHist, and ArmISA::t.

Referenced by Profiler::collateStats().

Stats::Histogram& Sequencer::getMissTypeLatencyHist ( uint32_t t )

inline

Definition at line 123 of file Sequencer.hh.

References m_missTypeLatencyHist, and ArmISA::t.

Referenced by Profiler::collateStats().

Stats::Histogram& Sequencer::getMissTypeMachLatencyHist	(	uint32_t	r,
		uint32_t	t
	)		const

inline

Definition at line 130 of file Sequencer.hh.

References m_missTypeMachLatencyHist, MipsISA::r, and ArmISA::t.

Referenced by Profiler::collateStats().

Stats::Histogram& Sequencer::getOutstandReqHist ( )

inline

Definition at line 105 of file Sequencer.hh.

References m_outstandReqHist.

Referenced by Profiler::collateStats().

Stats::Histogram& Sequencer::getTypeLatencyHist ( uint32_t t )

inline

Definition at line 108 of file Sequencer.hh.

References m_typeLatencyHist, and ArmISA::t.

Referenced by Profiler::collateStats().

bool Sequencer::handleLlsc	(	Addr	address,
		SequencerRequest *	request
	)

private

Definition at line 268 of file Sequencer.cc.

References AbstractCacheEntry::clearLocked(), ArmISA::e, AbstractCacheEntry::isLocked(), CacheMemory::lookup(), m_dataCache_ptr, SequencerRequest::m_type, RubyPort::m_version, SequencerRequest::pkt, Packet::req, Request::setExtraData(), and AbstractCacheEntry::setLocked().

Referenced by writeCallback().

void Sequencer::hitCallback	(	SequencerRequest *	request,
		DataBlock &	data,
		bool	llscSuccess,
		const MachineType	mach,
		const bool	externalHit,
		const Cycles	initialRequestTime,
		const Cycles	forwardRequestTime,
		const Cycles	firstResponseTime
	)

private

Definition at line 439 of file Sequencer.cc.

References Packet::cmdString(), Clocked::curCycle(), curTick(), DPRINTF, DPRINTFR, CacheRecorder::enqueueNextFetchRequest(), CacheRecorder::enqueueNextFlushRequest(), Packet::findNextSenderState(), Packet::getAddr(), Packet::getConstPtr(), RubySystem::getCooldownEnabled(), DataBlock::getData(), getOffset(), Packet::getPtr(), Packet::getSize(), RubySystem::getWarmupEnabled(), Packet::isFlush(), SequencerRequest::issue_time, Request::isSwap(), RubySystem::m_cache_recorder, RubyPort::m_ruby_system, SequencerRequest::m_type, RubyPort::m_usingRubyTester, RubyPort::m_version, SequencerRequest::pkt, printAddress(), recordMissLatency(), Packet::req, ArmISA::rs, RubyPort::ruby_hit_callback(), DataBlock::setData(), RubyPort::testDrainComplete(), X86ISA::type, and warn_once.

Referenced by readCallback(), and writeCallback().

RequestStatus Sequencer::insertRequest	(	PacketPtr	pkt,
		RubyRequestType	request_type
	)

private

void Sequencer::invalidateSC ( Addr address )

Definition at line 257 of file Sequencer.cc.

References AbstractCacheEntry::clearLocked(), ArmISA::e, AbstractCacheEntry::isLocked(), CacheMemory::lookup(), m_dataCache_ptr, and RubyPort::m_version.

bool Sequencer::isDeadlockEventScheduled ( ) const

inlinevirtual

Implements RubyPort.

Definition at line 90 of file Sequencer.hh.

References deadlockCheckEvent, and Event::scheduled().

void Sequencer::issueRequest	(	PacketPtr	pkt,
		RubyRequestType	type
	)

private

Definition at line 627 of file Sequencer.cc.

References Clocked::clockEdge(), Request::contextId(), coreId(), curTick(), Clocked::cyclesToTicks(), DPRINTFR, MessageBuffer::enqueue(), Packet::getAddr(), Request::getPC(), Packet::getPtr(), Packet::getSize(), Request::hasContextId(), Request::hasPC(), InvalidContextID, Packet::isFlush(), m_data_cache_hit_latency, m_inst_cache_hit_latency, RubyPort::m_mandatory_q_ptr, RubyPort::m_version, pc, printAddress(), and Packet::req.

Referenced by makeRequest().

RequestStatus Sequencer::makeRequest ( PacketPtr pkt )

virtual

Implements RubyPort.

Definition at line 537 of file Sequencer.cc.

References DPRINTF, X86ISA::FlagShift, System::getArch(), Request::getFlags(), insertRequest(), Packet::isFlush(), Request::isInstFetch(), Packet::isLLSC(), Request::isLockedRMW(), Packet::isRead(), issueRequest(), Packet::isWrite(), m_max_outstanding_requests, m_outstanding_count, panic, Packet::req, ArmISA::status, X86ISA::StoreCheck, and RubyPort::system.

Referenced by CacheRecorder::enqueueNextFetchRequest(), and CacheRecorder::enqueueNextFlushRequest().

void Sequencer::markRemoved ( )

Definition at line 249 of file Sequencer.cc.

References m_outstanding_count, m_readRequestTable, and m_writeRequestTable.

Referenced by readCallback(), and writeCallback().

Sequencer& Sequencer::operator= ( const Sequencer & obj )

private

int Sequencer::outstandingCount ( ) const

inlinevirtual

Implements RubyPort.

Definition at line 88 of file Sequencer.hh.

References m_outstanding_count.

void Sequencer::print ( std::ostream & out ) const

Definition at line 691 of file Sequencer.cc.

References m_outstanding_count, m_readRequestTable, RubyPort::m_version, and m_writeRequestTable.

Referenced by operator<<().

void Sequencer::readCallback	(	Addr	address,
		DataBlock &	data,
		const bool	externalHit = `false`,
		const MachineType	mach = `MachineType_NUM`,
		const Cycles	initialRequestTime = `Cycles(0)`,
		const Cycles	forwardRequestTime = `Cycles(0)`,
		const Cycles	firstResponseTime = `Cycles(0)`
	)

Definition at line 415 of file Sequencer.cc.

References hitCallback(), ArmISA::i, m_readRequestTable, makeLineAddress(), and markRemoved().

void Sequencer::recordMissLatency	(	const Cycles	t,
		const RubyRequestType	type,
		const MachineType	respondingMach,
		bool	isExternalHit,
		Cycles	issuedTime,
		Cycles	initialRequestTime,
		Cycles	forwardRequestTime,
		Cycles	firstResponseTime,
		Cycles	completionTime
	)

private

void Sequencer::recordRequestType ( SequencerRequestType requestType )

Definition at line 712 of file Sequencer.cc.

References DPRINTF.

void Sequencer::regStats ( )

virtual

Register statistics for this object.

Reimplemented from SimObject.

Definition at line 725 of file Sequencer.cc.

References Stats::DataWrap< Derived, InfoProxyType >::desc(), Stats::DataWrap< Derived, InfoProxyType >::flags(), ArmISA::i, Stats::Histogram::init(), ArmISA::j, m_FirstResponseToCompletionDelayHist, m_ForwardToFirstResponseDelayHist, m_hitLatencyHist, m_hitMachLatencyHist, m_hitTypeLatencyHist, m_hitTypeMachLatencyHist, m_InitialToForwardDelayHist, m_IssueToInitialDelayHist, m_latencyHist, m_load_waiting_on_load, m_load_waiting_on_store, m_missLatencyHist, m_missMachLatencyHist, m_missTypeLatencyHist, m_missTypeMachLatencyHist, m_outstandReqHist, m_store_waiting_on_load, m_store_waiting_on_store, m_typeLatencyHist, SimObject::name(), Stats::DataWrap< Derived, InfoProxyType >::name(), Stats::nozero, and ClockedObject::regStats().

void Sequencer::resetStats ( )

virtual

Reset statistics associated with this object.

Reimplemented from SimObject.

Definition at line 134 of file Sequencer.cc.

References ArmISA::i, ArmISA::j, m_FirstResponseToCompletionDelayHist, m_ForwardToFirstResponseDelayHist, m_hitLatencyHist, m_hitMachLatencyHist, m_hitTypeLatencyHist, m_hitTypeMachLatencyHist, m_IncompleteTimes, m_InitialToForwardDelayHist, m_IssueToInitialDelayHist, m_latencyHist, m_missLatencyHist, m_missMachLatencyHist, m_missTypeLatencyHist, m_missTypeMachLatencyHist, m_typeLatencyHist, and Stats::DistBase< Derived, Stor >::reset().

void Sequencer::wakeup ( )

Definition at line 83 of file Sequencer.cc.

References Clocked::clockEdge(), Clocked::clockPeriod(), Clocked::curCycle(), deadlockCheckEvent, Draining, Drainable::drainState(), Packet::getAddr(), SequencerRequest::issue_time, m_deadlock_threshold, m_outstanding_count, m_readRequestTable, RubyPort::m_version, m_writeRequestTable, panic, SequencerRequest::pkt, and EventManager::schedule().

Referenced by Sequencer::SequencerWakeupEvent::process().

void Sequencer::writeCallback	(	Addr	address,
		DataBlock &	data,
		const bool	externalHit = `false`,
		const MachineType	mach = `MachineType_NUM`,
		const Cycles	initialRequestTime = `Cycles(0)`,
		const Cycles	forwardRequestTime = `Cycles(0)`,
		const Cycles	firstResponseTime = `Cycles(0)`
	)