| _currPwrState | ClockedObject | protected |
| _params | SimObject | protected |
| checkCoherence(Addr address) | Sequencer | |
| ckptCount | Serializable | static |
| ckptMaxCount | Serializable | static |
| ckptPrevCount | Serializable | static |
| Clocked(ClockDomain &clk_domain) | Clocked | inlineprotected |
| Clocked(Clocked &)=delete | Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | Clocked | inline |
| ClockedObject(const ClockedObjectParams *p) | ClockedObject | |
| clockPeriod() const | Clocked | inline |
| collateStats() | Sequencer | |
| computeStats() | ClockedObject | |
| coreId() const | Sequencer | inline |
| curCycle() const | Clocked | inline |
| currentSection() | Serializable | static |
| cyclesToTicks(Cycles c) const | Clocked | inline |
| deadlockCheckEvent | Sequencer | private |
| deschedule(Event &event) | EventManager | inline |
| deschedule(Event *event) | EventManager | inline |
| descheduleDeadlockEvent() | Sequencer | inlinevirtual |
| drain() override | RubyPort | virtual |
| Drainable() | Drainable | protected |
| drainResume() | Drainable | inlineprotectedvirtual |
| drainState() const | Drainable | inline |
| empty() const | Sequencer | |
| EventManager(EventManager &em) | EventManager | inline |
| EventManager(EventManager *em) | EventManager | inline |
| EventManager(EventQueue *eq) | EventManager | inline |
| eventq | EventManager | protected |
| eventQueue() const | EventManager | inline |
| evictionCallback(Addr address) | Sequencer | |
| find(const char *name) | SimObject | static |
| frequency() const | Clocked | inline |
| getFirstResponseToCompletionDelayHist(const MachineType t) const | Sequencer | inline |
| getForwardRequestToFirstResponseHist(const MachineType t) const | Sequencer | inline |
| getHitLatencyHist() | Sequencer | inline |
| getHitMachLatencyHist(uint32_t t) | Sequencer | inline |
| getHitTypeLatencyHist(uint32_t t) | Sequencer | inline |
| getHitTypeMachLatencyHist(uint32_t r, uint32_t t) | Sequencer | inline |
| getId() | RubyPort | inline |
| getIncompleteTimes(const MachineType t) const | Sequencer | inline |
| getInitialToForwardDelayHist(const MachineType t) const | Sequencer | inline |
| getIssueToInitialDelayHist(uint32_t t) const | Sequencer | inline |
| getLatencyHist() | Sequencer | inline |
| getMasterPort(const std::string &if_name, PortID idx=InvalidPortID) override | RubyPort | virtual |
| getMissLatencyHist() | Sequencer | inline |
| getMissMachLatencyHist(uint32_t t) const | Sequencer | inline |
| getMissTypeLatencyHist(uint32_t t) | Sequencer | inline |
| getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const | Sequencer | inline |
| getOutstandReqHist() | Sequencer | inline |
| getProbeManager() | SimObject | |
| getSlavePort(const std::string &if_name, PortID idx=InvalidPortID) override | RubyPort | virtual |
| getTypeLatencyHist(uint32_t t) | Sequencer | inline |
| handleLlsc(Addr address, SequencerRequest *request) | Sequencer | private |
| hitCallback(SequencerRequest *request, DataBlock &data, bool llscSuccess, const MachineType mach, const bool externalHit, const Cycles initialRequestTime, const Cycles forwardRequestTime, const Cycles firstResponseTime) | Sequencer | private |
| init() override | RubyPort | virtual |
| initState() | SimObject | virtual |
| insertRequest(PacketPtr pkt, RubyRequestType request_type) | Sequencer | private |
| invalidateSC(Addr address) | Sequencer | |
| isCPUSequencer() | RubyPort | inline |
| isDeadlockEventScheduled() const | Sequencer | inlinevirtual |
| issueRequest(PacketPtr pkt, RubyRequestType type) | Sequencer | private |
| loadState(CheckpointIn &cp) | SimObject | virtual |
| m_controller | RubyPort | protected |
| m_coreId | Sequencer | private |
| m_data_cache_hit_latency | Sequencer | private |
| m_dataCache_ptr | Sequencer | private |
| m_deadlock_check_scheduled | Sequencer | private |
| m_deadlock_threshold | Sequencer | private |
| m_FirstResponseToCompletionDelayHist | Sequencer | private |
| m_ForwardToFirstResponseDelayHist | Sequencer | private |
| m_hitLatencyHist | Sequencer | private |
| m_hitMachLatencyHist | Sequencer | private |
| m_hitTypeLatencyHist | Sequencer | private |
| m_hitTypeMachLatencyHist | Sequencer | private |
| m_IncompleteTimes | Sequencer | private |
| m_InitialToForwardDelayHist | Sequencer | private |
| m_inst_cache_hit_latency | Sequencer | private |
| m_instCache_ptr | Sequencer | private |
| m_IssueToInitialDelayHist | Sequencer | private |
| m_latencyHist | Sequencer | private |
| m_load_waiting_on_load | Sequencer | private |
| m_load_waiting_on_store | Sequencer | private |
| m_mandatory_q_ptr | RubyPort | protected |
| m_max_outstanding_requests | Sequencer | private |
| m_missLatencyHist | Sequencer | private |
| m_missMachLatencyHist | Sequencer | private |
| m_missTypeLatencyHist | Sequencer | private |
| m_missTypeMachLatencyHist | Sequencer | private |
| m_outstanding_count | Sequencer | private |
| m_outstandReqHist | Sequencer | private |
| m_readRequestTable | Sequencer | private |
| m_ruby_system | RubyPort | protected |
| m_runningGarnetStandalone | Sequencer | private |
| m_store_waiting_on_load | Sequencer | private |
| m_store_waiting_on_store | Sequencer | private |
| m_typeLatencyHist | Sequencer | private |
| m_usingRubyTester | RubyPort | protected |
| m_version | RubyPort | protected |
| m_writeRequestTable | Sequencer | private |
| makeRequest(PacketPtr pkt) | Sequencer | virtual |
| markRemoved() | Sequencer | |
| memInvalidate() | SimObject | inlinevirtual |
| MemObject(const Params *params) | MemObject | |
| memWriteback() | SimObject | inlinevirtual |
| name() const | SimObject | inlinevirtual |
| nextCycle() const | Clocked | inline |
| notifyFork() | Drainable | inlinevirtual |
| numPwrStateTransitions | ClockedObject | protected |
| operator=(const Sequencer &obj) | Sequencer | private |
| RubyPort::operator=(Clocked &)=delete | Clocked | protected |
| outstandingCount() const | Sequencer | inlinevirtual |
| params() const | MemObject | inline |
| Params typedef | Sequencer | |
| print(std::ostream &out) const | Sequencer | |
| prvEvalTick | ClockedObject | protected |
| pwrState() const | ClockedObject | inline |
| pwrState(Enums::PwrState) | ClockedObject | |
| pwrStateClkGateDist | ClockedObject | protected |
| pwrStateName() const | ClockedObject | inline |
| pwrStateResidencyTicks | ClockedObject | protected |
| pwrStateWeights() const | ClockedObject | |
| readCallback(Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0)) | Sequencer | |
| recordMissLatency(const Cycles t, const RubyRequestType type, const MachineType respondingMach, bool isExternalHit, Cycles issuedTime, Cycles initialRequestTime, Cycles forwardRequestTime, Cycles firstResponseTime, Cycles completionTime) | Sequencer | private |
| recordRequestType(SequencerRequestType requestType) | Sequencer | |
| recvTimingResp(PacketPtr pkt, PortID master_port_id) | RubyPort | protected |
| regProbeListeners() | SimObject | virtual |
| regProbePoints() | SimObject | virtual |
| regStats() | Sequencer | virtual |
| RequestTable typedef | Sequencer | private |
| reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
| resetClock() const | Clocked | inlineprotected |
| resetStats() | Sequencer | virtual |
| ruby_eviction_callback(Addr address) | RubyPort | protected |
| ruby_hit_callback(PacketPtr pkt) | RubyPort | protected |
| RubyPort(const Params *p) | RubyPort | |
| schedule(Event &event, Tick when) | EventManager | inline |
| schedule(Event *event, Tick when) | EventManager | inline |
| Sequencer(const Params *) | Sequencer | |
| Sequencer(const Sequencer &obj) | Sequencer | private |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | ClockedObject | virtual |
| serializeAll(CheckpointOut &cp) | SimObject | static |
| Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| setController(AbstractController *_cntrl) | RubyPort | inline |
| setCurTick(Tick newVal) | EventManager | inline |
| signalDrainDone() const | Drainable | inlineprotected |
| SimObject(const Params *_params) | SimObject | |
| slave_ports | RubyPort | protected |
| startup() | SimObject | virtual |
| system | RubyPort | protected |
| testDrainComplete() | RubyPort | protected |
| ticksToCycles(Tick t) const | Clocked | inline |
| trySendRetries() | RubyPort | protected |
| unserialize(CheckpointIn &cp) override | ClockedObject | virtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| updateClockPeriod() const | Clocked | inline |
| voltage() const | Clocked | inline |
| wakeup() | Sequencer | |
| wakeupEventQueue(Tick when=(Tick)-1) | EventManager | inline |
| writeCallback(Addr address, DataBlock &data, const bool externalHit=false, const MachineType mach=MachineType_NUM, const Cycles initialRequestTime=Cycles(0), const Cycles forwardRequestTime=Cycles(0), const Cycles firstResponseTime=Cycles(0)) | Sequencer | |
| ~Clocked() | Clocked | inlineprotectedvirtual |
| ~Drainable() | Drainable | protectedvirtual |
| ~RubyPort() | RubyPort | inlinevirtual |
| ~Sequencer() | Sequencer | |
| ~Serializable() | Serializable | virtual |
| ~SimObject() | SimObject | virtual |
