gem5
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A stage responsible for fetching "lines" from memory and passing them to Fetch2. More...
#include <fetch1.hh>
Classes | |
struct | Fetch1ThreadInfo |
Stage cycle-by-cycle state. More... | |
class | FetchRequest |
Memory access queuing. More... | |
class | IcachePort |
Exposable fetch port. More... | |
Public Member Functions | |
Fetch1 (const std::string &name_, MinorCPU &cpu_, MinorCPUParams ¶ms, Latch< BranchData >::Output inp_, Latch< ForwardLineData >::Input out_, Latch< BranchData >::Output prediction_, std::vector< InputBuffer< ForwardLineData >> &next_stage_input_buffer) | |
MinorCPU::MinorCPUPort & | getIcachePort () |
Returns the IcachePort owned by this Fetch1. More... | |
void | evaluate () |
Pass on input/buffer data to the output if you can. More... | |
void | wakeupFetch (ThreadID tid) |
Initiate fetch1 fetching. More... | |
void | minorTrace () const |
bool | isDrained () |
Is this stage drained? For Fetch1, draining is initiated by Execute signalling a branch with the reason HaltFetch. More... | |
Public Member Functions inherited from Named | |
Named (const std::string &name_) | |
const std::string & | name () const |
Protected Types | |
enum | FetchState { FetchHalted, FetchWaitingForPC, FetchRunning } |
Cycle-by-cycle state. More... | |
enum | IcacheState { IcacheRunning, IcacheNeedsRetry } |
State of memory access for head instruction fetch. More... | |
typedef FetchRequest * | FetchRequestPtr |
typedef Queue< FetchRequestPtr, ReportTraitsPtrAdaptor < FetchRequestPtr > , NoBubbleTraits < FetchRequestPtr > > | FetchQueue |
Protected Member Functions | |
void | changeStream (const BranchData &branch) |
Start fetching from a new address. More... | |
void | updateExpectedSeqNums (const BranchData &branch) |
Update streamSeqNum and predictionSeqNum from the given branch (and assume these have changed and discard (on delivery) all lines in flight) More... | |
void | processResponse (FetchRequestPtr response, ForwardLineData &line) |
Convert a response to a ForwardLineData. More... | |
ThreadID | getScheduledThread () |
Use the current threading policy to determine the next thread to fetch from. More... | |
void | fetchLine (ThreadID tid) |
Insert a line fetch into the requests. More... | |
void | tryToSendToTransfers (FetchRequestPtr request) |
Try and issue a fetch for a translated request at the head of the requests queue. More... | |
bool | tryToSend (FetchRequestPtr request) |
Try to send (or resend) a memory request's next/only packet to the memory system. More... | |
void | moveFromRequestsToTransfers (FetchRequestPtr request) |
Move a request between queues. More... | |
void | stepQueues () |
Step requests along between requests and transfers queues. More... | |
void | popAndDiscard (FetchQueue &queue) |
Pop a request from the given queue and correctly deallocate and discard it. More... | |
void | handleTLBResponse (FetchRequestPtr response) |
Handle pushing a TLB response onto the right queue. More... | |
unsigned int | numInFlightFetches () |
Returns the total number of queue occupancy, in-ITLB and in-memory system fetches. More... | |
void | minorTraceResponseLine (const std::string &name, FetchRequestPtr response) const |
Print the appropriate MinorLine line for a fetch response. More... | |
virtual bool | recvTimingResp (PacketPtr pkt) |
Memory interface. More... | |
virtual void | recvReqRetry () |
Protected Attributes | |
MinorCPU & | cpu |
Construction-assigned data members. More... | |
Latch< BranchData >::Output | inp |
Input port carrying branch requests from Execute. More... | |
Latch< ForwardLineData >::Input | out |
Output port carrying read lines to Fetch2. More... | |
Latch< BranchData >::Output | prediction |
Input port carrying branch predictions from Fetch2. More... | |
std::vector< InputBuffer < ForwardLineData > > & | nextStageReserve |
Interface to reserve space in the next stage. More... | |
IcachePort | icachePort |
IcachePort to pass to the CPU. More... | |
unsigned int | lineSnap |
Line snap size in bytes. More... | |
unsigned int | maxLineWidth |
Maximum fetch width in bytes. More... | |
unsigned int | fetchLimit |
Maximum number of fetches allowed in flight (in queues or memory) More... | |
std::vector< Fetch1ThreadInfo > | fetchInfo |
ThreadID | threadPriority |
FetchQueue | requests |
Queue of address translated requests from Fetch1. More... | |
FetchQueue | transfers |
Queue of in-memory system requests and responses. More... | |
IcacheState | icacheState |
Retry state of icache_port. More... | |
InstSeqNum | lineSeqNum |
Sequence number for line fetch used for ordering lines to flush. More... | |
unsigned int | numFetchesInMemorySystem |
Count of the number fetches which have left the transfers queue and are in the 'wild' in the memory system. More... | |
unsigned int | numFetchesInITLB |
Number of requests inside the ITLB rather than in the queues. More... | |
Protected Attributes inherited from Named | |
const std::string | _name |
Friends | |
std::ostream & | operator<< (std::ostream &os, Fetch1::FetchState state) |
std::ostream & | operator<< (std::ostream &os, IcacheState state) |
A stage responsible for fetching "lines" from memory and passing them to Fetch2.
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Minor::Fetch1::Fetch1 | ( | const std::string & | name_, |
MinorCPU & | cpu_, | ||
MinorCPUParams & | params, | ||
Latch< BranchData >::Output | inp_, | ||
Latch< ForwardLineData >::Input | out_, | ||
Latch< BranchData >::Output | prediction_, | ||
std::vector< InputBuffer< ForwardLineData >> & | next_stage_input_buffer | ||
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Definition at line 55 of file fetch1.cc.
References cpu, DPRINTF, fatal, fetchLimit, lineSnap, and maxLineWidth.
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Start fetching from a new address.
Definition at line 488 of file fetch1.cc.
References DPRINTF, FetchHalted, fetchInfo, FetchRunning, FetchWaitingForPC, Minor::BranchData::HaltFetch, Minor::Fetch1::Fetch1ThreadInfo::pc, Minor::BranchData::reason, Minor::Fetch1::Fetch1ThreadInfo::state, Minor::BranchData::SuspendThread, Minor::BranchData::target, Minor::BranchData::threadId, updateExpectedSeqNums(), and Minor::Fetch1::Fetch1ThreadInfo::wakeupGuard.
Referenced by evaluate().
void Minor::Fetch1::evaluate | ( | ) |
Pass on input/buffer data to the output if you can.
Are both branches from later stages valid and for the same thread?
Definition at line 572 of file fetch1.cc.
References ActivityRecorder::activity(), MinorCPU::activityRecorder, changeStream(), cpu, DPRINTF, Minor::Queue< ElemType, ReportTraits, BubbleTraits >::empty(), Minor::Pipeline::Fetch1StageId, FetchHalted, fetchInfo, fetchLimit, fetchLine(), Minor::Queue< ElemType, ReportTraits, BubbleTraits >::front(), getScheduledThread(), Minor::Fetch1::FetchRequest::id, inp, InvalidThreadID, Minor::BranchData::isBubble(), Minor::ForwardLineData::isBubble(), Minor::Fetch1::FetchRequest::isComplete(), Minor::Fetch1::FetchRequest::isDiscardable(), Minor::BranchData::isStreamChange(), Minor::BranchData::newStreamSeqNum, nextStageReserve, numInFlightFetches(), out, popAndDiscard(), prediction, processResponse(), Minor::Fetch1::Fetch1ThreadInfo::state, stepQueues(), Minor::Fetch1::Fetch1ThreadInfo::streamSeqNum, Minor::InstId::threadId, Minor::BranchData::threadId, transfers, and MinorCPU::wakeupOnEvent().
Referenced by Minor::Pipeline::evaluate().
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Insert a line fetch into the requests.
This can be a partial line request where the given address has a non-0 offset into a line.
Definition at line 148 of file fetch1.cc.
References cpu, DPRINTF, BaseTLB::Execute, fetchInfo, Minor::Fetch1::FetchRequest::id, Request::INST_FETCH, Minor::Fetch1::FetchRequest::InTranslation, lineSeqNum, lineSnap, maxLineWidth, numFetchesInITLB, Minor::Fetch1::Fetch1ThreadInfo::pc, Minor::Fetch1::Fetch1ThreadInfo::predictionSeqNum, Minor::Queue< ElemType, ReportTraits, BubbleTraits >::push(), Minor::Fetch1::FetchRequest::request, requests, Minor::Queue< ElemType, ReportTraits, BubbleTraits >::reserve(), Request::setContext(), Request::setVirt(), Minor::Fetch1::FetchRequest::state, Minor::Fetch1::Fetch1ThreadInfo::streamSeqNum, Minor::InstId::threadId, MinorCPU::threads, and transfers.
Referenced by evaluate().
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Returns the IcachePort owned by this Fetch1.
Definition at line 393 of file fetch1.hh.
References icachePort.
Referenced by Minor::Pipeline::getInstPort().
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Use the current threading policy to determine the next thread to fetch from.
Definition at line 116 of file fetch1.cc.
References ThreadContext::Active, cpu, fetchInfo, FetchRunning, InvalidThreadID, panic, MinorCPU::randomPriority(), MinorCPU::roundRobinPriority(), MinorCPU::threadPolicy, and threadPriority.
Referenced by evaluate().
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Handle pushing a TLB response onto the right queue.
Definition at line 253 of file fetch1.cc.
References DPRINTF, DTRACE, Minor::Fetch1::FetchRequest::fault, Request::getPaddr(), Request::getVaddr(), Request::hasPaddr(), minorTraceResponseLine(), Named::name(), NoFault, numFetchesInITLB, Minor::Fetch1::FetchRequest::request, Minor::Fetch1::FetchRequest::state, Minor::Fetch1::FetchRequest::Translated, and tryToSendToTransfers().
bool Minor::Fetch1::isDrained | ( | ) |
Is this stage drained? For Fetch1, draining is initiated by Execute signalling a branch with the reason HaltFetch.
Definition at line 727 of file fetch1.cc.
References cpu, DPRINTF, FetchHalted, fetchInfo, FetchRunning, numInFlightFetches(), out, and Minor::Fetch1::Fetch1ThreadInfo::state.
Referenced by Minor::Pipeline::isDrained().
void Minor::Fetch1::minorTrace | ( | ) | const |
Definition at line 761 of file fetch1.cc.
References Minor::Fetch1::Fetch1ThreadInfo::blocked, data, fetchInfo, icacheState, MINORTRACE, Minor::Queue< ElemType, ReportTraits, BubbleTraits >::minorTrace(), numFetchesInITLB, numFetchesInMemorySystem, out, requests, Minor::Fetch1::Fetch1ThreadInfo::state, Minor::Fetch1::Fetch1ThreadInfo::streamSeqNum, and transfers.
Referenced by Minor::Pipeline::minorTrace().
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Print the appropriate MinorLine line for a fetch response.
Definition at line 397 of file fetch1.cc.
References Minor::Fetch1::FetchRequest::fault, Minor::Fetch1::FetchRequest::id, Packet::isError(), M5_VAR_USED, MINORLINE, NoFault, Minor::Fetch1::FetchRequest::packet, and Minor::Fetch1::FetchRequest::request.
Referenced by handleTLBResponse(), and recvTimingResp().
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Move a request between queues.
Definition at line 321 of file fetch1.cc.
References Minor::Queue< ElemType, ReportTraits, BubbleTraits >::empty(), Minor::Queue< ElemType, ReportTraits, BubbleTraits >::front(), Minor::Queue< ElemType, ReportTraits, BubbleTraits >::pop(), Minor::Queue< ElemType, ReportTraits, BubbleTraits >::push(), requests, and transfers.
Referenced by recvReqRetry(), and tryToSendToTransfers().
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Returns the total number of queue occupancy, in-ITLB and in-memory system fetches.
Definition at line 389 of file fetch1.cc.
References Minor::Queue< ElemType, ReportTraits, BubbleTraits >::occupiedSpace(), requests, and transfers.
Referenced by evaluate(), and isDrained().
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Pop a request from the given queue and correctly deallocate and discard it.
Definition at line 380 of file fetch1.cc.
References Minor::Queue< ElemType, ReportTraits, BubbleTraits >::empty(), Minor::Queue< ElemType, ReportTraits, BubbleTraits >::front(), and Minor::Queue< ElemType, ReportTraits, BubbleTraits >::pop().
Referenced by evaluate().
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Convert a response to a ForwardLineData.
Definition at line 538 of file fetch1.cc.
References Minor::ForwardLineData::adoptPacketData(), DPRINTF, Minor::Fetch1::FetchRequest::fault, fetchInfo, FetchWaitingForPC, Request::getVaddr(), Minor::Fetch1::FetchRequest::id, Minor::ForwardLineData::id, Minor::ForwardLineData::lineBaseAddr, NoFault, Minor::Fetch1::FetchRequest::packet, Minor::Fetch1::FetchRequest::pc, Minor::ForwardLineData::pc, Minor::Fetch1::FetchRequest::request, Minor::ForwardLineData::setFault(), Minor::Fetch1::Fetch1ThreadInfo::state, and Minor::InstId::threadId.
Referenced by evaluate().
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Definition at line 453 of file fetch1.cc.
References DPRINTF, Minor::Queue< ElemType, ReportTraits, BubbleTraits >::empty(), Minor::Queue< ElemType, ReportTraits, BubbleTraits >::front(), IcacheNeedsRetry, IcacheRunning, icacheState, moveFromRequestsToTransfers(), requests, and tryToSend().
Referenced by Minor::Fetch1::IcachePort::recvReqRetry().
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Memory interface.
Definition at line 416 of file fetch1.cc.
References Minor::Fetch1::FetchRequest::Complete, cpu, DPRINTF, DTRACE, Minor::Pipeline::Fetch1StageId, Minor::Fetch1::FetchRequest::id, Packet::isError(), minorTraceResponseLine(), Named::name(), numFetchesInMemorySystem, Minor::Fetch1::FetchRequest::packet, Packet::popSenderState(), safe_cast(), Minor::Fetch1::FetchRequest::state, and MinorCPU::wakeupOnEvent().
Referenced by Minor::Fetch1::IcachePort::recvTimingResp().
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Step requests along between requests and transfers queues.
Definition at line 358 of file fetch1.cc.
References DPRINTF, Minor::Queue< ElemType, ReportTraits, BubbleTraits >::empty(), Minor::Queue< ElemType, ReportTraits, BubbleTraits >::front(), IcacheNeedsRetry, IcacheRunning, icacheState, requests, and tryToSendToTransfers().
Referenced by evaluate().
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Try to send (or resend) a memory request's next/only packet to the memory system.
Returns true if the fetch was successfully sent to memory
Definition at line 330 of file fetch1.cc.
References DPRINTF, IcacheNeedsRetry, icachePort, icacheState, Minor::Fetch1::FetchRequest::id, numFetchesInMemorySystem, Minor::Fetch1::FetchRequest::packet, Minor::Fetch1::FetchRequest::RequestIssuing, MasterPort::sendTimingReq(), and Minor::Fetch1::FetchRequest::state.
Referenced by recvReqRetry(), and tryToSendToTransfers().
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Try and issue a fetch for a translated request at the head of the requests queue.
Also tries to move the request between queues
Definition at line 282 of file fetch1.cc.
References Minor::Fetch1::FetchRequest::Complete, cpu, DPRINTF, Minor::Queue< ElemType, ReportTraits, BubbleTraits >::empty(), Minor::Fetch1::FetchRequest::fault, Minor::Pipeline::Fetch1StageId, Minor::Queue< ElemType, ReportTraits, BubbleTraits >::front(), Minor::Fetch1::FetchRequest::InTranslation, Minor::Fetch1::FetchRequest::isDiscardable(), Minor::Fetch1::FetchRequest::makePacket(), moveFromRequestsToTransfers(), Packet::needsResponse(), NoFault, Minor::Fetch1::FetchRequest::packet, requests, Minor::Fetch1::FetchRequest::state, Minor::Fetch1::FetchRequest::Translated, tryToSend(), and MinorCPU::wakeupOnEvent().
Referenced by handleTLBResponse(), and stepQueues().
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Update streamSeqNum and predictionSeqNum from the given branch (and assume these have changed and discard (on delivery) all lines in flight)
Definition at line 520 of file fetch1.cc.
References DPRINTF, fetchInfo, Minor::BranchData::newPredictionSeqNum, Minor::BranchData::newStreamSeqNum, Minor::Fetch1::Fetch1ThreadInfo::predictionSeqNum, Minor::Fetch1::Fetch1ThreadInfo::streamSeqNum, and Minor::BranchData::threadId.
Referenced by changeStream().
void Minor::Fetch1::wakeupFetch | ( | ThreadID | tid | ) |
Initiate fetch1 fetching.
Definition at line 713 of file fetch1.cc.
References cpu, DPRINTF, Minor::Pipeline::Fetch1StageId, fetchInfo, FetchRunning, Minor::Fetch1::Fetch1ThreadInfo::pc, ThreadContext::pcState(), Minor::Fetch1::Fetch1ThreadInfo::state, Minor::Fetch1::Fetch1ThreadInfo::wakeupGuard, and MinorCPU::wakeupOnEvent().
Referenced by Minor::Pipeline::drainResume(), and Minor::Pipeline::wakeupFetch().
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Construction-assigned data members.
Pointer back to the containing CPU
Definition at line 190 of file fetch1.hh.
Referenced by evaluate(), Fetch1(), fetchLine(), getScheduledThread(), isDrained(), recvTimingResp(), tryToSendToTransfers(), and wakeupFetch().
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Definition at line 281 of file fetch1.hh.
Referenced by changeStream(), evaluate(), fetchLine(), getScheduledThread(), isDrained(), minorTrace(), processResponse(), updateExpectedSeqNums(), and wakeupFetch().
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Maximum number of fetches allowed in flight (in queues or memory)
Definition at line 218 of file fetch1.hh.
Referenced by evaluate(), and Fetch1().
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IcachePort to pass to the CPU.
Fetch1 is the only module that uses it.
Definition at line 204 of file fetch1.hh.
Referenced by getIcachePort(), and tryToSend().
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Retry state of icache_port.
Definition at line 303 of file fetch1.hh.
Referenced by minorTrace(), recvReqRetry(), stepQueues(), and tryToSend().
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Input port carrying branch requests from Execute.
Definition at line 193 of file fetch1.hh.
Referenced by evaluate().
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Sequence number for line fetch used for ordering lines to flush.
Definition at line 306 of file fetch1.hh.
Referenced by fetchLine().
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Line snap size in bytes.
All fetches clip to make their ends not extend beyond this limit. Setting this to the machine L1 cache line length will result in fetches never crossing line boundaries.
Definition at line 209 of file fetch1.hh.
Referenced by Fetch1(), and fetchLine().
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Maximum fetch width in bytes.
Setting this (and lineSnap) to the machine L1 cache line length will result in fetches of whole cache lines. Setting this to sizeof(MachInst) will result it fetches of single instructions (except near the end of lineSnap lines)
Definition at line 215 of file fetch1.hh.
Referenced by Fetch1(), and fetchLine().
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Interface to reserve space in the next stage.
Definition at line 200 of file fetch1.hh.
Referenced by evaluate().
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Number of requests inside the ITLB rather than in the queues.
All requests so located must have reserved space in the transfers queue
Definition at line 316 of file fetch1.hh.
Referenced by fetchLine(), handleTLBResponse(), and minorTrace().
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Count of the number fetches which have left the transfers queue and are in the 'wild' in the memory system.
Try not to rely on this value, it's better to code without knowledge of the number of outstanding accesses
Definition at line 312 of file fetch1.hh.
Referenced by minorTrace(), recvTimingResp(), and tryToSend().
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Output port carrying read lines to Fetch2.
Definition at line 195 of file fetch1.hh.
Referenced by evaluate(), isDrained(), and minorTrace().
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Input port carrying branch predictions from Fetch2.
Definition at line 197 of file fetch1.hh.
Referenced by evaluate().
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Queue of address translated requests from Fetch1.
Definition at line 297 of file fetch1.hh.
Referenced by fetchLine(), minorTrace(), moveFromRequestsToTransfers(), numInFlightFetches(), recvReqRetry(), stepQueues(), and tryToSendToTransfers().
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Definition at line 282 of file fetch1.hh.
Referenced by getScheduledThread().
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Queue of in-memory system requests and responses.
Definition at line 300 of file fetch1.hh.
Referenced by evaluate(), fetchLine(), minorTrace(), moveFromRequestsToTransfers(), and numInFlightFetches().