#include <base_dyn_inst.hh>

Inheritance diagram for BaseDynInst< Impl >:

Classes
union	Result

Public Types
enum	{ MaxInstSrcRegs = TheISA::MaxInstSrcRegs, MaxInstDestRegs = TheISA::MaxInstDestRegs }

typedef Impl::CPUType	ImplCPU

typedef ImplCPU::ImplState	ImplState

typedef TheISA::RegIndex	RegIndex

typedef Impl::DynInstPtr	DynInstPtr

typedef RefCountingPtr < BaseDynInst< Impl > >	BaseDynInstPtr

typedef std::list< DynInstPtr > ::iterator	ListIt

Public Types inherited from ExecContext
typedef TheISA::IntReg	IntReg

typedef TheISA::PCState	PCState

typedef TheISA::FloatReg	FloatReg

typedef TheISA::FloatRegBits	FloatRegBits

typedef TheISA::MiscReg	MiscReg

typedef TheISA::CCReg	CCReg

Public Member Functions
BaseCPU *	getCpuPtr ()

void	recordResult (bool f)
	Records changes to result? More...

bool	effAddrValid () const
	Is the effective virtual address valid. More...

bool	memOpDone () const
	Whether or not the memory operation is done. More...

void	memOpDone (bool f)

void	demapPage (Addr vaddr, uint64_t asn)
	Invalidate a page in the DTLB and ITLB. More...

void	demapInstPage (Addr vaddr, uint64_t asn)

void	demapDataPage (Addr vaddr, uint64_t asn)

Fault	initiateMemRead (Addr addr, unsigned size, Request::Flags flags)

Fault	writeMem (uint8_t data, unsigned size, Addr addr, Request::Flags flags, uint64_t res)

void	splitRequest (RequestPtr req, RequestPtr &sreqLow, RequestPtr &sreqHigh)
	Splits a request in two if it crosses a dcache block. More...

void	initiateTranslation (RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, uint64_t *res, BaseTLB::Mode mode)
	Initiate a DTB address translation. More...

void	finishTranslation (WholeTranslationState *state)
	Finish a DTB address translation. More...

bool	translationStarted () const
	True if the DTB address translation has started. More...

void	translationStarted (bool f)

bool	translationCompleted () const
	True if the DTB address translation has completed. More...

void	translationCompleted (bool f)

bool	possibleLoadViolation () const
	True if this address was found to match a previous load and they issued out of order. More...

void	possibleLoadViolation (bool f)

bool	hitExternalSnoop () const
	True if the address hit a external snoop while sitting in the LSQ. More...

void	hitExternalSnoop (bool f)

bool	isTranslationDelayed () const
	Returns true if the DTB address translation is being delayed due to a hw page table walk. More...

PhysRegIndex	renamedDestRegIdx (int idx) const
	Returns the physical register index of the i'th destination register. More...

PhysRegIndex	renamedSrcRegIdx (int idx) const
	Returns the physical register index of the i'th source register. More...

TheISA::RegIndex	flattenedDestRegIdx (int idx) const
	Returns the flattened register index of the i'th destination register. More...

PhysRegIndex	prevDestRegIdx (int idx) const
	Returns the physical register index of the previous physical register that remapped to the same logical register index. More...

void	renameDestReg (int idx, PhysRegIndex renamed_dest, PhysRegIndex previous_rename)
	Renames a destination register to a physical register. More...

void	renameSrcReg (int idx, PhysRegIndex renamed_src)
	Renames a source logical register to the physical register which has/will produce that logical register's result. More...

void	flattenDestReg (int idx, TheISA::RegIndex flattened_dest)
	Flattens a destination architectural register index into a logical index. More...

	BaseDynInst (const StaticInstPtr &staticInst, const StaticInstPtr &macroop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu)
	BaseDynInst constructor given a binary instruction. More...

	BaseDynInst (const StaticInstPtr &staticInst, const StaticInstPtr &macroop)
	BaseDynInst constructor given a StaticInst pointer. More...

	~BaseDynInst ()
	BaseDynInst destructor. More...

void	dump ()
	Dumps out contents of this BaseDynInst. More...

void	dump (std::string &outstring)
	Dumps out contents of this BaseDynInst into given string. More...

int	cpuId () const
	Read this CPU's ID. More...

uint32_t	socketId () const
	Read this CPU's Socket ID. More...

MasterID	masterId () const
	Read this CPU's data requestor ID. More...

ContextID	contextId () const
	Read this context's system-wide ID. More...

Fault	getFault () const
	Returns the fault type. More...

bool	doneTargCalc ()
	Checks whether or not this instruction has had its branch target calculated yet. More...

void	setPredTarg (const TheISA::PCState &_predPC)
	Set the predicted target of this current instruction. More...

const TheISA::PCState &	readPredTarg ()

Addr	predInstAddr ()
	Returns the predicted PC immediately after the branch. More...

Addr	predNextInstAddr ()
	Returns the predicted PC two instructions after the branch. More...

Addr	predMicroPC ()
	Returns the predicted micro PC after the branch. More...

bool	readPredTaken ()
	Returns whether the instruction was predicted taken or not. More...

void	setPredTaken (bool predicted_taken)

bool	mispredicted ()
	Returns whether the instruction mispredicted. More...

bool	isNop () const

bool	isMemRef () const

bool	isLoad () const

bool	isStore () const

bool	isStoreConditional () const

bool	isInstPrefetch () const

bool	isDataPrefetch () const

bool	isInteger () const

bool	isFloating () const

bool	isControl () const

bool	isCall () const

bool	isReturn () const

bool	isDirectCtrl () const

bool	isIndirectCtrl () const

bool	isCondCtrl () const

bool	isUncondCtrl () const

bool	isCondDelaySlot () const

bool	isThreadSync () const

bool	isSerializing () const

bool	isSerializeBefore () const

bool	isSerializeAfter () const

bool	isSquashAfter () const

bool	isMemBarrier () const

bool	isWriteBarrier () const

bool	isNonSpeculative () const

bool	isQuiesce () const

bool	isIprAccess () const

bool	isUnverifiable () const

bool	isSyscall () const

bool	isMacroop () const

bool	isMicroop () const

bool	isDelayedCommit () const

bool	isLastMicroop () const

bool	isFirstMicroop () const

bool	isMicroBranch () const

void	setSerializeBefore ()
	Temporarily sets this instruction as a serialize before instruction. More...

void	clearSerializeBefore ()
	Clears the serializeBefore part of this instruction. More...

bool	isTempSerializeBefore ()
	Checks if this serializeBefore is only temporarily set. More...

void	setSerializeAfter ()
	Temporarily sets this instruction as a serialize after instruction. More...

void	clearSerializeAfter ()
	Clears the serializeAfter part of this instruction. More...

bool	isTempSerializeAfter ()
	Checks if this serializeAfter is only temporarily set. More...

void	setSerializeHandled ()
	Sets the serialization part of this instruction as handled. More...

bool	isSerializeHandled ()
	Checks if the serialization part of this instruction has been handled. More...

OpClass	opClass () const
	Returns the opclass of this instruction. More...

TheISA::PCState	branchTarget () const
	Returns the branch target address. More...

int8_t	numSrcRegs () const
	Returns the number of source registers. More...

int8_t	numDestRegs () const
	Returns the number of destination registers. More...

int8_t	numFPDestRegs () const

int8_t	numIntDestRegs () const

int8_t	numCCDestRegs () const

RegIndex	destRegIdx (int i) const
	Returns the logical register index of the i'th destination register. More...

RegIndex	srcRegIdx (int i) const
	Returns the logical register index of the i'th source register. More...

template<class T >
void	popResult (T &t)
	Pops a result off the instResult queue. More...

template<class T >
void	readResult (T &t)
	Read the most recent result stored by this instruction. More...

template<class T >
void	setResult (T t)
	Pushes a result onto the instResult queue. More...

void	setIntRegOperand (const StaticInst *si, int idx, IntReg val)
	Records an integer register being set to a value. More...

void	setCCRegOperand (const StaticInst *si, int idx, CCReg val)
	Records a CC register being set to a value. More...

void	setFloatRegOperand (const StaticInst *si, int idx, FloatReg val)
	Records an fp register being set to a value. More...

void	setFloatRegOperandBits (const StaticInst *si, int idx, FloatRegBits val)
	Records an fp register being set to an integer value. More...

void	markSrcRegReady ()
	Records that one of the source registers is ready. More...

void	markSrcRegReady (RegIndex src_idx)
	Marks a specific register as ready. More...

bool	isReadySrcRegIdx (int idx) const
	Returns if a source register is ready. More...

void	setCompleted ()
	Sets this instruction as completed. More...

bool	isCompleted () const
	Returns whether or not this instruction is completed. More...

void	setResultReady ()
	Marks the result as ready. More...

bool	isResultReady () const
	Returns whether or not the result is ready. More...

void	setCanIssue ()
	Sets this instruction as ready to issue. More...

bool	readyToIssue () const
	Returns whether or not this instruction is ready to issue. More...

void	clearCanIssue ()
	Clears this instruction being able to issue. More...

void	setIssued ()
	Sets this instruction as issued from the IQ. More...

bool	isIssued () const
	Returns whether or not this instruction has issued. More...

void	clearIssued ()
	Clears this instruction as being issued. More...

void	setExecuted ()
	Sets this instruction as executed. More...

bool	isExecuted () const
	Returns whether or not this instruction has executed. More...

void	setCanCommit ()
	Sets this instruction as ready to commit. More...

void	clearCanCommit ()
	Clears this instruction as being ready to commit. More...

bool	readyToCommit () const
	Returns whether or not this instruction is ready to commit. More...

void	setAtCommit ()

bool	isAtCommit ()

void	setCommitted ()
	Sets this instruction as committed. More...

bool	isCommitted () const
	Returns whether or not this instruction is committed. More...

void	setSquashed ()
	Sets this instruction as squashed. More...

bool	isSquashed () const
	Returns whether or not this instruction is squashed. More...

void	setInIQ ()
	Sets this instruction as a entry the IQ. More...

void	clearInIQ ()
	Sets this instruction as a entry the IQ. More...

bool	isInIQ () const
	Returns whether or not this instruction has issued. More...

void	setSquashedInIQ ()
	Sets this instruction as squashed in the IQ. More...

bool	isSquashedInIQ () const
	Returns whether or not this instruction is squashed in the IQ. More...

void	setInLSQ ()
	Sets this instruction as a entry the LSQ. More...

void	removeInLSQ ()
	Sets this instruction as a entry the LSQ. More...

bool	isInLSQ () const
	Returns whether or not this instruction is in the LSQ. More...

void	setSquashedInLSQ ()
	Sets this instruction as squashed in the LSQ. More...

bool	isSquashedInLSQ () const
	Returns whether or not this instruction is squashed in the LSQ. More...

void	setInROB ()
	Sets this instruction as a entry the ROB. More...

void	clearInROB ()
	Sets this instruction as a entry the ROB. More...

bool	isInROB () const
	Returns whether or not this instruction is in the ROB. More...

void	setSquashedInROB ()
	Sets this instruction as squashed in the ROB. More...

bool	isSquashedInROB () const
	Returns whether or not this instruction is squashed in the ROB. More...

TheISA::PCState	pcState () const
	Read the PC state of this instruction. More...

void	pcState (const TheISA::PCState &val)
	Set the PC state of this instruction. More...

Addr	instAddr () const
	Read the PC of this instruction. More...

Addr	nextInstAddr () const
	Read the PC of the next instruction. More...

Addr	microPC () const
	Read the micro PC of this instruction. More...

bool	readPredicate ()

void	setPredicate (bool val)

void	setASID (short addr_space_id)
	Sets the ASID. More...

void	setTid (ThreadID tid)
	Sets the thread id. More...

void	setThreadState (ImplState *state)
	Sets the pointer to the thread state. More...

ThreadContext *	tcBase ()
	Returns the thread context. More...

void	setEA (Addr ea)
	Sets the effective address. More...

Addr	getEA () const
	Returns the effective address. More...

bool	doneEACalc ()
	Returns whether or not the eff. More...

bool	eaSrcsReady ()
	Returns whether or not the eff. More...

bool	strictlyOrdered () const
	Is this instruction's memory access strictly ordered? More...

bool	hasRequest ()
	Has this instruction generated a memory request. More...

ListIt &	getInstListIt ()
	Returns iterator to this instruction in the list of all insts. More...

void	setInstListIt (ListIt _instListIt)
	Sets iterator for this instruction in the list of all insts. More...

unsigned int	readStCondFailures () const
	Returns the number of consecutive store conditional failures. More...

void	setStCondFailures (unsigned int sc_failures)
	Sets the number of consecutive store conditional failures. More...

void	armMonitor (Addr address)

bool	mwait (PacketPtr pkt)

void	mwaitAtomic (ThreadContext *tc)

AddressMonitor *	getAddrMonitor ()

Public Member Functions inherited from ExecContext
virtual IntReg	readIntRegOperand (const StaticInst *si, int idx)=0
	Reads an integer register. More...

virtual FloatReg	readFloatRegOperand (const StaticInst *si, int idx)=0
	Reads a floating point register of single register width. More...

virtual FloatRegBits	readFloatRegOperandBits (const StaticInst *si, int idx)=0
	Reads a floating point register in its binary format, instead of by value. More...

virtual CCReg	readCCRegOperand (const StaticInst *si, int idx)=0

virtual MiscReg	readMiscRegOperand (const StaticInst *si, int idx)=0

virtual void	setMiscRegOperand (const StaticInst *si, int idx, const MiscReg &val)=0

virtual MiscReg	readMiscReg (int misc_reg)=0
	Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...

virtual void	setMiscReg (int misc_reg, const MiscReg &val)=0
	Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...

virtual Fault	readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags)
	Perform an atomic memory read operation. More...

virtual Fault	initiateMemRead (Addr addr, unsigned int size, Request::Flags flags)
	Initiate a timing memory read operation. More...

virtual Fault	writeMem (uint8_t data, unsigned int size, Addr addr, Request::Flags flags, uint64_t res)=0
	For atomic-mode contexts, perform an atomic memory write operation. More...

virtual void	syscall (int64_t callnum, Fault *fault)=0
	Executes a syscall specified by the callnum. More...

virtual Fault	hwrei ()=0
	Somewhat Alpha-specific function that handles returning from an error or interrupt. More...

virtual bool	simPalCheck (int palFunc)=0
	Check for special simulator handling of specific PAL calls. More...

virtual MiscReg	readRegOtherThread (int regIdx, ThreadID tid=InvalidThreadID)=0

virtual void	setRegOtherThread (int regIdx, MiscReg val, ThreadID tid=InvalidThreadID)=0

Public Member Functions inherited from RefCounted
	RefCounted ()
	We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More...

virtual	~RefCounted ()
	We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More...

void	incref ()
	Increment the reference count. More...

void	decref ()
	Decrement the reference count and destroy the object if all references are gone. More...

Public Attributes
InstSeqNum	seqNum
	The sequence number of the instruction. More...

const StaticInstPtr	staticInst
	The StaticInst used by this BaseDynInst. More...

ImplCPU *	cpu
	Pointer to the Impl's CPU object. More...

ImplState *	thread
	Pointer to the thread state. More...

Fault	fault
	The kind of fault this instruction has generated. More...

Trace::InstRecord *	traceData
	InstRecord that tracks this instructions. More...

ThreadID	threadNumber
	The thread this instruction is from. More...

ListIt	instListIt
	Iterator pointing to this BaseDynInst in the list of all insts. More...

TheISA::PCState	predPC
	Predicted PC state after this instruction. More...

const StaticInstPtr	macroop
	The Macroop if one exists. More...

uint8_t	readyRegs
	How many source registers are ready. More...

Addr	effAddr
	The effective virtual address (lds & stores only). More...

Addr	physEffAddrLow
	The effective physical address. More...

Addr	physEffAddrHigh
	The effective physical address of the second request for a split request. More...

unsigned	memReqFlags
	The memory request flags (from translation). More...

short	asid
	data address space ID, for loads & stores. More...

uint8_t	effSize
	The size of the request. More...

uint8_t *	memData
	Pointer to the data for the memory access. More...

int16_t	lqIdx
	Load queue index. More...

int16_t	sqIdx
	Store queue index. More...

RequestPtr	savedReq
	Saved memory requests (needed when the DTB address translation is delayed due to a hw page table walk). More...

RequestPtr	savedSreqLow

RequestPtr	savedSreqHigh

RequestPtr	reqToVerify

Protected Types
enum	Status { IqEntry, RobEntry, LsqEntry, Completed, ResultReady, CanIssue, Issued, Executed, CanCommit, AtCommit, Committed, Squashed, SquashedInIQ, SquashedInLSQ, SquashedInROB, RecoverInst, BlockingInst, ThreadsyncWait, SerializeBefore, SerializeAfter, SerializeHandled, NumStatus }

enum	Flags { TranslationStarted, TranslationCompleted, PossibleLoadViolation, HitExternalSnoop, EffAddrValid, RecordResult, Predicate, PredTaken, EACalcDone, IsStrictlyOrdered, ReqMade, MemOpDone, MaxFlags }

Protected Attributes
std::queue< Result >	instResult
	The result of the instruction; assumes an instruction can have many destination registers. More...

TheISA::PCState	pc
	PC state for this instruction. More...

std::bitset< MaxFlags >	instFlags

std::bitset< NumStatus >	status
	The status of this BaseDynInst. More...

std::bitset< MaxInstSrcRegs >	_readySrcRegIdx
	Whether or not the source register is ready. More...

std::array< TheISA::RegIndex, TheISA::MaxInstDestRegs >	_flatDestRegIdx
	Flattened register index of the destination registers of this instruction. More...

std::array< PhysRegIndex, TheISA::MaxInstDestRegs >	_destRegIdx
	Physical register index of the destination registers of this instruction. More...

std::array< PhysRegIndex, TheISA::MaxInstSrcRegs >	_srcRegIdx
	Physical register index of the source registers of this instruction. More...

std::array< PhysRegIndex, TheISA::MaxInstDestRegs >	_prevDestRegIdx
	Physical register index of the previous producers of the architected destinations. More...

Private Member Functions
void	initVars ()
	Function to initialize variables in the constructors. More...

Private Attributes
Addr	instEffAddr
	Instruction effective address. More...

Detailed Description

template<class Impl>
class BaseDynInst< Impl >

Definition at line 78 of file base_dyn_inst.hh.

Member Typedef Documentation

template<class Impl >

typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInst< Impl >::BaseDynInstPtr

Definition at line 90 of file base_dyn_inst.hh.

template<class Impl >

typedef Impl::DynInstPtr BaseDynInst< Impl >::DynInstPtr

Definition at line 89 of file base_dyn_inst.hh.

template<class Impl >

typedef Impl::CPUType BaseDynInst< Impl >::ImplCPU

Definition at line 82 of file base_dyn_inst.hh.

template<class Impl >

typedef ImplCPU::ImplState BaseDynInst< Impl >::ImplState

Definition at line 83 of file base_dyn_inst.hh.

template<class Impl >

typedef std::list<DynInstPtr>::iterator BaseDynInst< Impl >::ListIt

Definition at line 93 of file base_dyn_inst.hh.

template<class Impl >

typedef TheISA::RegIndex BaseDynInst< Impl >::RegIndex

Definition at line 86 of file base_dyn_inst.hh.

Member Enumeration Documentation

template<class Impl >

anonymous enum

Enumerator
MaxInstSrcRegs
MaxInstDestRegs	Max source regs.

Definition at line 95 of file base_dyn_inst.hh.

template<class Impl >

enum BaseDynInst::Flags

protected

Enumerator
TranslationStarted
TranslationCompleted
PossibleLoadViolation
HitExternalSnoop
EffAddrValid
RecordResult
Predicate
PredTaken
EACalcDone	Whether or not the effective address calculation is completed. Todo: : Consider if this is necessary or not.
IsStrictlyOrdered
ReqMade
MemOpDone
MaxFlags

Definition at line 136 of file base_dyn_inst.hh.

template<class Impl >

enum BaseDynInst::Status

protected

Enumerator
IqEntry
RobEntry	Instruction is in the IQ.
LsqEntry	Instruction is in the ROB.
Completed	Instruction is in the LSQ.
ResultReady	Instruction has completed.
CanIssue	Instruction has its result.
Issued	Instruction can issue and execute.
Executed	Instruction has issued.
CanCommit	Instruction has executed.
AtCommit	Instruction can commit.
Committed	Instruction has reached commit.
Squashed	Instruction has committed.
SquashedInIQ	Instruction is squashed.
SquashedInLSQ	Instruction is squashed in the IQ.
SquashedInROB	Instruction is squashed in the LSQ.
RecoverInst	Instruction is squashed in the ROB.
BlockingInst	Is a recover instruction.
ThreadsyncWait	Is a blocking instruction.
SerializeBefore	Is a thread synchronization instruction.
SerializeAfter	Needs to serialize on instructions ahead of it.
SerializeHandled	Needs to serialize instructions behind it.
NumStatus	Serialization has been handled.

Definition at line 110 of file base_dyn_inst.hh.

Constructor & Destructor Documentation

template<class Impl >

BaseDynInst< Impl >::BaseDynInst	(	const StaticInstPtr &	staticInst,
		const StaticInstPtr &	macroop,
		TheISA::PCState	pc,
		TheISA::PCState	predPC,
		InstSeqNum	seq_num,
		ImplCPU *	cpu
	)

BaseDynInst constructor given a binary instruction.

Parameters

staticInst	A StaticInstPtr to the underlying instruction.
pc	The PC state for the instruction.
predPC	The predicted next PC state for the instruction.
seq_num	The sequence number of the instruction.
cpu	Pointer to the instruction's CPU.

Definition at line 62 of file base_dyn_inst_impl.hh.

References BaseDynInst< Impl >::initVars(), BaseDynInst< Impl >::pc, BaseDynInst< Impl >::predPC, and BaseDynInst< Impl >::seqNum.

template<class Impl >

BaseDynInst< Impl >::BaseDynInst	(	const StaticInstPtr &	staticInst,
		const StaticInstPtr &	macroop
	)

BaseDynInst constructor given a StaticInst pointer.

Parameters

_staticInst The StaticInst for this BaseDynInst.

Definition at line 77 of file base_dyn_inst_impl.hh.

References BaseDynInst< Impl >::initVars(), and BaseDynInst< Impl >::seqNum.

template<class Impl >

BaseDynInst< Impl >::~BaseDynInst ( )

BaseDynInst destructor.

Definition at line 138 of file base_dyn_inst_impl.hh.

References DPRINTF, and NoFault.

Member Function Documentation

template<class Impl >

void BaseDynInst< Impl >::armMonitor ( Addr address )

inlinevirtual

Implements ExecContext.

Definition at line 867 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu, and BaseDynInst< Impl >::threadNumber.

template<class Impl >

TheISA::PCState BaseDynInst< Impl >::branchTarget ( ) const

inline

Returns the branch target address.

Definition at line 591 of file base_dyn_inst.hh.

References StaticInst::branchTarget(), BaseDynInst< Impl >::pc, and BaseDynInst< Impl >::staticInst.

template<class Impl >

void BaseDynInst< Impl >::clearCanCommit ( )

inline

Clears this instruction as being ready to commit.

Definition at line 716 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::CanCommit, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::clearCanIssue ( )

inline

Clears this instruction being able to issue.

Definition at line 695 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::CanIssue, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::clearInIQ ( )

inline

Sets this instruction as a entry the IQ.

Definition at line 743 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::IqEntry, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::clearInROB ( )

inline

Sets this instruction as a entry the ROB.

Definition at line 779 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::RobEntry, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::clearIssued ( )

inline

Clears this instruction as being issued.

Definition at line 704 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Issued, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::clearSerializeAfter ( )

inline

Clears the serializeAfter part of this instruction.

Definition at line 572 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeAfter, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::clearSerializeBefore ( )

inline

Clears the serializeBefore part of this instruction.

Definition at line 563 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeBefore, and BaseDynInst< Impl >::status.

template<class Impl >

ContextID BaseDynInst< Impl >::contextId ( ) const

inline

Read this context's system-wide ID.

Definition at line 469 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::thread.

template<class Impl >

int BaseDynInst< Impl >::cpuId ( ) const

inline

Read this CPU's ID.

Definition at line 460 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu.

template<class Impl >

void BaseDynInst< Impl >::demapDataPage	(	Addr	vaddr,
		uint64_t	asn
	)

inline

Definition at line 312 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu.

template<class Impl >

void BaseDynInst< Impl >::demapInstPage	(	Addr	vaddr,
		uint64_t	asn
	)

inline

Definition at line 308 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu.

template<class Impl >

void BaseDynInst< Impl >::demapPage	(	Addr	vaddr,
		uint64_t	asn
	)

inlinevirtual

Invalidate a page in the DTLB and ITLB.

Implements ExecContext.

Definition at line 304 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu.

template<class Impl >

RegIndex BaseDynInst< Impl >::destRegIdx ( int i ) const

inline

Returns the logical register index of the i'th destination register.

Definition at line 607 of file base_dyn_inst.hh.

References StaticInst::destRegIdx(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::doneEACalc ( )

inline

Returns whether or not the eff.

addr. calculation has been completed.

Definition at line 839 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::EACalcDone, and BaseDynInst< Impl >::instFlags.

template<class Impl >

bool BaseDynInst< Impl >::doneTargCalc ( )

inline

Checks whether or not this instruction has had its branch target calculated yet.

For now it is not utilized and is hacked to be always false.

Todo:: : Actually use this instruction.

Definition at line 479 of file base_dyn_inst.hh.

template<class Impl >

void BaseDynInst< Impl >::dump ( )

Dumps out contents of this BaseDynInst.

Definition at line 183 of file base_dyn_inst_impl.hh.

References cprintf(), and pc.

template<class Impl >

void BaseDynInst< Impl >::dump ( std::string & outstring )

Dumps out contents of this BaseDynInst into given string.

Definition at line 192 of file base_dyn_inst_impl.hh.

References pc, and ArmISA::s.

template<class Impl >

bool BaseDynInst< Impl >::eaSrcsReady ( )

Returns whether or not the eff.

addr. source registers are ready.

Definition at line 223 of file base_dyn_inst_impl.hh.

References ArmISA::i.

template<class Impl >

bool BaseDynInst< Impl >::effAddrValid ( ) const

inline

Is the effective virtual address valid.

Definition at line 291 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::EffAddrValid, and BaseDynInst< Impl >::instFlags.

template<class Impl >

void BaseDynInst< Impl >::finishTranslation ( WholeTranslationState * state )

inline

Finish a DTB address translation.

Definition at line 1052 of file base_dyn_inst.hh.

References WholeTranslationState::deleteReqs(), WholeTranslationState::getFault(), WholeTranslationState::getFlags(), WholeTranslationState::getPaddr(), Request::getPaddr(), Request::isCondSwap(), WholeTranslationState::isSplit, WholeTranslationState::isStrictlyOrdered(), WholeTranslationState::mainReq, NoFault, WholeTranslationState::res, Request::setExtraData(), WholeTranslationState::sreqHigh, and WholeTranslationState::sreqLow.

template<class Impl >

void BaseDynInst< Impl >::flattenDestReg	(	int	idx,
		TheISA::RegIndex	flattened_dest
	)

inline

Flattens a destination architectural register index into a logical index.

Definition at line 425 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::_flatDestRegIdx.

template<class Impl >

TheISA::RegIndex BaseDynInst< Impl >::flattenedDestRegIdx ( int idx ) const

inline

Returns the flattened register index of the i'th destination register.

Definition at line 389 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::_flatDestRegIdx.

template<class Impl >

AddressMonitor* BaseDynInst< Impl >::getAddrMonitor ( )

inlinevirtual

Implements ExecContext.

Definition at line 871 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu, and BaseDynInst< Impl >::threadNumber.

template<class Impl >

BaseCPU* BaseDynInst< Impl >::getCpuPtr ( )

inline

Definition at line 165 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu.

template<class Impl >

Addr BaseDynInst< Impl >::getEA ( ) const

inlinevirtual

Returns the effective address.

Implements ExecContext.

Definition at line 836 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instEffAddr.

template<class Impl >

Fault BaseDynInst< Impl >::getFault ( ) const

inline

Returns the fault type.

Definition at line 472 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::fault.

template<class Impl >

ListIt& BaseDynInst< Impl >::getInstListIt ( )

inline

Returns iterator to this instruction in the list of all insts.

Definition at line 851 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instListIt.

template<class Impl >

bool BaseDynInst< Impl >::hasRequest ( )

inline

Has this instruction generated a memory request.

Definition at line 848 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::ReqMade.

template<class Impl >

bool BaseDynInst< Impl >::hitExternalSnoop ( ) const

inline

True if the address hit a external snoop while sitting in the LSQ.

If this is true and a older instruction sees it, this instruction must reexecute

Definition at line 354 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::HitExternalSnoop, and BaseDynInst< Impl >::instFlags.

template<class Impl >

void BaseDynInst< Impl >::hitExternalSnoop ( bool f )

inline

Definition at line 355 of file base_dyn_inst.hh.

References ArmISA::f, BaseDynInst< Impl >::HitExternalSnoop, and BaseDynInst< Impl >::instFlags.

template<class Impl >

Fault BaseDynInst< Impl >::initiateMemRead	(	Addr	addr,
		unsigned	size,
		Request::Flags	flags
	)

Definition at line 877 of file base_dyn_inst.hh.

References ArmISA::asid, Request::getVaddr(), AlphaISA::HasUnalignedMemAcc, NoFault, pc, BaseTLB::Read, X86ISA::size(), and Request::taskId().

template<class Impl >

void BaseDynInst< Impl >::initiateTranslation	(	RequestPtr	req,
		RequestPtr	sreqLow,
		RequestPtr	sreqHigh,
		uint64_t *	res,
		BaseTLB::Mode	mode
	)

inline

Initiate a DTB address translation.

Definition at line 994 of file base_dyn_inst.hh.

References AlphaISA::HasUnalignedMemAcc, WholeTranslationState::mainReq, ArmISA::mode, NoFault, WholeTranslationState::sreqHigh, and WholeTranslationState::sreqLow.

template<class Impl >

void BaseDynInst< Impl >::initVars ( )

private

Function to initialize variables in the constructors.

Definition at line 87 of file base_dyn_inst_impl.hh.

References ArmISA::asid, DPRINTF, NoFault, and ArmISA::status.

Referenced by BaseDynInst< Impl >::BaseDynInst().

template<class Impl >

Addr BaseDynInst< Impl >::instAddr ( ) const

inline

Read the PC of this instruction.

Definition at line 797 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::pc.

template<class Impl >

bool BaseDynInst< Impl >::isAtCommit ( )

inline

Definition at line 723 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::AtCommit, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isCall ( ) const

inline

Definition at line 531 of file base_dyn_inst.hh.

References StaticInst::isCall(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isCommitted ( ) const

inline

Returns whether or not this instruction is committed.

Definition at line 729 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Committed, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isCompleted ( ) const

inline

Returns whether or not this instruction is completed.

Definition at line 680 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Completed, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isCondCtrl ( ) const

inline

Definition at line 535 of file base_dyn_inst.hh.

References StaticInst::isCondCtrl(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isCondDelaySlot ( ) const

inline

Definition at line 537 of file base_dyn_inst.hh.

References StaticInst::isCondDelaySlot(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isControl ( ) const

inline

Definition at line 530 of file base_dyn_inst.hh.

References StaticInst::isControl(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isDataPrefetch ( ) const

inline

Definition at line 527 of file base_dyn_inst.hh.

References StaticInst::isDataPrefetch(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isDelayedCommit ( ) const

inline

Definition at line 554 of file base_dyn_inst.hh.

References StaticInst::isDelayedCommit(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isDirectCtrl ( ) const

inline

Definition at line 533 of file base_dyn_inst.hh.

References StaticInst::isDirectCtrl(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isExecuted ( ) const

inline

Returns whether or not this instruction has executed.

Definition at line 710 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Executed, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isFirstMicroop ( ) const

inline

Definition at line 556 of file base_dyn_inst.hh.

References StaticInst::isFirstMicroop(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isFloating ( ) const

inline

Definition at line 529 of file base_dyn_inst.hh.

References StaticInst::isFloating(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isIndirectCtrl ( ) const

inline

Definition at line 534 of file base_dyn_inst.hh.

References StaticInst::isIndirectCtrl(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isInIQ ( ) const

inline

Returns whether or not this instruction has issued.

Definition at line 746 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::IqEntry, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isInLSQ ( ) const

inline

Returns whether or not this instruction is in the LSQ.

Definition at line 764 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::LsqEntry, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isInROB ( ) const

inline

Returns whether or not this instruction is in the ROB.

Definition at line 782 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::RobEntry, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isInstPrefetch ( ) const

inline

Definition at line 526 of file base_dyn_inst.hh.

References StaticInst::isInstPrefetch(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isInteger ( ) const

inline

Definition at line 528 of file base_dyn_inst.hh.

References StaticInst::isInteger(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isIprAccess ( ) const

inline

Definition at line 549 of file base_dyn_inst.hh.

References StaticInst::isIprAccess(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isIssued ( ) const

inline

Returns whether or not this instruction has issued.

Definition at line 701 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Issued, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isLastMicroop ( ) const

inline

Definition at line 555 of file base_dyn_inst.hh.

References StaticInst::isLastMicroop(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isLoad ( ) const

inline

Definition at line 522 of file base_dyn_inst.hh.

References StaticInst::isLoad(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isMacroop ( ) const

inline

Definition at line 552 of file base_dyn_inst.hh.

References StaticInst::isMacroop(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isMemBarrier ( ) const

inline

Definition at line 545 of file base_dyn_inst.hh.

References StaticInst::isMemBarrier(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isMemRef ( ) const

inline

Definition at line 521 of file base_dyn_inst.hh.

References StaticInst::isMemRef(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isMicroBranch ( ) const

inline

Definition at line 557 of file base_dyn_inst.hh.

References StaticInst::isMicroBranch(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isMicroop ( ) const

inline

Definition at line 553 of file base_dyn_inst.hh.

References StaticInst::isMicroop(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isNonSpeculative ( ) const

inline

Definition at line 547 of file base_dyn_inst.hh.

References StaticInst::isNonSpeculative(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isNop ( ) const

inline

Definition at line 520 of file base_dyn_inst.hh.

References StaticInst::isNop(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isQuiesce ( ) const

inline

Definition at line 548 of file base_dyn_inst.hh.

References StaticInst::isQuiesce(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isReadySrcRegIdx ( int idx ) const

inline

Returns if a source register is ready.

Definition at line 671 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::_readySrcRegIdx.

template<class Impl >

bool BaseDynInst< Impl >::isResultReady ( ) const

inline

Returns whether or not the result is ready.

Definition at line 686 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::ResultReady, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isReturn ( ) const

inline

Definition at line 532 of file base_dyn_inst.hh.

References StaticInst::isReturn(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isSerializeAfter ( ) const

inline

Definition at line 542 of file base_dyn_inst.hh.

References StaticInst::isSerializeAfter(), BaseDynInst< Impl >::SerializeAfter, BaseDynInst< Impl >::staticInst, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isSerializeBefore ( ) const

inline

Definition at line 540 of file base_dyn_inst.hh.

References StaticInst::isSerializeBefore(), BaseDynInst< Impl >::SerializeBefore, BaseDynInst< Impl >::staticInst, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isSerializeHandled ( )

inline

Checks if the serialization part of this instruction has been handled.

This does not apply to the temporary serializing state; it only applies to this instruction's own permanent serializing state.

Definition at line 585 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeHandled, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isSerializing ( ) const

inline

Definition at line 539 of file base_dyn_inst.hh.

References StaticInst::isSerializing(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isSquashAfter ( ) const

inline

Definition at line 544 of file base_dyn_inst.hh.

References StaticInst::isSquashAfter(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isSquashed ( ) const

inline

Returns whether or not this instruction is squashed.

Definition at line 735 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Squashed, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isSquashedInIQ ( ) const

inline

Returns whether or not this instruction is squashed in the IQ.

Definition at line 752 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SquashedInIQ, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isSquashedInLSQ ( ) const

inline

Returns whether or not this instruction is squashed in the LSQ.

Definition at line 770 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SquashedInLSQ, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isSquashedInROB ( ) const

inline

Returns whether or not this instruction is squashed in the ROB.

Definition at line 788 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SquashedInROB, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isStore ( ) const

inline

Definition at line 523 of file base_dyn_inst.hh.

References StaticInst::isStore(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isStoreConditional ( ) const

inline

Definition at line 524 of file base_dyn_inst.hh.

References StaticInst::isStoreConditional(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isSyscall ( ) const

inline

Definition at line 551 of file base_dyn_inst.hh.

References StaticInst::isSyscall(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isTempSerializeAfter ( )

inline

Checks if this serializeAfter is only temporarily set.

Definition at line 575 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeAfter, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isTempSerializeBefore ( )

inline

Checks if this serializeBefore is only temporarily set.

Definition at line 566 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeBefore, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::isThreadSync ( ) const

inline

Definition at line 538 of file base_dyn_inst.hh.

References StaticInst::isThreadSync(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isTranslationDelayed ( ) const

inline

Returns true if the DTB address translation is being delayed due to a hw page table walk.

Definition at line 361 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::translationCompleted(), and BaseDynInst< Impl >::translationStarted().

template<class Impl >

bool BaseDynInst< Impl >::isUncondCtrl ( ) const

inline

Definition at line 536 of file base_dyn_inst.hh.

References StaticInst::isUncondCtrl(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isUnverifiable ( ) const

inline

Definition at line 550 of file base_dyn_inst.hh.

References StaticInst::isUnverifiable(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::isWriteBarrier ( ) const

inline

Definition at line 546 of file base_dyn_inst.hh.

References StaticInst::isWriteBarrier(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

void BaseDynInst< Impl >::markSrcRegReady ( )

Records that one of the source registers is ready.

Definition at line 203 of file base_dyn_inst_impl.hh.

References DPRINTF.

template<class Impl >

void BaseDynInst< Impl >::markSrcRegReady ( RegIndex src_idx )

Marks a specific register as ready.

Definition at line 214 of file base_dyn_inst_impl.hh.

template<class Impl >

MasterID BaseDynInst< Impl >::masterId ( ) const

inline

Read this CPU's data requestor ID.

Definition at line 466 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu.

template<class Impl >

bool BaseDynInst< Impl >::memOpDone ( ) const

inline

Whether or not the memory operation is done.

Definition at line 294 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::MemOpDone.

template<class Impl >

void BaseDynInst< Impl >::memOpDone ( bool f )

inline

Definition at line 295 of file base_dyn_inst.hh.

References ArmISA::f, BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::MemOpDone.

template<class Impl >

Addr BaseDynInst< Impl >::microPC ( ) const

inline

Read the micro PC of this instruction.

Definition at line 803 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::pc.

template<class Impl >

bool BaseDynInst< Impl >::mispredicted ( )

inline

Returns whether the instruction mispredicted.

Definition at line 510 of file base_dyn_inst.hh.

References AlphaISA::advancePC(), BaseDynInst< Impl >::pc, BaseDynInst< Impl >::predPC, and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::mwait ( PacketPtr pkt )

inlinevirtual

Implements ExecContext.

Definition at line 868 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu, and BaseDynInst< Impl >::threadNumber.

template<class Impl >

void BaseDynInst< Impl >::mwaitAtomic ( ThreadContext * tc )

inlinevirtual

Implements ExecContext.

Definition at line 869 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu, and BaseDynInst< Impl >::threadNumber.

template<class Impl >

Addr BaseDynInst< Impl >::nextInstAddr ( ) const

inline

Read the PC of the next instruction.

Definition at line 800 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::pc.

template<class Impl >

int8_t BaseDynInst< Impl >::numCCDestRegs ( ) const

inline

Definition at line 604 of file base_dyn_inst.hh.

References StaticInst::numCCDestRegs(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

int8_t BaseDynInst< Impl >::numDestRegs ( ) const

inline

Returns the number of destination registers.

Definition at line 598 of file base_dyn_inst.hh.

References StaticInst::numDestRegs(), and BaseDynInst< Impl >::staticInst.

Referenced by BaseO3DynInst< Impl >::forwardOldRegs().

template<class Impl >

int8_t BaseDynInst< Impl >::numFPDestRegs ( ) const

inline

Definition at line 602 of file base_dyn_inst.hh.

References StaticInst::numFPDestRegs(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

int8_t BaseDynInst< Impl >::numIntDestRegs ( ) const

inline

Definition at line 603 of file base_dyn_inst.hh.

References StaticInst::numIntDestRegs(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

int8_t BaseDynInst< Impl >::numSrcRegs ( ) const

inline

Returns the number of source registers.

Definition at line 595 of file base_dyn_inst.hh.

References StaticInst::numSrcRegs(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

OpClass BaseDynInst< Impl >::opClass ( ) const

inline

Returns the opclass of this instruction.

Definition at line 588 of file base_dyn_inst.hh.

References StaticInst::opClass(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

TheISA::PCState BaseDynInst< Impl >::pcState ( ) const

inlinevirtual

Read the PC state of this instruction.

Implements ExecContext.

Definition at line 791 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::pc.

template<class Impl >

void BaseDynInst< Impl >::pcState ( const TheISA::PCState & val )

inlinevirtual

Set the PC state of this instruction.

Implements ExecContext.

Definition at line 794 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::pc, and X86ISA::val.

template<class Impl >

template<class T >

void BaseDynInst< Impl >::popResult ( T & t )

inline

Pops a result off the instResult queue.

Definition at line 614 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instResult.

template<class Impl >

bool BaseDynInst< Impl >::possibleLoadViolation ( ) const

inline

True if this address was found to match a previous load and they issued out of order.

If that happend, then it's only a problem if an incoming snoop invalidate modifies the line, in which case we need to squash. If nothing modified the line the order doesn't matter.

Definition at line 347 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::PossibleLoadViolation.

template<class Impl >

void BaseDynInst< Impl >::possibleLoadViolation ( bool f )

inline

Definition at line 348 of file base_dyn_inst.hh.

References ArmISA::f, BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::PossibleLoadViolation.

template<class Impl >

Addr BaseDynInst< Impl >::predInstAddr ( )

inline

Returns the predicted PC immediately after the branch.

Definition at line 490 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::predPC.

template<class Impl >

Addr BaseDynInst< Impl >::predMicroPC ( )

inline

Returns the predicted micro PC after the branch.

Definition at line 496 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::predPC.

template<class Impl >

Addr BaseDynInst< Impl >::predNextInstAddr ( )

inline

Returns the predicted PC two instructions after the branch.

Definition at line 493 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::predPC.

template<class Impl >

PhysRegIndex BaseDynInst< Impl >::prevDestRegIdx ( int idx ) const

inline

Returns the physical register index of the previous physical register that remapped to the same logical register index.

Definition at line 397 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::_prevDestRegIdx.

Referenced by BaseO3DynInst< Impl >::forwardOldRegs().

template<class Impl >

bool BaseDynInst< Impl >::readPredicate ( )

inlinevirtual

Implements ExecContext.

Definition at line 805 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::Predicate.

template<class Impl >

bool BaseDynInst< Impl >::readPredTaken ( )

inline

Returns whether the instruction was predicted taken or not.

Definition at line 499 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::PredTaken.

template<class Impl >

const TheISA::PCState& BaseDynInst< Impl >::readPredTarg ( )

inline

Definition at line 487 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::predPC.

template<class Impl >

template<class T >

void BaseDynInst< Impl >::readResult ( T & t )

inline

Read the most recent result stored by this instruction.

Definition at line 624 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instResult.

template<class Impl >

unsigned int BaseDynInst< Impl >::readStCondFailures ( ) const

inlinevirtual

Returns the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 858 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::thread.

template<class Impl >

bool BaseDynInst< Impl >::readyToCommit ( ) const

inline

Returns whether or not this instruction is ready to commit.

Definition at line 719 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::CanCommit, and BaseDynInst< Impl >::status.

template<class Impl >

bool BaseDynInst< Impl >::readyToIssue ( ) const

inline

Returns whether or not this instruction is ready to issue.

Definition at line 692 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::CanIssue, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::recordResult ( bool f )

inline

Records changes to result?

Definition at line 288 of file base_dyn_inst.hh.

References ArmISA::f, BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::RecordResult.

template<class Impl >

void BaseDynInst< Impl >::removeInLSQ ( )

inline

Sets this instruction as a entry the LSQ.

Definition at line 761 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::LsqEntry, and BaseDynInst< Impl >::status.

template<class Impl >

PhysRegIndex BaseDynInst< Impl >::renamedDestRegIdx ( int idx ) const

inline

Returns the physical register index of the i'th destination register.

Definition at line 374 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::_destRegIdx.

template<class Impl >

void BaseDynInst< Impl >::renameDestReg	(	int	idx,
		PhysRegIndex	renamed_dest,
		PhysRegIndex	previous_rename
	)

inline

Renames a destination register to a physical register.

Also records the previous physical register that the logical register mapped to.

Definition at line 405 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::_destRegIdx, and BaseDynInst< Impl >::_prevDestRegIdx.

template<class Impl >

PhysRegIndex BaseDynInst< Impl >::renamedSrcRegIdx ( int idx ) const

inline

Returns the physical register index of the i'th source register.

Definition at line 380 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::_srcRegIdx, and ArmISA::MaxInstSrcRegs.

template<class Impl >

void BaseDynInst< Impl >::renameSrcReg	(	int	idx,
		PhysRegIndex	renamed_src
	)

inline

Renames a source logical register to the physical register which has/will produce that logical register's result.

Todo:: : add in whether or not the source register is ready.

Definition at line 417 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::_srcRegIdx.

template<class Impl >

void BaseDynInst< Impl >::setASID ( short addr_space_id )

inline

Sets the ASID.

Definition at line 820 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::asid.

template<class Impl >

void BaseDynInst< Impl >::setAtCommit ( )

inline

Definition at line 721 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::AtCommit, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setCanCommit ( )

inline

Sets this instruction as ready to commit.

Definition at line 713 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::CanCommit, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setCanIssue ( )

inline

Sets this instruction as ready to issue.

Definition at line 689 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::CanIssue, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setCCRegOperand	(	const StaticInst *	si,
		int	idx,
		CCReg	val
	)

inlinevirtual

Records a CC register being set to a value.

Implements ExecContext.

Reimplemented in BaseO3DynInst< Impl >.

Definition at line 647 of file base_dyn_inst.hh.

References X86ISA::val.

Referenced by BaseO3DynInst< Impl >::setCCRegOperand().

template<class Impl >

void BaseDynInst< Impl >::setCommitted ( )

inline

Sets this instruction as committed.

Definition at line 726 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Committed, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setCompleted ( )

inline

Sets this instruction as completed.

Definition at line 677 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Completed, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setEA ( Addr ea )

inlinevirtual

Sets the effective address.

Implements ExecContext.

Definition at line 833 of file base_dyn_inst.hh.

References ArmISA::ea, BaseDynInst< Impl >::EACalcDone, BaseDynInst< Impl >::instEffAddr, and BaseDynInst< Impl >::instFlags.

template<class Impl >

void BaseDynInst< Impl >::setExecuted ( )

inline

Sets this instruction as executed.

Definition at line 707 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Executed, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setFloatRegOperand	(	const StaticInst *	si,
		int	idx,
		FloatReg	val
	)

inlinevirtual

Records an fp register being set to a value.

Implements ExecContext.

Reimplemented in BaseO3DynInst< Impl >.

Definition at line 653 of file base_dyn_inst.hh.

References X86ISA::val.

Referenced by BaseO3DynInst< Impl >::setFloatRegOperand().

template<class Impl >

void BaseDynInst< Impl >::setFloatRegOperandBits	(	const StaticInst *	si,
		int	idx,
		FloatRegBits	val
	)

inlinevirtual

Records an fp register being set to an integer value.

Implements ExecContext.

Reimplemented in BaseO3DynInst< Impl >.

Definition at line 659 of file base_dyn_inst.hh.

References X86ISA::val.

Referenced by BaseO3DynInst< Impl >::setFloatRegOperandBits().

template<class Impl >

void BaseDynInst< Impl >::setInIQ ( )

inline

Sets this instruction as a entry the IQ.

Definition at line 740 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::IqEntry, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setInLSQ ( )

inline

Sets this instruction as a entry the LSQ.

Definition at line 758 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::LsqEntry, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setInROB ( )

inline

Sets this instruction as a entry the ROB.

Definition at line 776 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::RobEntry, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setInstListIt ( ListIt _instListIt )

inline

Sets iterator for this instruction in the list of all insts.

Definition at line 854 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instListIt.

template<class Impl >

void BaseDynInst< Impl >::setIntRegOperand	(	const StaticInst *	si,
		int	idx,
		IntReg	val
	)

inlinevirtual

Records an integer register being set to a value.

Implements ExecContext.

Reimplemented in BaseO3DynInst< Impl >.

Definition at line 641 of file base_dyn_inst.hh.

References X86ISA::val.

Referenced by BaseO3DynInst< Impl >::setIntRegOperand().

template<class Impl >

void BaseDynInst< Impl >::setIssued ( )

inline

Sets this instruction as issued from the IQ.

Definition at line 698 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Issued, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setPredicate ( bool val )

inlinevirtual

Implements ExecContext.

Definition at line 810 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, BaseDynInst< Impl >::Predicate, Trace::InstRecord::setPredicate(), BaseDynInst< Impl >::traceData, and X86ISA::val.

template<class Impl >

void BaseDynInst< Impl >::setPredTaken ( bool predicted_taken )

inline

Definition at line 504 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::PredTaken.

template<class Impl >

void BaseDynInst< Impl >::setPredTarg ( const TheISA::PCState & _predPC )

inline

Set the predicted target of this current instruction.

Definition at line 482 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::predPC.

template<class Impl >

template<class T >

void BaseDynInst< Impl >::setResult ( T t )

inline

Pushes a result onto the instResult queue.

Definition at line 631 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, BaseDynInst< Impl >::instResult, BaseDynInst< Impl >::RecordResult, and BaseDynInst< Impl >::Result::set().

template<class Impl >

void BaseDynInst< Impl >::setResultReady ( )

inline

Marks the result as ready.

Definition at line 683 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::ResultReady, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setSerializeAfter ( )

inline

Temporarily sets this instruction as a serialize after instruction.

Definition at line 569 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeAfter, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setSerializeBefore ( )

inline

Temporarily sets this instruction as a serialize before instruction.

Definition at line 560 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeBefore, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setSerializeHandled ( )

inline

Sets the serialization part of this instruction as handled.

Definition at line 578 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SerializeHandled, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setSquashed ( )

inline

Sets this instruction as squashed.

Definition at line 732 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Squashed, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setSquashedInIQ ( )

inline

Sets this instruction as squashed in the IQ.

Definition at line 749 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::Squashed, BaseDynInst< Impl >::SquashedInIQ, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setSquashedInLSQ ( )

inline

Sets this instruction as squashed in the LSQ.

Definition at line 767 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SquashedInLSQ, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setSquashedInROB ( )

inline

Sets this instruction as squashed in the ROB.

Definition at line 785 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::SquashedInROB, and BaseDynInst< Impl >::status.

template<class Impl >

void BaseDynInst< Impl >::setStCondFailures ( unsigned int sc_failures )

inlinevirtual

Sets the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 862 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::thread.

template<class Impl >

void BaseDynInst< Impl >::setThreadState ( ImplState * state )

inline

Sets the pointer to the thread state.

Definition at line 826 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::thread.

template<class Impl >

void BaseDynInst< Impl >::setTid ( ThreadID tid )

inline

Sets the thread id.

Definition at line 823 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::threadNumber.

template<class Impl >

uint32_t BaseDynInst< Impl >::socketId ( ) const

inline

Read this CPU's Socket ID.

Definition at line 463 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::cpu.

template<class Impl >

void BaseDynInst< Impl >::splitRequest	(	RequestPtr	req,
		RequestPtr &	sreqLow,
		RequestPtr &	sreqHigh
	)

inline

Splits a request in two if it crosses a dcache block.

Definition at line 977 of file base_dyn_inst.hh.

References addr, Request::getSize(), Request::getVaddr(), roundDown(), and Request::splitOnVaddr().

template<class Impl >

RegIndex BaseDynInst< Impl >::srcRegIdx ( int i ) const

inline

Returns the logical register index of the i'th source register.

Definition at line 610 of file base_dyn_inst.hh.

References StaticInst::srcRegIdx(), and BaseDynInst< Impl >::staticInst.

template<class Impl >

bool BaseDynInst< Impl >::strictlyOrdered ( ) const

inline

Is this instruction's memory access strictly ordered?

Definition at line 845 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::IsStrictlyOrdered.

template<class Impl >

ThreadContext* BaseDynInst< Impl >::tcBase ( )

inlinevirtual

Returns the thread context.

Implements ExecContext.

Definition at line 829 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::thread.

template<class Impl >

bool BaseDynInst< Impl >::translationCompleted ( ) const

inline

True if the DTB address translation has completed.

Definition at line 339 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::TranslationCompleted.

Referenced by BaseDynInst< Impl >::isTranslationDelayed().

template<class Impl >

void BaseDynInst< Impl >::translationCompleted ( bool f )

inline

Definition at line 340 of file base_dyn_inst.hh.

References ArmISA::f, BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::TranslationCompleted.

template<class Impl >

bool BaseDynInst< Impl >::translationStarted ( ) const

inline

True if the DTB address translation has started.

Definition at line 335 of file base_dyn_inst.hh.

References BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::TranslationStarted.

Referenced by BaseDynInst< Impl >::isTranslationDelayed().

template<class Impl >

void BaseDynInst< Impl >::translationStarted ( bool f )

inline

Definition at line 336 of file base_dyn_inst.hh.

References ArmISA::f, BaseDynInst< Impl >::instFlags, and BaseDynInst< Impl >::TranslationStarted.

template<class Impl >

Fault BaseDynInst< Impl >::writeMem	(	uint8_t *	data,
		unsigned	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res
	)

Definition at line 930 of file base_dyn_inst.hh.

References ArmISA::asid, Request::getVaddr(), AlphaISA::HasUnalignedMemAcc, NoFault, pc, X86ISA::size(), Request::taskId(), and BaseTLB::Write.

Member Data Documentation

template<class Impl >

std::array<PhysRegIndex, TheISA::MaxInstDestRegs> BaseDynInst< Impl >::_destRegIdx

protected

Physical register index of the destination registers of this instruction.

Definition at line 273 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::renamedDestRegIdx(), BaseDynInst< Impl >::renameDestReg(), BaseO3DynInst< Impl >::setCCRegOperand(), BaseO3DynInst< Impl >::setFloatRegOperand(), BaseO3DynInst< Impl >::setFloatRegOperandBits(), and BaseO3DynInst< Impl >::setIntRegOperand().

template<class Impl >

std::array<TheISA::RegIndex, TheISA::MaxInstDestRegs> BaseDynInst< Impl >::_flatDestRegIdx

protected

Flattened register index of the destination registers of this instruction.

Definition at line 268 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::flattenDestReg(), and BaseDynInst< Impl >::flattenedDestRegIdx().

template<class Impl >

std::array<PhysRegIndex, TheISA::MaxInstDestRegs> BaseDynInst< Impl >::_prevDestRegIdx

protected

Physical register index of the previous producers of the architected destinations.

Definition at line 283 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::prevDestRegIdx(), and BaseDynInst< Impl >::renameDestReg().

template<class Impl >

std::bitset<MaxInstSrcRegs> BaseDynInst< Impl >::_readySrcRegIdx

protected

Whether or not the source register is ready.

Todo:: : Not sure this should be here vs the derived class.

Definition at line 194 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::isReadySrcRegIdx().

template<class Impl >

std::array<PhysRegIndex, TheISA::MaxInstSrcRegs> BaseDynInst< Impl >::_srcRegIdx

protected

Physical register index of the source registers of this instruction.

Definition at line 278 of file base_dyn_inst.hh.

Referenced by BaseO3DynInst< Impl >::readCCRegOperand(), BaseO3DynInst< Impl >::readFloatRegOperand(), BaseO3DynInst< Impl >::readFloatRegOperandBits(), BaseO3DynInst< Impl >::readIntRegOperand(), BaseDynInst< Impl >::renamedSrcRegIdx(), and BaseDynInst< Impl >::renameSrcReg().

template<class Impl >

short BaseDynInst< Impl >::asid

data address space ID, for loads & stores.

Definition at line 230 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::setASID().

template<class Impl >

ImplCPU* BaseDynInst< Impl >::cpu

Pointer to the Impl's CPU object.

Definition at line 163 of file base_dyn_inst.hh.

template<class Impl >

Addr BaseDynInst< Impl >::effAddr

The effective virtual address (lds & stores only).

Definition at line 216 of file base_dyn_inst.hh.

template<class Impl >

uint8_t BaseDynInst< Impl >::effSize

The size of the request.

Definition at line 233 of file base_dyn_inst.hh.

template<class Impl >

Fault BaseDynInst< Impl >::fault

The kind of fault this instruction has generated.

Definition at line 171 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::getFault().

template<class Impl >

Addr BaseDynInst< Impl >::instEffAddr

private

Instruction effective address.

Todo:: : Consider if this is necessary or not.

Definition at line 262 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::getEA(), and BaseDynInst< Impl >::setEA().

template<class Impl >

std::bitset<MaxFlags> BaseDynInst< Impl >::instFlags

protected

Definition at line 186 of file base_dyn_inst.hh.

template<class Impl >

ListIt BaseDynInst< Impl >::instListIt

Iterator pointing to this BaseDynInst in the list of all insts.

Definition at line 201 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::getInstListIt(), and BaseDynInst< Impl >::setInstListIt().

template<class Impl >

std::queue<Result> BaseDynInst< Impl >::instResult

protected

The result of the instruction; assumes an instruction can have many destination registers.

Definition at line 180 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::popResult(), BaseDynInst< Impl >::readResult(), and BaseDynInst< Impl >::setResult().

template<class Impl >

int16_t BaseDynInst< Impl >::lqIdx

Load queue index.

Definition at line 239 of file base_dyn_inst.hh.

template<class Impl >

const StaticInstPtr BaseDynInst< Impl >::macroop

The Macroop if one exists.

Definition at line 208 of file base_dyn_inst.hh.

template<class Impl >

uint8_t* BaseDynInst< Impl >::memData

Pointer to the data for the memory access.

Definition at line 236 of file base_dyn_inst.hh.

template<class Impl >

unsigned BaseDynInst< Impl >::memReqFlags

The memory request flags (from translation).

Definition at line 227 of file base_dyn_inst.hh.

template<class Impl >

TheISA::PCState BaseDynInst< Impl >::pc

protected

PC state for this instruction.

Definition at line 183 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::BaseDynInst(), BaseDynInst< Impl >::branchTarget(), BaseDynInst< Impl >::instAddr(), BaseDynInst< Impl >::microPC(), BaseDynInst< Impl >::mispredicted(), BaseDynInst< Impl >::nextInstAddr(), and BaseDynInst< Impl >::pcState().

template<class Impl >

Addr BaseDynInst< Impl >::physEffAddrHigh

The effective physical address of the second request for a split request.

Definition at line 224 of file base_dyn_inst.hh.

template<class Impl >

Addr BaseDynInst< Impl >::physEffAddrLow

The effective physical address.

Definition at line 219 of file base_dyn_inst.hh.

template<class Impl >

TheISA::PCState BaseDynInst< Impl >::predPC

Predicted PC state after this instruction.

Definition at line 205 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::BaseDynInst(), BaseDynInst< Impl >::mispredicted(), BaseDynInst< Impl >::predInstAddr(), BaseDynInst< Impl >::predMicroPC(), BaseDynInst< Impl >::predNextInstAddr(), BaseDynInst< Impl >::readPredTarg(), and BaseDynInst< Impl >::setPredTarg().

template<class Impl >

uint8_t BaseDynInst< Impl >::readyRegs

How many source registers are ready.

Definition at line 211 of file base_dyn_inst.hh.

template<class Impl >

RequestPtr BaseDynInst< Impl >::reqToVerify

Definition at line 256 of file base_dyn_inst.hh.

template<class Impl >

RequestPtr BaseDynInst< Impl >::savedReq

Saved memory requests (needed when the DTB address translation is delayed due to a hw page table walk).

Definition at line 250 of file base_dyn_inst.hh.

template<class Impl >

RequestPtr BaseDynInst< Impl >::savedSreqHigh

Definition at line 252 of file base_dyn_inst.hh.

template<class Impl >

RequestPtr BaseDynInst< Impl >::savedSreqLow

Definition at line 251 of file base_dyn_inst.hh.

template<class Impl >

InstSeqNum BaseDynInst< Impl >::seqNum

The sequence number of the instruction.

Definition at line 157 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::BaseDynInst().

template<class Impl >

int16_t BaseDynInst< Impl >::sqIdx

Store queue index.

Definition at line 242 of file base_dyn_inst.hh.

template<class Impl >

const StaticInstPtr BaseDynInst< Impl >::staticInst

The StaticInst used by this BaseDynInst.

Definition at line 160 of file base_dyn_inst.hh.

template<class Impl >

std::bitset<NumStatus> BaseDynInst< Impl >::status

protected

The status of this BaseDynInst.

Several bits can be set.

Definition at line 189 of file base_dyn_inst.hh.

template<class Impl >

ImplState* BaseDynInst< Impl >::thread

Pointer to the thread state.

Definition at line 168 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::contextId(), BaseDynInst< Impl >::readStCondFailures(), BaseDynInst< Impl >::setStCondFailures(), BaseDynInst< Impl >::setThreadState(), BaseDynInst< Impl >::tcBase(), and BaseO3DynInst< Impl >::updateMiscRegs().

template<class Impl >

ThreadID BaseDynInst< Impl >::threadNumber

The thread this instruction is from.

Definition at line 198 of file base_dyn_inst.hh.

Referenced by BaseDynInst< Impl >::armMonitor(), BaseDynInst< Impl >::getAddrMonitor(), BaseDynInst< Impl >::mwait(), BaseDynInst< Impl >::mwaitAtomic(), BaseO3DynInst< Impl >::readMiscReg(), BaseO3DynInst< Impl >::readMiscRegOperand(), and BaseDynInst< Impl >::setTid().

template<class Impl >

Trace::InstRecord* BaseDynInst< Impl >::traceData

InstRecord that tracks this instructions.

Definition at line 174 of file base_dyn_inst.hh.

Referenced by BaseO3DynInst< Impl >::calcEA(), BaseO3DynInst< Impl >::memAccess(), and BaseDynInst< Impl >::setPredicate().

The documentation for this class was generated from the following files:

cpu/base_dyn_inst.hh
cpu/base_dyn_inst_impl.hh

Classes

Public Types

Public Member Functions

Public Attributes

Protected Types

Protected Attributes

Private Member Functions

Private Attributes

Detailed Description

template<class Impl> class BaseDynInst< Impl >

Member Typedef Documentation

Member Enumeration Documentation

Constructor & Destructor Documentation

Member Function Documentation

Member Data Documentation

template<class Impl>
class BaseDynInst< Impl >