#include <tlb.hh>

Inheritance diagram for ArmISA::TLB:

Public Types
enum	ArmFlags { AlignmentMask = 0x7, AlignByte = 0x0, AlignHalfWord = 0x1, AlignWord = 0x2, AlignDoubleWord = 0x3, AlignQuadWord = 0x4, AlignOctWord = 0x5, AllowUnaligned = 0x8, UserMode = 0x10, MustBeOne = 0x40 }

enum	ArmTranslationType { NormalTran = 0, S1CTran = 0x1, HypMode = 0x2, S1S2NsTran = 0x4, S1E0Tran = 0x8, S1E1Tran = 0x10, S1E2Tran = 0x20, S1E3Tran = 0x40, S12E0Tran = 0x80, S12E1Tran = 0x100 }

Public Types inherited from BaseTLB
enum	Mode { Read, Write, Execute }

Public Types inherited from SimObject
typedef SimObjectParams	Params

Public Member Functions
	TLB (const ArmTLBParams *p)

	TLB (const Params p, int _size, TableWalker _walker)

TlbEntry *	lookup (Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, bool secure, bool functional, bool ignore_asn, uint8_t target_el)
	Lookup an entry in the TLB. More...

virtual	~TLB ()

void	takeOverFrom (BaseTLB *otlb) override
	Take over from an old tlb context. More...

void	init () override
	setup all the back pointers More...

void	setTestInterface (SimObject *ti)

TableWalker *	getTableWalker ()

void	setMMU (Stage2MMU *m, MasterID master_id)

int	getsize () const

void	insert (Addr vaddr, TlbEntry &pte)

Fault	getTE (TlbEntry *te, RequestPtr req, ThreadContext tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tranType)

Fault	getResultTe (TlbEntry *te, RequestPtr req, ThreadContext tc, Mode mode, Translation translation, bool timing, bool functional, TlbEntry mergeTe)

Fault	checkPermissions (TlbEntry *te, RequestPtr req, Mode mode)

Fault	checkPermissions64 (TlbEntry te, RequestPtr req, Mode mode, ThreadContext tc)

void	flushAllSecurity (bool secure_lookup, uint8_t target_el, bool ignore_el=false)
	Reset the entire TLB. More...

void	flushAllNs (bool hyp, uint8_t target_el, bool ignore_el=false)
	Remove all entries in the non secure world, depending on whether they were allocated in hyp mode or not. More...

void	flushAll () override
	Reset the entire TLB. More...

void	flushMvaAsid (Addr mva, uint64_t asn, bool secure_lookup, uint8_t target_el)
	Remove any entries that match both a va and asn. More...

void	flushAsid (uint64_t asn, bool secure_lookup, uint8_t target_el)
	Remove any entries that match the asn. More...

void	flushMva (Addr mva, bool secure_lookup, bool hyp, uint8_t target_el)
	Remove all entries that match the va regardless of asn. More...

void	flushIpaVmid (Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el)
	Invalidate all entries in the stage 2 TLB that match the given ipa and the current VMID. More...

Fault	trickBoxCheck (RequestPtr req, Mode mode, TlbEntry::DomainType domain)

Fault	walkTrickBoxCheck (Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level)

void	printTlb () const

void	demapPage (Addr vaddr, uint64_t asn) override

bool	translateFunctional (ThreadContext *tc, Addr vaddr, Addr &paddr)
	Do a functional lookup on the TLB (for debugging) and don't modify any internal state. More...

Fault	translateFunctional (RequestPtr req, ThreadContext *tc, Mode mode, ArmTranslationType tranType=NormalTran)
	Do a functional lookup on the TLB (for checker cpu) that behaves like a normal lookup without modifying any page table state. More...

void	setAttr (uint64_t attr)
	Accessor functions for memory attributes for last accessed TLB entry. More...

uint64_t	getAttr () const

Fault	translateFs (RequestPtr req, ThreadContext tc, Mode mode, Translation translation, bool &delay, bool timing, ArmTranslationType tranType, bool functional=false)

Fault	translateSe (RequestPtr req, ThreadContext tc, Mode mode, Translation translation, bool &delay, bool timing)

Fault	translateAtomic (RequestPtr req, ThreadContext *tc, Mode mode, ArmTranslationType tranType=NormalTran)

Fault	translateTiming (RequestPtr req, ThreadContext tc, Translation translation, Mode mode, ArmTranslationType tranType=NormalTran)

Fault	translateComplete (RequestPtr req, ThreadContext tc, Translation translation, Mode mode, ArmTranslationType tranType, bool callFromS2)

Fault	finalizePhysical (RequestPtr req, ThreadContext *tc, Mode mode) const

void	drainResume () override
	Resume execution after a successful drain. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

void	regStats () override
	Register statistics for this object. More...

void	regProbePoints () override
	Register probe points for this object. More...

BaseMasterPort *	getMasterPort () override
	Get the table walker master port. More...

const Params *	params () const

void	invalidateMiscReg ()

Fault	testTranslation (RequestPtr req, Mode mode, TlbEntry::DomainType domain)

Fault	testWalk (Addr pa, Addr size, Addr va, bool is_secure, Mode mode, TlbEntry::DomainType domain, LookupLevel lookup_level)

Public Member Functions inherited from BaseTLB
void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

Public Member Functions inherited from SimObject
const Params *	params () const

	SimObject (const Params *_params)

virtual	~SimObject ()

virtual const std::string	name () const

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	resetStats ()
	Reset statistics associated with this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from EventManager
	EventManager (EventManager &em)

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick)-1)

void	setCurTick (Tick newVal)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Protected Member Functions
void	updateMiscReg (ThreadContext *tc, ArmTranslationType tranType=NormalTran)

Protected Member Functions inherited from BaseTLB
	BaseTLB (const Params *p)

Protected Member Functions inherited from Drainable
	Drainable ()

virtual	~Drainable ()

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Attributes
TlbEntry *	table

int	size

bool	isStage2

bool	stage2Req

uint64_t	_attr

bool	directToStage2

TableWalker *	tableWalker

TLB *	stage2Tlb

Stage2MMU *	stage2Mmu

TlbTestInterface *	test

Stats::Scalar	instHits

Stats::Scalar	instMisses

Stats::Scalar	readHits

Stats::Scalar	readMisses

Stats::Scalar	writeHits

Stats::Scalar	writeMisses

Stats::Scalar	inserts

Stats::Scalar	flushTlb

Stats::Scalar	flushTlbMva

Stats::Scalar	flushTlbMvaAsid

Stats::Scalar	flushTlbAsid

Stats::Scalar	flushedEntries

Stats::Scalar	alignFaults

Stats::Scalar	prefetchFaults

Stats::Scalar	domainFaults

Stats::Scalar	permsFaults

Stats::Formula	readAccesses

Stats::Formula	writeAccesses

Stats::Formula	instAccesses

Stats::Formula	hits

Stats::Formula	misses

Stats::Formula	accesses

ProbePoints::PMUUPtr	ppRefills
	PMU probe for TLB refills. More...

int	rangeMRU

CPSR	cpsr

bool	aarch64

ExceptionLevel	aarch64EL

SCTLR	sctlr

SCR	scr

bool	isPriv

bool	isSecure

bool	isHyp

TTBCR	ttbcr

uint16_t	asid

uint8_t	vmid

PRRR	prrr

NMRR	nmrr

HCR	hcr

uint32_t	dacr

bool	miscRegValid

ContextID	miscRegContext

ArmTranslationType	curTranType

bool	haveLPAE

bool	haveVirtualization

bool	haveLargeAsid64

AddrRange	m5opRange

Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Private Member Functions
void	_flushMva (Addr mva, uint64_t asn, bool secure_lookup, bool hyp, bool ignore_asn, uint8_t target_el)
	Remove any entries that match both a va and asn. More...

bool	checkELMatch (uint8_t target_el, uint8_t tentry_el, bool ignore_el)

Additional Inherited Members
Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Get the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)

static void	unserializeGlobals (CheckpointIn &cp)

Static Public Attributes inherited from Serializable
static int	ckptCount = 0

static int	ckptMaxCount = 0

static int	ckptPrevCount = -1

Detailed Description

Definition at line 102 of file tlb.hh.

Member Enumeration Documentation

enum ArmISA::TLB::ArmFlags

Enumerator
AlignmentMask
AlignByte
AlignHalfWord
AlignWord
AlignDoubleWord
AlignQuadWord
AlignOctWord
AllowUnaligned
UserMode
MustBeOne

Definition at line 105 of file tlb.hh.

enum ArmISA::TLB::ArmTranslationType

Enumerator
NormalTran
S1CTran
HypMode
S1S2NsTran
S1E0Tran
S1E1Tran
S1E2Tran
S1E3Tran
S12E0Tran
S12E1Tran

Definition at line 124 of file tlb.hh.

Constructor & Destructor Documentation

TLB::TLB ( const ArmTLBParams * p )

Definition at line 76 of file tlb.cc.

References haveLargeAsid64, ArmISA::TableWalker::haveLargeAsid64(), haveLPAE, ArmISA::TableWalker::haveLPAE(), haveVirtualization, ArmISA::TableWalker::haveVirtualization(), ArmSystem::m5opRange(), m5opRange, ArmISA::TableWalker::setTlb(), and tableWalker.

ArmISA::TLB::TLB	(	const Params *	p,
		int	_size,
		TableWalker *	_walker
	)

TLB::~TLB ( )

virtual

Definition at line 98 of file tlb.cc.

References table.

Member Function Documentation

void TLB::_flushMva	(	Addr	mva,
		uint64_t	asn,
		bool	secure_lookup,
		bool	hyp,
		bool	ignore_asn,
		uint8_t	target_el
	)

private

Remove any entries that match both a va and asn.

Parameters

mva	virtual address to flush
asn	contextid/asn to flush on match
secure_lookup	if the operation affects the secure world
hyp	if the operation affects hyp mode
ignore_asn	if the flush should ignore the asn

Definition at line 337 of file tlb.cc.

References DPRINTF, flushedEntries, lookup(), MipsISA::te, and vmid.

Referenced by flushIpaVmid(), flushMva(), and flushMvaAsid().

bool TLB::checkELMatch	(	uint8_t	target_el,
		uint8_t	tentry_el,
		bool	ignore_el
	)

private

Definition at line 364 of file tlb.cc.

Referenced by flushAllNs(), flushAllSecurity(), and flushAsid().

Fault TLB::checkPermissions	(	TlbEntry *	te,
		RequestPtr	req,
		Mode	mode
	)

Definition at line 604 of file tlb.cc.

References alignFaults, ArmISA::ArmFault::AlignmentFault, AlignmentMask, ArmISA::TlbEntry::ap, dacr, ArmISA::TlbEntry::domain, domainFaults, ArmISA::ArmFault::DomainLL, DPRINTF, BaseTLB::Execute, Request::getFlags(), Request::getPC(), Request::getVaddr(), ArmISA::TlbEntry::hap, hcr, Request::isPrefetch(), isPriv, Request::isPTWalk(), isSecure, isStage2, ArmISA::TlbEntry::longDescFormat, ArmISA::TlbEntry::lookupLevel, ArmISA::ArmFault::LpaeTran, ArmISA::mask, ArmISA::TlbEntry::mtype, ArmISA::TlbEntry::NoAccess, NoFault, ArmISA::TlbEntry::nonCacheable, ArmISA::TlbEntry::Normal, ArmISA::TlbEntry::ns, panic, ArmISA::ArmFault::PermissionLL, permsFaults, ArmISA::ArmFault::PrefetchUncacheable, ArmISA::TlbEntry::pxn, scr, sctlr, UserMode, MipsISA::vaddr, ArmISA::ArmFault::VmsaTran, BaseTLB::Write, and ArmISA::TlbEntry::xn.

Referenced by getResultTe(), and ArmISA::Stage2LookUp::getTe().

Fault TLB::checkPermissions64	(	TlbEntry *	te,
		RequestPtr	req,
		Mode	mode,
		ThreadContext *	tc
	)

Definition at line 776 of file tlb.cc.

Referenced by getResultTe(), and ArmISA::Stage2LookUp::getTe().

void ArmISA::TLB::demapPage	(	Addr	vaddr,
		uint64_t	asn
	)

inlineoverridevirtual

Implements BaseTLB.

Definition at line 293 of file tlb.hh.

References panic.

void TLB::drainResume ( )

overridevirtual

Resume execution after a successful drain.

Reimplemented from Drainable.

Definition at line 378 of file tlb.cc.

References miscRegValid.

Fault TLB::finalizePhysical	(	RequestPtr	req,
		ThreadContext *	tc,
		Mode	mode
	)		const

Definition at line 136 of file tlb.cc.

References AddrRange::contains(), Request::GENERIC_IPR, Request::getPaddr(), GenericISA::iprAddressPseudoInst(), m5opRange, Request::MMAPPED_IPR, NoFault, Request::setFlags(), and Request::setPaddr().

Referenced by translateFs(), and translateSe().

void ArmISA::TLB::flushAll ( )

inlineoverridevirtual

Reset the entire TLB.

Used for CPU switching to prevent stale translations after multiple switches

Implements BaseTLB.

Definition at line 251 of file tlb.hh.

References flushAllSecurity().

void TLB::flushAllNs	(	bool	hyp,
		uint8_t	target_el,
		bool	ignore_el = `false`
	)

Remove all entries in the non secure world, depending on whether they were allocated in hyp mode or not.

Parameters

hyp	if the opperation affects hyp mode

Definition at line 267 of file tlb.cc.

References checkELMatch(), DPRINTF, ArmISA::TlbEntry::el, flushAllNs(), flushedEntries, flushTlb, ArmISA::TlbEntry::isHyp, isStage2, ArmISA::TlbEntry::nstid, ArmISA::TlbEntry::print(), size, stage2Tlb, table, MipsISA::te, ArmISA::TlbEntry::valid, and X86ISA::x.

Referenced by flushAllNs().

void TLB::flushAllSecurity	(	bool	secure_lookup,
		uint8_t	target_el,
		bool	ignore_el = `false`
	)

Reset the entire TLB.

Parameters

secure_lookup if the operation affects the secure world

Definition at line 238 of file tlb.cc.

References checkELMatch(), DPRINTF, ArmISA::TlbEntry::el, flushAllSecurity(), flushedEntries, flushTlb, isHyp, isStage2, ArmISA::TlbEntry::nstid, ArmISA::TlbEntry::print(), size, stage2Tlb, table, MipsISA::te, ArmISA::TlbEntry::valid, ArmISA::TlbEntry::vmid, vmid, and X86ISA::x.

Referenced by flushAll(), and flushAllSecurity().

void TLB::flushAsid	(	uint64_t	asn,
		bool	secure_lookup,
		uint8_t	target_el
	)

Remove any entries that match the asn.

Parameters

asn	contextid/asn to flush on match
secure_lookup	if the operation affects the secure world

Definition at line 304 of file tlb.cc.

References ArmISA::TlbEntry::asid, checkELMatch(), DPRINTF, ArmISA::TlbEntry::el, flushedEntries, flushTlbAsid, ArmISA::TlbEntry::nstid, ArmISA::TlbEntry::print(), size, table, MipsISA::te, ArmISA::TlbEntry::valid, ArmISA::TlbEntry::vmid, vmid, and X86ISA::x.

void TLB::flushIpaVmid	(	Addr	ipa,
		bool	secure_lookup,
		bool	hyp,
		uint8_t	target_el
	)

Invalidate all entries in the stage 2 TLB that match the given ipa and the current VMID.

Parameters

ipa	the address to invalidate
secure_lookup	if the operation affects the secure world
hyp	if the operation affects hyp mode

Definition at line 357 of file tlb.cc.

References _flushMva(), isStage2, and stage2Tlb.

void TLB::flushMva	(	Addr	mva,
		bool	secure_lookup,
		bool	hyp,
		uint8_t	target_el
	)

Remove all entries that match the va regardless of asn.

Parameters

mva	address to flush from cache
secure_lookup	if the operation affects the secure world
hyp	if the operation affects hyp mode

Definition at line 328 of file tlb.cc.

References _flushMva(), DPRINTF, and flushTlbMva.

void TLB::flushMvaAsid	(	Addr	mva,
		uint64_t	asn,
		bool	secure_lookup,
		uint8_t	target_el
	)

Remove any entries that match both a va and asn.

Parameters

mva	virtual address to flush
asn	contextid/asn to flush on match
secure_lookup	if the operation affects the secure world

Definition at line 294 of file tlb.cc.

References _flushMva(), DPRINTF, and flushTlbMvaAsid.

uint64_t ArmISA::TLB::getAttr ( ) const

inline

Definition at line 325 of file tlb.hh.

References _attr.

BaseMasterPort * TLB::getMasterPort ( )

overridevirtual

Get the table walker master port.

This is used for migrating port connections during a CPU takeOverFrom() call. For architectures that do not have a table walker, NULL is returned, hence the use of a pointer rather than a reference. For ARM this method will always return a valid port pointer.

Returns: A pointer to the walker master port

Reimplemented from BaseTLB.

Definition at line 1227 of file tlb.cc.

References ArmISA::Stage2MMU::getPort(), and stage2Mmu.

Fault TLB::getResultTe	(	TlbEntry **	te,
		RequestPtr	req,
		ThreadContext *	tc,
		Mode	mode,
		Translation *	translation,
		bool	timing,
		bool	functional,
		TlbEntry *	mergeTe
	)

Definition at line 1441 of file tlb.cc.

References aarch64, ArmISA::ArmFault::annotate(), checkPermissions(), checkPermissions64(), curTranType, DPRINTF, Request::getPaddr(), ArmISA::Stage2LookUp::getTe(), getTE(), Request::getVaddr(), Request::hasPaddr(), ArmISA::Stage2LookUp::isComplete(), isSecure, isStage2, NoFault, ArmISA::ArmFault::OVA, ArmISA::ArmFault::S1PTW, ArmISA::Stage2LookUp::setSelfDelete(), stage2Req, and stage2Tlb.

Referenced by translateFs().

int ArmISA::TLB::getsize ( ) const

inline

Definition at line 218 of file tlb.hh.

References size.

TableWalker* ArmISA::TLB::getTableWalker ( )

inline

Definition at line 214 of file tlb.hh.

References tableWalker.

Fault TLB::getTE	(	TlbEntry **	te,
		RequestPtr	req,
		ThreadContext *	tc,
		Mode	mode,
		Translation *	translation,
		bool	timing,
		bool	functional,
		bool	is_secure,
		TLB::ArmTranslationType	tranType
	)

Definition at line 1379 of file tlb.cc.

References aarch64, aarch64EL, asid, DPRINTF, ArmISA::EL1, BaseTLB::Execute, Request::getVaddr(), instHits, instMisses, isHyp, Request::isPrefetch(), isStage2, lookup(), NoFault, prefetchFaults, ArmISA::ArmFault::PrefetchTLBMiss, printTlb(), ArmISA::purifyTaggedAddr(), readHits, readMisses, stage2Req, tableWalker, ttbcr, MipsISA::vaddr, vmid, ArmISA::TableWalker::walk(), BaseTLB::Write, writeHits, and writeMisses.

Referenced by ArmISA::Stage2LookUp::finish(), getResultTe(), and ArmISA::Stage2LookUp::getTe().

void TLB::init ( )

overridevirtual

setup all the back pointers

Reimplemented from SimObject.

Definition at line 104 of file tlb.cc.

References isStage2, stage2Mmu, ArmISA::Stage2MMU::stage2Tlb(), and stage2Tlb.

void TLB::insert	(	Addr	vaddr,
		TlbEntry &	pte
	)

void ArmISA::TLB::invalidateMiscReg ( )

inline

Definition at line 407 of file tlb.hh.

References miscRegValid.

TlbEntry * TLB::lookup	(	Addr	vpn,
		uint16_t	asn,
		uint8_t	vmid,
		bool	hyp,
		bool	secure,
		bool	functional,
		bool	ignore_asn,
		uint8_t	target_el
	)

Lookup an entry in the TLB.

Parameters

vpn	virtual address
asn	context id/address space id to use
vmid	The virtual machine ID used for stage 2 translation
secure	if the lookup is secure
hyp	if the lookup is done from hyp mode
functional	if the lookup should modify state
ignore_asn	if on lookup asn should be ignored

Returns: pointer to TLB entry if it exists

Definition at line 151 of file tlb.cc.

References ArmISA::TlbEntry::ap, ArmISA::TlbEntry::asid, DPRINTF, ArmISA::TlbEntry::el, ArmISA::TlbEntry::global, ArmISA::i, ArmISA::TlbEntry::ns, ArmISA::TlbEntry::nstid, ArmISA::TlbEntry::pAddr(), ArmISA::TlbEntry::pfn, rangeMRU, ArmISA::TlbEntry::size, size, table, and X86ISA::x.

Referenced by _flushMva(), getTE(), ArmISA::TableWalker::processWalkWrapper(), and translateFunctional().

const Params* ArmISA::TLB::params ( ) const

inline

Definition at line 403 of file tlb.hh.

References SimObject::_params.

void TLB::printTlb ( ) const

Definition at line 224 of file tlb.cc.

References DPRINTF, ArmISA::TlbEntry::print(), size, table, MipsISA::te, ArmISA::TlbEntry::valid, and X86ISA::x.

Referenced by getTE().

void TLB::regProbePoints ( )

overridevirtual

Register probe points for this object.

No probe points by default, so do nothing in base.

Reimplemented from SimObject.

Definition at line 558 of file tlb.cc.

References SimObject::getProbeManager(), and ppRefills.

void TLB::regStats ( )

overridevirtual

Register statistics for this object.

Reimplemented from SimObject.

Definition at line 441 of file tlb.cc.

References accesses, alignFaults, Stats::DataWrap< Derived, InfoProxyType >::desc(), domainFaults, flushedEntries, flushTlb, flushTlbAsid, flushTlbMva, flushTlbMvaAsid, hits, instAccesses, instHits, instMisses, misses, SimObject::name(), Stats::DataWrap< Derived, InfoProxyType >::name(), permsFaults, prefetchFaults, readAccesses, readHits, readMisses, SimObject::regStats(), writeAccesses, writeHits, and writeMisses.

void TLB::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 409 of file tlb.cc.

References _attr, csprintf(), directToStage2, DPRINTF, haveLPAE, ArmISA::i, SERIALIZE_SCALAR, Serializable::serializeSection(), size, stage2Req, and table.

void ArmISA::TLB::setAttr ( uint64_t attr )

inline

Accessor functions for memory attributes for last accessed TLB entry.

Definition at line 319 of file tlb.hh.

References _attr, and ArmISA::attr.

Referenced by translateFs().

void TLB::setMMU	(	Stage2MMU *	m,
		MasterID	master_id
	)

Definition at line 111 of file tlb.cc.

References ArmISA::m, ArmISA::TableWalker::setMMU(), stage2Mmu, and tableWalker.

Referenced by ArmISA::Stage2MMU::Stage2MMU().

void TLB::setTestInterface ( SimObject * ti )

Definition at line 1512 of file tlb.cc.

References fatal_if(), SimObject::name(), test, and MipsISA::ti.

void TLB::takeOverFrom ( BaseTLB * otlb )

overridevirtual

Take over from an old tlb context.

Implements BaseTLB.

Definition at line 386 of file tlb.cc.

References _attr, directToStage2, haveLPAE, isStage2, panic, stage2Req, stage2Tlb, and takeOverFrom().

Referenced by takeOverFrom().

Fault TLB::testTranslation	(	RequestPtr	req,
		Mode	mode,
		TlbEntry::DomainType	domain
	)

Definition at line 1524 of file tlb.cc.

References Request::getSize(), Request::hasSize(), isPriv, NoFault, test, and ArmISA::TlbTestInterface::translationCheck().

Referenced by translateFs().

Fault TLB::testWalk	(	Addr	pa,
		Addr	size,
		Addr	va,
		bool	is_secure,
		Mode	mode,
		TlbEntry::DomainType	domain,
		LookupLevel	lookup_level
	)

Definition at line 1534 of file tlb.cc.

References isPriv, NoFault, test, and ArmISA::TlbTestInterface::walkCheck().

Referenced by ArmISA::TableWalker::testWalk().

Fault TLB::translateAtomic	(	RequestPtr	req,
		ThreadContext *	tc,
		Mode	mode,
		TLB::ArmTranslationType	tranType = `NormalTran`
	)

Definition at line 1141 of file tlb.cc.

References directToStage2, FullSystem, stage2Tlb, translateAtomic(), translateFs(), translateSe(), and updateMiscReg().

Referenced by ArmISA::Stage2MMU::readDataUntimed(), and translateAtomic().

Fault TLB::translateComplete	(	RequestPtr	req,
		ThreadContext *	tc,
		Translation *	translation,
		Mode	mode,
		TLB::ArmTranslationType	tranType,
		bool	callFromS2
	)

Definition at line 1199 of file tlb.cc.

References DPRINTF, BaseTLB::Translation::finish(), FullSystem, Request::hasPaddr(), BaseTLB::Translation::markDelayed(), NoFault, stage2Req, translateFs(), and translateSe().

Referenced by ArmISA::Stage2LookUp::finish(), and translateTiming().

Fault TLB::translateFs	(	RequestPtr	req,
		ThreadContext *	tc,
		Mode	mode,
		Translation *	translation,
		bool &	delay,
		bool	timing,
		TLB::ArmTranslationType	tranType,
		bool	functional = `false`
	)

Definition at line 976 of file tlb.cc.

Referenced by translateAtomic(), translateComplete(), and translateFunctional().

bool TLB::translateFunctional	(	ThreadContext *	tc,
		Addr	vaddr,
		Addr &	paddr
	)

Do a functional lookup on the TLB (for debugging) and don't modify any internal state.

Parameters

tc	thread context to get the context id from
vaddr	virtual address to translate
pa	returned physical address

Returns: if the translation was successful

Definition at line 118 of file tlb.cc.

References aarch64, aarch64EL, asid, directToStage2, ArmISA::e, ArmISA::EL1, isHyp, isSecure, lookup(), ArmISA::TlbEntry::pAddr(), stage2Tlb, translateFunctional(), updateMiscReg(), and vmid.

Referenced by ArmISA::Stage2MMU::readDataUntimed(), translateFunctional(), and try_translate().

Fault TLB::translateFunctional	(	RequestPtr	req,
		ThreadContext *	tc,
		Mode	mode,
		TLB::ArmTranslationType	tranType = `NormalTran`
	)

Do a functional lookup on the TLB (for checker cpu) that behaves like a normal lookup without modifying any page table state.

Definition at line 1162 of file tlb.cc.

References directToStage2, FullSystem, stage2Tlb, translateFs(), translateFunctional(), translateSe(), and updateMiscReg().

Fault TLB::translateSe	(	RequestPtr	req,
		ThreadContext *	tc,
		Mode	mode,
		Translation *	translation,
		bool &	delay,
		bool	timing
	)

Definition at line 564 of file tlb.cc.

References aarch64, aarch64EL, ArmISA::ArmFault::AlignmentFault, AlignmentMask, AllowUnaligned, BaseTLB::Execute, finalizePhysical(), Request::getFlags(), ThreadContext::getProcessPtr(), Request::getVaddr(), isStage2, ArmISA::mask, MustBeOne, ArmISA::TlbEntry::NoAccess, MipsISA::p, Process::pTable, ArmISA::purifyTaggedAddr(), sctlr, Request::setPaddr(), PageTableBase::translate(), ttbcr, updateMiscReg(), MipsISA::vaddr, ArmISA::ArmFault::VmsaTran, and BaseTLB::Write.

Referenced by translateAtomic(), translateComplete(), and translateFunctional().

Fault TLB::translateTiming	(	RequestPtr	req,
		ThreadContext *	tc,
		Translation *	translation,
		Mode	mode,
		TLB::ArmTranslationType	tranType = `NormalTran`
	)

Definition at line 1183 of file tlb.cc.

References directToStage2, isStage2, stage2Tlb, translateComplete(), translateTiming(), and updateMiscReg().

Referenced by ArmISA::TableWalker::doL1DescriptorWrapper(), ArmISA::TableWalker::doL2DescriptorWrapper(), ArmISA::TableWalker::doLongDescriptorWrapper(), ArmISA::TableWalker::processWalkWrapper(), ArmISA::Stage2MMU::Stage2Translation::translateTiming(), and translateTiming().

Fault ArmISA::TLB::trickBoxCheck	(	RequestPtr	req,
		Mode	mode,
		TlbEntry::DomainType	domain
	)

void TLB::unserialize ( CheckpointIn & cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 425 of file tlb.cc.

References _attr, csprintf(), directToStage2, DPRINTF, haveLPAE, ArmISA::i, size, stage2Req, table, UNSERIALIZE_SCALAR, and Serializable::unserializeSection().

void TLB::updateMiscReg	(	ThreadContext *	tc,
		ArmTranslationType	tranType = `NormalTran`
	)

protected

Definition at line 1233 of file tlb.cc.

References aarch64, aarch64EL, asid, bits(), ThreadContext::contextId(), cpsr, curTranType, dacr, directToStage2, DPRINTF, ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::ELIs64(), ArmISA::flattenMiscRegNsBanked(), haveLargeAsid64, haveVirtualization, hcr, HypMode, ArmISA::inSecureState(), isHyp, isPriv, isSecure, isStage2, ArmISA::longDescFormatInUse(), ArmISA::MISCREG_CONTEXTIDR, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_DACR, ArmISA::MISCREG_HCR, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_HSCTLR, ArmISA::MISCREG_NMRR, ArmISA::MISCREG_PRRR, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SCTLR, ArmISA::MISCREG_SCTLR_EL1, ArmISA::MISCREG_SCTLR_EL2, ArmISA::MISCREG_SCTLR_EL3, ArmISA::MISCREG_TCR_EL1, ArmISA::MISCREG_TCR_EL2, ArmISA::MISCREG_TCR_EL3, ArmISA::MISCREG_TTBCR, ArmISA::MISCREG_TTBR0, ArmISA::MISCREG_TTBR0_EL1, ArmISA::MISCREG_TTBR1, ArmISA::MISCREG_TTBR1_EL1, ArmISA::MISCREG_VTTBR, ArmISA::MISCREG_VTTBR_EL2, miscRegContext, miscRegValid, ArmISA::MODE_HYP, ArmISA::MODE_USER, nmrr, NormalTran, ArmISA::opModeToEL(), prrr, ThreadContext::readMiscReg(), S12E0Tran, S12E1Tran, S1CTran, S1E0Tran, S1E1Tran, S1E2Tran, S1E3Tran, S1S2NsTran, scr, sctlr, stage2Req, ttbcr, and vmid.

Referenced by checkPermissions64(), translateAtomic(), translateFs(), translateFunctional(), translateSe(), and translateTiming().

Fault ArmISA::TLB::walkTrickBoxCheck	(	Addr	pa,
		bool	is_secure,
		Addr	va,
		Addr	sz,
		bool	is_exec,
		bool	is_write,
		TlbEntry::DomainType	domain,
		LookupLevel	lookup_level
	)