ArmISA::PMU Class Reference

Model of an ARM PMU version 3. More...

#include <pmu.hh>

Inheritance diagram for ArmISA::PMU:

Classes
struct	CounterState
	State of a counter within the PMU. More...
struct	EventType
	Event type configuration. More...
class	ProbeListener

Public Member Functions
	PMU (const ArmPMUParams *p)
	~PMU ()
void	addEventProbe (unsigned int id, SimObject *obj, const char *name)
void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...
void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...
void	drainResume () override
	Resume execution after a successful drain. More...
void	setMiscReg (int misc_reg, MiscReg val) override
	Set a register within the PMU. More...
MiscReg	readMiscReg (int misc_reg) override
	Read a register within the PMU. More...
Public Member Functions inherited from SimObject
const Params *	params () const
	SimObject (const Params *_params)
virtual	~SimObject ()
virtual const std::string	name () const
virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...
virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...
virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...
virtual void	regStats ()
	Register statistics for this object. More...
virtual void	resetStats ()
	Reset statistics associated with this object. More...
virtual void	regProbePoints ()
	Register probe points for this object. More...
virtual void	regProbeListeners ()
	Register probe listeners for this object. More...
ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...
virtual void	startup ()
	startup() is the final initialization call before simulation. More...
DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...
virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...
virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...
void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...
void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...
Public Member Functions inherited from EventManager
	EventManager (EventManager &em)
	EventManager (EventManager *em)
	EventManager (EventQueue *eq)
EventQueue *	eventQueue () const
void	schedule (Event &event, Tick when)
void	deschedule (Event &event)
void	reschedule (Event &event, Tick when, bool always=false)
void	schedule (Event *event, Tick when)
void	deschedule (Event *event)
void	reschedule (Event *event, Tick when, bool always=false)
void	wakeupEventQueue (Tick when=(Tick)-1)
void	setCurTick (Tick newVal)
Public Member Functions inherited from Serializable
	Serializable ()
virtual	~Serializable ()
void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...
void	serializeSection (CheckpointOut &cp, const std::string &name) const
void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...
void	unserializeSection (CheckpointIn &cp, const std::string &name)
Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...
virtual void	notifyFork ()
	Notify a child process of a fork. More...
Public Member Functions inherited from ArmISA::BaseISADevice
	BaseISADevice ()
virtual	~BaseISADevice ()
virtual void	setISA (ISA *isa)

Protected Types
typedef unsigned int	EventTypeId
	Event type ID. More...
typedef std::unique_ptr < ProbeListener >	ProbeListenerUPtr

Protected Member Functions
	BitUnion32 (PMCR_t) Bitfield< 0 > e
	EndBitUnion (PMCR_t) BitUnion32(PMSELR_t) Bitfield<4
	EndBitUnion (PMSELR_t) BitUnion32(PMEVTYPER_t) Bitfield<9
	EndBitUnion (PMEVTYPER_t) typedef unsigned int CounterId
	Counter ID within the PMU. More...
MiscReg	readMiscRegInt (int misc_reg)
void	setControlReg (PMCR_t val)
	PMCR write handling. More...
void	resetEventCounts ()
	Reset all event counters excluding the cycle counter to zero. More...
void	raiseInterrupt ()
	Deliver a PMU interrupt to the GIC. More...
uint64_t	getCounterValue (CounterId id) const
	Get the value of a performance counter. More...
void	setCounterValue (CounterId id, uint64_t val)
	Set the value of a performance counter. More...
PMEVTYPER_t	getCounterTypeRegister (CounterId id) const
	Get the type and filter settings of a counter (PMEVTYPER) More...
void	setCounterTypeRegister (CounterId id, PMEVTYPER_t type)
	Set the type and filter settings of a performance counter (PMEVTYPER) More...
void	handleEvent (CounterId id, uint64_t delta)
	Handle an counting event triggered by a probe. More...
bool	isValidCounter (CounterId id) const
	Is this a valid counter ID? More...
CounterState &	getCounter (CounterId id)
	Return the state of a counter. More...
const CounterState &	getCounter (CounterId id) const
	Return the state of a counter. More...
void	updateCounter (CounterId id, CounterState &ctr)
	Depending on counter configuration, add or remove the probes driving the counter. More...
bool	isFiltered (const CounterState &ctr) const
	Check if a counter's settings allow it to be counted. More...
void	updateAllCounters ()
	Call updateCounter() for each counter in the PMU if the counter's state has changed. More...
Protected Member Functions inherited from Drainable
	Drainable ()
virtual	~Drainable ()
void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Attributes
Bitfield< 1 >	p
Bitfield< 2 >	c
Bitfield< 3 >	d
Bitfield< 4 >	x
Bitfield< 5 >	dp
Bitfield< 6 >	lc
Bitfield< 15, 11 >	n
Bitfield< 23, 16 >	idcode
Bitfield< 31, 24 >	imp
	sel
	evtCount
Bitfield< 26 >	m
Bitfield< 27 >	nsh
Bitfield< 28 >	nsu
Bitfield< 29 >	nsk
Bitfield< 30 >	u
Bitfield< 31 >	p
MiscReg	reg_pmcnten
	Performance Monitor Count Enable Register. More...
PMCR_t	reg_pmcr
	Performance Monitor Control Register. More...
PMSELR_t	reg_pmselr
	Performance Monitor Selection Register. More...
MiscReg	reg_pminten
	Performance Monitor Interrupt Enable Register. More...
MiscReg	reg_pmovsr
	Performance Monitor Overflow Status Register. More...
uint64_t	reg_pmceid
	Performance counter ID register. More...
unsigned	clock_remainder
	Remainder part when the clock counter is divided by 64. More...
std::vector< CounterState >	counters
	State of all general-purpose counters supported by PMU. More...
CounterState	cycleCounter
	State of the cycle counter. More...
PMCR_t	reg_pmcr_conf
	Constant (configuration-dependent) part of the PMCR. More...
const unsigned int	pmuInterrupt
	Performance monitor interrupt number. More...
Platform *const	platform
	Platform this device belongs to. More...
std::multimap< EventTypeId, EventType >	pmuEventTypes
	Event types supported by this PMU. More...
Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...
Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...
Protected Attributes inherited from ArmISA::BaseISADevice
ISA *	isa

Static Protected Attributes
static const CounterId	PMCCNTR = 31
	Cycle Count Register Number. More...
static const EventTypeId	ARCH_EVENT_SW_INCR = 0x00
	ID of the software increment event. More...
static const MiscReg	reg_pmcr_wr_mask = 0x39
	PMCR write mask when accessed from the guest. More...

Additional Inherited Members
Public Types inherited from SimObject
typedef SimObjectParams	Params
Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...
static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...
Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Get the fully-qualified name of the active section. More...
static void	serializeAll (const std::string &cpt_dir)
static void	unserializeGlobals (CheckpointIn &cp)
Static Public Attributes inherited from Serializable
static int	ckptCount = 0
static int	ckptMaxCount = 0
static int	ckptPrevCount = -1

Detailed Description

Model of an ARM PMU version 3.

This class implements a subset of the ARM PMU v3 specification as described in the ARMv8 reference manual. It supports most of the features of the PMU, however the following features are known to be missing:

• Event filtering (e.g., from different privilege levels).
• Access controls (the PMU currently ignores the execution level).
• The chain counter (event no. 0x1E) is unimplemented.

The PMU itself does not implement any events, in merely provides an interface for the configuration scripts to hook up probes that drive events. Configuration scripts should call addEventProbe() to configure custom events or high-level methods to configure architected events. The Python implementation of addEventProbe() automatically delays event type registration until after instantiation.

In order to support CPU switching and some combined counters (e.g., memory references synthesized from loads and stores), the PMU allows multiple probes per event type. When creating a system that switches between CPU models that share the same PMU, PMU events for all of the CPU models can be registered with the PMU.

See Also

The ARM Architecture Refererence Manual (DDI 0487A)

Definition at line 91 of file pmu.hh.

Member Typedef Documentation

typedef unsigned int ArmISA::PMU::EventTypeId

protected

Event type ID.

See the PMU documentation for a list of architected IDs.

Definition at line 184 of file pmu.hh.

typedef std::unique_ptr<ProbeListener> ArmISA::PMU::ProbeListenerUPtr

protected

Definition at line 281 of file pmu.hh.

Constructor & Destructor Documentation

ArmISA::PMU::PMU

(

const ArmPMUParams *

p

)

Definition at line 58 of file pmu.cc.

References cycleCounter, DPRINTF, ArmISA::PMU::CounterState::eventId, fatal, and reg_pmcr_conf.

ArmISA::PMU::~PMU

(

)

Definition at line 86 of file pmu.cc.

Member Function Documentation

void ArmISA::PMU::addEventProbe	(	unsigned int	id,
		SimObject *	obj,
		const char *	name
	)

Definition at line 91 of file pmu.cc.

References DPRINTF, SparcISA::id, SimObject::name(), pmuEventTypes, reg_pmceid, and ULL.

ArmISA::PMU::BitUnion32 ( PMCR_t  )

protected

void ArmISA::PMU::drainResume ( )

overridevirtual

Resume execution after a successful drain.

Reimplemented from Drainable.

Definition at line 104 of file pmu.cc.

References updateAllCounters().

ArmISA::PMU::EndBitUnion ( PMCR_t  )

protected

ArmISA::PMU::EndBitUnion ( PMSELR_t  )

protected

ArmISA::PMU::EndBitUnion ( PMEVTYPER_t  )

protected

Counter ID within the PMU.

This value is typically used to index into various registers controlling interrupts and overflows. The value normally in the [0, 31] range, where 31 refers to the cycle counter.

CounterState& ArmISA::PMU::getCounter ( CounterId  id )

inlineprotected

Return the state of a counter.

Parameters

id	ID of counter within the PMU.

Returns

Reference to a CounterState instance representing the counter.

Definition at line 396 of file pmu.hh.

References counters, cycleCounter, SparcISA::id, isValidCounter(), and PMCCNTR.

Referenced by getCounterTypeRegister(), getCounterValue(), handleEvent(), setCounterTypeRegister(), setCounterValue(), and setMiscReg().

const CounterState& ArmISA::PMU::getCounter ( CounterId  id ) const

inlineprotected

Return the state of a counter.

Parameters

id	ID of counter within the PMU.

Returns

Reference to a CounterState instance representing the counter.

Definition at line 409 of file pmu.hh.

References counters, cycleCounter, SparcISA::id, isValidCounter(), and PMCCNTR.

PMU::PMEVTYPER_t ArmISA::PMU::getCounterTypeRegister ( CounterId  id ) const

protected

Get the type and filter settings of a counter (PMEVTYPER)

This method implements a read from a PMEVTYPER register. It returns the type value and filter settings of a general purpose performance counter or the cycle counter. Non-existing counters are treated as constant '0'.

Parameters

id	Counter ID within the PMU.

Returns

Performance counter type ID.

Definition at line 465 of file pmu.cc.

References ArmISA::PMU::CounterState::eventId, ArmISA::PMU::CounterState::filter, getCounter(), isValidCounter(), and X86ISA::type.

Referenced by readMiscRegInt().

uint64_t ArmISA::PMU::getCounterValue ( CounterId  id ) const

inlineprotected

Get the value of a performance counter.

This method returns the value of a general purpose performance counter or the fixed-function cycle counter. Non-existing counters are treated as constant '0'.

Returns

Value of the performance counter, 0 if the counter does not exist.

Definition at line 222 of file pmu.hh.

References getCounter(), isValidCounter(), and ArmISA::PMU::CounterState::value.

Referenced by readMiscRegInt().

void ArmISA::PMU::handleEvent ( CounterId  id, uint64_t  delta  )

protected

Handle an counting event triggered by a probe.

This method is called by the ProbeListener class whenever an active probe is triggered. Ths method adds the event count from the probe to the affected counter, checks for overflows, and delivers an interrupt if needed.

Parameters

id	Counter ID affected by the probe.
delta	Counter increment

Definition at line 385 of file pmu.cc.

References ArmISA::PMU::CounterState::add(), clock_remainder, DPRINTF, getCounter(), SparcISA::id, isFiltered(), PMCCNTR, raiseInterrupt(), reg_pmcr, reg_pminten, and reg_pmovsr.

Referenced by ArmISA::PMU::ProbeListener::notify().

bool ArmISA::PMU::isFiltered ( const CounterState &  ctr ) const

protected

Check if a counter's settings allow it to be counted.

Parameters

ctr	Counter state instance representing this counter.

Returns

false if the counter is active, true otherwise.

Definition at line 356 of file pmu.cc.

References ArmISA::el, ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::PMU::CounterState::filter, ArmISA::inSecureState(), ArmISA::BaseISADevice::isa, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_SCR, ArmISA::opModeToEL(), panic, and ArmISA::ISA::readMiscRegNoEffect().

Referenced by handleEvent().

bool ArmISA::PMU::isValidCounter ( CounterId  id ) const

inlineprotected

Is this a valid counter ID?

Parameters

id	ID of counter within the PMU.

Returns

true if counter is within the allowed range or the cycle counter, false otherwise.

Definition at line 385 of file pmu.hh.

References counters, and PMCCNTR.

Referenced by getCounter(), getCounterTypeRegister(), getCounterValue(), setCounterTypeRegister(), and setCounterValue().

void ArmISA::PMU::raiseInterrupt ( )

protected

Deliver a PMU interrupt to the GIC.

Definition at line 503 of file pmu.cc.

References DPRINTF, RealView::gic, platform, pmuInterrupt, BaseGic::sendInt(), and warn_once.

Referenced by handleEvent().

MiscReg ArmISA::PMU::readMiscReg ( int  misc_reg )

overridevirtual

Read a register within the PMU.

Parameters

misc_reg

Register number (see miscregs.hh)

Returns

Register value.

Implements ArmISA::BaseISADevice.

Definition at line 222 of file pmu.cc.

References DPRINTF, ArmISA::miscRegName, readMiscRegInt(), ArmISA::unflattenMiscReg(), and X86ISA::val.

MiscReg ArmISA::PMU::readMiscRegInt ( int  misc_reg )

protected

Definition at line 231 of file pmu.cc.

References cycleCounter, getCounterTypeRegister(), getCounterValue(), ArmISA::MISCREG_PMCCFILTR, ArmISA::MISCREG_PMCCFILTR_EL0, ArmISA::MISCREG_PMCCNTR, ArmISA::MISCREG_PMCCNTR_EL0, ArmISA::MISCREG_PMCEID0, ArmISA::MISCREG_PMCEID0_EL0, ArmISA::MISCREG_PMCEID1, ArmISA::MISCREG_PMCEID1_EL0, ArmISA::MISCREG_PMCNTENCLR, ArmISA::MISCREG_PMCNTENCLR_EL0, ArmISA::MISCREG_PMCNTENSET, ArmISA::MISCREG_PMCNTENSET_EL0, ArmISA::MISCREG_PMCR, ArmISA::MISCREG_PMCR_EL0, ArmISA::MISCREG_PMEVCNTR0_EL0, ArmISA::MISCREG_PMEVTYPER0_EL0, ArmISA::MISCREG_PMINTENCLR, ArmISA::MISCREG_PMINTENCLR_EL1, ArmISA::MISCREG_PMINTENSET, ArmISA::MISCREG_PMINTENSET_EL1, ArmISA::MISCREG_PMOVSCLR_EL0, ArmISA::MISCREG_PMOVSR, ArmISA::MISCREG_PMOVSSET, ArmISA::MISCREG_PMOVSSET_EL0, ArmISA::MISCREG_PMSELR, ArmISA::MISCREG_PMSWINC, ArmISA::MISCREG_PMSWINC_EL0, ArmISA::MISCREG_PMUSERENR, ArmISA::MISCREG_PMUSERENR_EL0, ArmISA::MISCREG_PMXEVCNTR, ArmISA::MISCREG_PMXEVCNTR_EL0, ArmISA::MISCREG_PMXEVTYPER, ArmISA::MISCREG_PMXEVTYPER_EL0, ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, ArmISA::miscRegName, panic, PMCCNTR, reg_pmceid, reg_pmcnten, reg_pmcr, reg_pmcr_conf, reg_pmcr_wr_mask, reg_pminten, reg_pmovsr, reg_pmselr, ArmISA::unflattenMiscReg(), ArmISA::PMU::CounterState::value, and warn.

Referenced by readMiscReg().

void ArmISA::PMU::resetEventCounts ( )

protected

Reset all event counters excluding the cycle counter to zero.

Definition at line 445 of file pmu.cc.

References counters.

Referenced by setControlReg().

void ArmISA::PMU::serialize ( CheckpointOut &  cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 516 of file pmu.cc.

References clock_remainder, counters, csprintf(), cycleCounter, DPRINTF, ArmISA::i, reg_pmceid, reg_pmcnten, reg_pmcr, reg_pminten, reg_pmovsr, reg_pmselr, SERIALIZE_SCALAR, and Serializable::serializeSection().

void ArmISA::PMU::setControlReg ( PMCR_t  val )

protected

PMCR write handling.

The PMCR register needs special handling since writing to it changes PMU-global state (e.g., resets all counters).

Parameters

val	New PMCR value

Definition at line 312 of file pmu.cc.

References clock_remainder, cycleCounter, DPRINTF, reg_pmcr, reg_pmcr_wr_mask, resetEventCounts(), updateAllCounters(), and ArmISA::PMU::CounterState::value.

Referenced by setMiscReg().

void ArmISA::PMU::setCounterTypeRegister ( CounterId  id, PMEVTYPER_t  type  )

protected

Set the type and filter settings of a performance counter (PMEVTYPER)

This method implements a write to a PMEVTYPER register. It sets the type value and filter settings of a general purpose performance counter or the cycle counter. Writes to non-existing counters are ignored. The method automatically updates the probes used by the counter if it is enabled.

Parameters

id	Counter ID within the PMU.
type	Performance counter type and filter configuration..

Definition at line 479 of file pmu.cc.

References DPRINTF, ArmISA::PMU::CounterState::eventId, ArmISA::PMU::CounterState::filter, getCounter(), isValidCounter(), PMCCNTR, reg_pmselr, updateCounter(), X86ISA::val, and warn_once.

Referenced by setMiscReg().

void ArmISA::PMU::setCounterValue ( CounterId  id, uint64_t  val  )

protected

Set the value of a performance counter.

This method sets the value of a general purpose performance counter or the fixed-function cycle counter. Writes to non-existing counters are ignored.

Definition at line 452 of file pmu.cc.

References getCounter(), isValidCounter(), X86ISA::val, ArmISA::PMU::CounterState::value, and warn_once.

Referenced by setMiscReg().

void ArmISA::PMU::setMiscReg ( int  misc_reg, MiscReg  val  )

overridevirtual

Set a register within the PMU.

Parameters

misc_reg	Register number (see miscregs.hh)
val	Value to store

Implements ArmISA::BaseISADevice.

Definition at line 111 of file pmu.cc.

References counters, cycleCounter, DPRINTF, ArmISA::PMU::CounterState::enabled, getCounter(), ArmISA::i, ArmISA::MISCREG_PMCCFILTR, ArmISA::MISCREG_PMCCFILTR_EL0, ArmISA::MISCREG_PMCCNTR, ArmISA::MISCREG_PMCCNTR_EL0, ArmISA::MISCREG_PMCEID0, ArmISA::MISCREG_PMCEID0_EL0, ArmISA::MISCREG_PMCEID1, ArmISA::MISCREG_PMCEID1_EL0, ArmISA::MISCREG_PMCNTENCLR, ArmISA::MISCREG_PMCNTENCLR_EL0, ArmISA::MISCREG_PMCNTENSET, ArmISA::MISCREG_PMCNTENSET_EL0, ArmISA::MISCREG_PMCR, ArmISA::MISCREG_PMCR_EL0, ArmISA::MISCREG_PMEVCNTR0_EL0, ArmISA::MISCREG_PMEVTYPER0_EL0, ArmISA::MISCREG_PMINTENCLR, ArmISA::MISCREG_PMINTENCLR_EL1, ArmISA::MISCREG_PMINTENSET, ArmISA::MISCREG_PMINTENSET_EL1, ArmISA::MISCREG_PMOVSCLR_EL0, ArmISA::MISCREG_PMOVSR, ArmISA::MISCREG_PMOVSSET, ArmISA::MISCREG_PMOVSSET_EL0, ArmISA::MISCREG_PMSELR, ArmISA::MISCREG_PMSELR_EL0, ArmISA::MISCREG_PMSWINC, ArmISA::MISCREG_PMSWINC_EL0, ArmISA::MISCREG_PMUSERENR, ArmISA::MISCREG_PMUSERENR_EL0, ArmISA::MISCREG_PMXEVCNTR, ArmISA::MISCREG_PMXEVCNTR_EL0, ArmISA::MISCREG_PMXEVTYPER, ArmISA::MISCREG_PMXEVTYPER_EL0, ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, ArmISA::miscRegName, panic, PMCCNTR, reg_pmcnten, reg_pminten, reg_pmovsr, reg_pmselr, setControlReg(), setCounterTypeRegister(), setCounterValue(), ArmISA::unflattenMiscReg(), updateAllCounters(), X86ISA::val, ArmISA::PMU::CounterState::value, and warn.

void ArmISA::PMU::unserialize ( CheckpointIn &  cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 535 of file pmu.cc.

References clock_remainder, counters, csprintf(), cycleCounter, DPRINTF, ArmISA::i, reg_pmceid, reg_pmcnten, reg_pmcr, reg_pminten, reg_pmovsr, reg_pmselr, UNSERIALIZE_SCALAR, and Serializable::unserializeSection().

void ArmISA::PMU::updateAllCounters ( )

protected

Call updateCounter() for each counter in the PMU if the counter's state has changed.

See Also

updateCounter()

Definition at line 335 of file pmu.cc.

References counters, cycleCounter, X86ISA::enable, ArmISA::PMU::CounterState::enabled, ArmISA::i, PMCCNTR, reg_pmcnten, reg_pmcr, and updateCounter().

Referenced by drainResume(), setControlReg(), and setMiscReg().

void ArmISA::PMU::updateCounter ( CounterId  id, CounterState &  ctr  )

protected

Depending on counter configuration, add or remove the probes driving the counter.

Look at the state of a counter and (re-)attach the probes needed to drive a counter if it is currently active. All probes for the counter are detached if the counter is inactive.

Parameters

id	ID of counter within the PMU.
ctr	Reference to the counter's state

Definition at line 412 of file pmu.cc.

References ARCH_EVENT_SW_INCR, ArmISA::PMU::EventType::create(), DPRINTF, ArmISA::PMU::CounterState::enabled, MipsISA::et, ArmISA::PMU::CounterState::eventId, ArmISA::PMU::CounterState::listeners, SimObject::name(), ArmISA::PMU::EventType::name, ArmISA::PMU::EventType::obj, pmuEventTypes, and warn.

Referenced by setCounterTypeRegister(), and updateAllCounters().

Member Data Documentation

const EventTypeId ArmISA::PMU::ARCH_EVENT_SW_INCR = 0x00

staticprotected

ID of the software increment event.

Definition at line 187 of file pmu.hh.

Referenced by updateCounter().

Bitfield<2> ArmISA::PMU::c

protected

Definition at line 128 of file pmu.hh.

unsigned ArmISA::PMU::clock_remainder

protected

Remainder part when the clock counter is divided by 64.

Definition at line 468 of file pmu.hh.

Referenced by handleEvent(), serialize(), setControlReg(), and unserialize().

std::vector<CounterState> ArmISA::PMU::counters

protected

State of all general-purpose counters supported by PMU.

Definition at line 471 of file pmu.hh.

Referenced by getCounter(), isValidCounter(), resetEventCounts(), serialize(), setMiscReg(), unserialize(), and updateAllCounters().

CounterState ArmISA::PMU::cycleCounter

protected

State of the cycle counter.

Definition at line 473 of file pmu.hh.

Referenced by getCounter(), PMU(), readMiscRegInt(), serialize(), setControlReg(), setMiscReg(), unserialize(), and updateAllCounters().

Bitfield<3> ArmISA::PMU::d

protected

Definition at line 130 of file pmu.hh.

Bitfield<5> ArmISA::PMU::dp

protected

Definition at line 134 of file pmu.hh.

ArmISA::PMU::evtCount

protected

Definition at line 151 of file pmu.hh.

Bitfield<23, 16> ArmISA::PMU::idcode

protected

Definition at line 140 of file pmu.hh.

Bitfield<31, 24> ArmISA::PMU::imp

protected

Definition at line 142 of file pmu.hh.

Bitfield<6> ArmISA::PMU::lc

protected

Definition at line 136 of file pmu.hh.

Bitfield<26> ArmISA::PMU::m

protected

Definition at line 154 of file pmu.hh.

Bitfield<15, 11> ArmISA::PMU::n

protected

Definition at line 138 of file pmu.hh.

Bitfield<27> ArmISA::PMU::nsh

protected

Definition at line 156 of file pmu.hh.

Bitfield<29> ArmISA::PMU::nsk

protected

Definition at line 160 of file pmu.hh.

Bitfield<28> ArmISA::PMU::nsu

protected

Definition at line 158 of file pmu.hh.

Bitfield<1> ArmISA::PMU::p

protected

Definition at line 126 of file pmu.hh.

Bitfield<31> ArmISA::PMU::p

protected

Definition at line 164 of file pmu.hh.

Platform* const ArmISA::PMU::platform

protected

Platform this device belongs to.

Definition at line 484 of file pmu.hh.

Referenced by raiseInterrupt().

const CounterId ArmISA::PMU::PMCCNTR = 31

staticprotected

Cycle Count Register Number.

Definition at line 177 of file pmu.hh.

Referenced by getCounter(), handleEvent(), isValidCounter(), readMiscRegInt(), setCounterTypeRegister(), setMiscReg(), and updateAllCounters().

std::multimap<EventTypeId, EventType> ArmISA::PMU::pmuEventTypes

protected

Event types supported by this PMU.

Each event type ID can map to multiple EventType structures, which enables the PMU to use multiple probes for a single event. This can be useful in the following cases:

• Some events can are increment by multiple different probe points (e.g., the CPU memory access counter gets incremented for both loads and stores).

• A system switching between multiple CPU models can register events for all models that will execute a thread and tehreby ensure that the PMU continues to work.

Definition at line 502 of file pmu.hh.

Referenced by addEventProbe(), and updateCounter().

const unsigned int ArmISA::PMU::pmuInterrupt

protected

Performance monitor interrupt number.

Definition at line 482 of file pmu.hh.

Referenced by raiseInterrupt().

uint64_t ArmISA::PMU::reg_pmceid

protected

Performance counter ID register.

This register contains a bitmask of available architected counters.

Definition at line 465 of file pmu.hh.

Referenced by addEventProbe(), readMiscRegInt(), serialize(), and unserialize().

MiscReg ArmISA::PMU::reg_pmcnten

protected

Performance Monitor Count Enable Register.

Definition at line 445 of file pmu.hh.

Referenced by readMiscRegInt(), serialize(), setMiscReg(), unserialize(), and updateAllCounters().

PMCR_t ArmISA::PMU::reg_pmcr

protected

Performance Monitor Control Register.

Definition at line 448 of file pmu.hh.

Referenced by handleEvent(), readMiscRegInt(), serialize(), setControlReg(), unserialize(), and updateAllCounters().

PMCR_t ArmISA::PMU::reg_pmcr_conf

protected

Constant (configuration-dependent) part of the PMCR.

Definition at line 477 of file pmu.hh.

Referenced by PMU(), and readMiscRegInt().

const MiscReg ArmISA::PMU::reg_pmcr_wr_mask = 0x39

staticprotected

PMCR write mask when accessed from the guest.

Definition at line 479 of file pmu.hh.

Referenced by readMiscRegInt(), and setControlReg().

MiscReg ArmISA::PMU::reg_pminten

protected

Performance Monitor Interrupt Enable Register.

Definition at line 454 of file pmu.hh.

Referenced by handleEvent(), readMiscRegInt(), serialize(), setMiscReg(), and unserialize().

MiscReg ArmISA::PMU::reg_pmovsr

protected

Performance Monitor Overflow Status Register.

Definition at line 457 of file pmu.hh.

Referenced by handleEvent(), readMiscRegInt(), serialize(), setMiscReg(), and unserialize().

PMSELR_t ArmISA::PMU::reg_pmselr

protected

Performance Monitor Selection Register.

Definition at line 451 of file pmu.hh.

Referenced by readMiscRegInt(), serialize(), setCounterTypeRegister(), setMiscReg(), and unserialize().

ArmISA::PMU::sel

protected

Definition at line 147 of file pmu.hh.

Bitfield<30> ArmISA::PMU::u

protected

Definition at line 162 of file pmu.hh.

Bitfield<4> ArmISA::PMU::x

protected

Definition at line 132 of file pmu.hh.

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The documentation for this class was generated from the following files:

• arch/arm/pmu.hh
• arch/arm/pmu.cc