ArmISA::ISA Class Reference

Some registers alias with others, and therefore need to be translated. More...

#include <isa.hh>

Inheritance diagram for ArmISA::ISA:

Classes
struct	MiscRegInitializerEntry
struct	MiscRegLUTEntry
	Register translation entry used in lookUpMiscReg. More...

Public Types
typedef ArmISAParams	Params
Public Types inherited from SimObject
typedef SimObjectParams	Params

Public Member Functions
void	clear ()
void	clear64 (const ArmISAParams *p)
MiscReg	readMiscRegNoEffect (int misc_reg) const
MiscReg	readMiscReg (int misc_reg, ThreadContext *tc)
void	setMiscRegNoEffect (int misc_reg, const MiscReg &val)
void	setMiscReg (int misc_reg, const MiscReg &val, ThreadContext *tc)
int	flattenIntIndex (int reg) const
int	flattenFloatIndex (int reg) const
int	flattenCCIndex (int reg) const
int	flattenMiscIndex (int reg) const
std::pair< int, int >	getMiscIndices (int misc_reg) const
void	serialize (CheckpointOut &cp) const
	Serialize an object. More...
void	unserialize (CheckpointIn &cp)
	Unserialize an object. More...
void	startup (ThreadContext *tc)
Enums::DecoderFlavour	decoderFlavour () const
const Params *	params () const
	ISA (Params *p)
Public Member Functions inherited from SimObject
const Params *	params () const
	SimObject (const Params *_params)
virtual	~SimObject ()
virtual const std::string	name () const
virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...
virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...
virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...
virtual void	regStats ()
	Register statistics for this object. More...
virtual void	resetStats ()
	Reset statistics associated with this object. More...
virtual void	regProbePoints ()
	Register probe points for this object. More...
virtual void	regProbeListeners ()
	Register probe listeners for this object. More...
ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...
virtual void	startup ()
	startup() is the final initialization call before simulation. More...
DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...
virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...
virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...
void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...
void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...
Public Member Functions inherited from EventManager
	EventManager (EventManager &em)
	EventManager (EventManager *em)
	EventManager (EventQueue *eq)
EventQueue *	eventQueue () const
void	schedule (Event &event, Tick when)
void	deschedule (Event &event)
void	reschedule (Event &event, Tick when, bool always=false)
void	schedule (Event *event, Tick when)
void	deschedule (Event *event)
void	reschedule (Event *event, Tick when, bool always=false)
void	wakeupEventQueue (Tick when=(Tick)-1)
void	setCurTick (Tick newVal)
Public Member Functions inherited from Serializable
	Serializable ()
virtual	~Serializable ()
void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...
void	serializeSection (CheckpointOut &cp, const std::string &name) const
void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...
void	unserializeSection (CheckpointIn &cp, const std::string &name)
Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...
virtual void	notifyFork ()
	Notify a child process of a fork. More...

Protected Member Functions
void	updateRegMap (CPSR cpsr)
BaseISADevice &	getGenericTimer (ThreadContext *tc)
Protected Member Functions inherited from Drainable
	Drainable ()
virtual	~Drainable ()
virtual void	drainResume ()
	Resume execution after a successful drain. More...
void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Attributes
ArmSystem *	system
const Enums::DecoderFlavour	_decoderFlavour
DummyISADevice	dummyDevice
	Dummy device for to handle non-existing ISA devices. More...
BaseISADevice *	pmu
std::unique_ptr< BaseISADevice >	timer
bool	highestELIs64
bool	haveSecurity
bool	haveLPAE
bool	haveVirtualization
bool	haveLargeAsid64
uint8_t	physAddrRange64
std::vector< struct MiscRegLUTEntry >	lookUpMiscReg
	Translation table accessible via the value of the register. More...
MiscReg	miscRegs [NumMiscRegs]
const IntRegIndex *	intRegMap
Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...
Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Static Protected Attributes
static const struct MiscRegInitializerEntry	MiscRegSwitch []
	Register table noting all translations. More...

Private Member Functions
void	assert32 (ThreadContext *tc)
void	assert64 (ThreadContext *tc)
void	tlbiVA (ThreadContext *tc, MiscReg newVal, uint16_t asid, bool secure_lookup, uint8_t target_el)
void	tlbiALL (ThreadContext *tc, bool secure_lookup, uint8_t target_el)
void	tlbiALLN (ThreadContext *tc, bool hyp, uint8_t target_el)
void	tlbiMVA (ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, uint8_t target_el)

Additional Inherited Members
Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...
static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...
Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Get the fully-qualified name of the active section. More...
static void	serializeAll (const std::string &cpt_dir)
static void	unserializeGlobals (CheckpointIn &cp)
Static Public Attributes inherited from Serializable
static int	ckptCount = 0
static int	ckptMaxCount = 0
static int	ckptPrevCount = -1

Detailed Description

Some registers alias with others, and therefore need to be translated.

For each entry: The first value is the misc register that is to be looked up the second value is the lower part of the translation the third the upper part aligned with reference documentation ARM DDI 0487A.i pp 1540-1543

Definition at line 67 of file isa.cc.

Member Typedef Documentation

typedef ArmISAParams ArmISA::ISA::Params

Definition at line 396 of file isa.hh.

Constructor & Destructor Documentation

ArmISA::ISA::ISA

(

Params *

p

)

Definition at line 208 of file isa.cc.

Member Function Documentation

void ArmISA::ISA::assert32 ( ThreadContext *  tc )

inlineprivate

Definition at line 151 of file isa.hh.

References M5_VAR_USED, ArmISA::MISCREG_CPSR, and readMiscReg().

Referenced by setMiscReg().

void ArmISA::ISA::assert64 ( ThreadContext *  tc )

inlineprivate

Definition at line 156 of file isa.hh.

References M5_VAR_USED, ArmISA::MISCREG_CPSR, and readMiscReg().

Referenced by setMiscReg().

void ArmISA::ISA::clear

(

)

Definition at line 260 of file isa.cc.

References clear64(), FullSystem, haveLPAE, haveSecurity, ArmSystem::highestELIs64(), ArmISA::MISCREG_CPACR, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_FPSID, ArmISA::MISCREG_HCPTR, ArmISA::MISCREG_ID_ISAR0, ArmISA::MISCREG_ID_ISAR1, ArmISA::MISCREG_ID_ISAR2, ArmISA::MISCREG_ID_ISAR3, ArmISA::MISCREG_ID_ISAR4, ArmISA::MISCREG_ID_ISAR5, ArmISA::MISCREG_ID_MMFR0, ArmISA::MISCREG_ID_MMFR1, ArmISA::MISCREG_ID_MMFR2, ArmISA::MISCREG_ID_MMFR3, ArmISA::MISCREG_MIDR, ArmISA::MISCREG_MIDR_EL1, ArmISA::MISCREG_MVFR0, ArmISA::MISCREG_MVFR1, ArmISA::MISCREG_NMRR_NS, ArmISA::MISCREG_PRRR_NS, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCTLR_NS, ArmISA::MISCREG_SCTLR_RST, ArmISA::MISCREG_SCTLR_S, ArmISA::MISCREG_SEV_MAILBOX, ArmISA::MISCREG_TLBTR, ArmISA::MISCREG_TTBCR_NS, ArmISA::MISCREG_VBAR_S, ArmISA::MISCREG_VPIDR, miscRegs, ArmISA::MODE_USER, MipsISA::p, params(), system, and updateRegMap().

void ArmISA::ISA::clear64

(

const ArmISAParams *

p

)

Definition at line 397 of file isa.cc.

References ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::encodePhysAddrRange64(), haveLargeAsid64, haveSecurity, haveVirtualization, ArmSystem::highestEL(), insertBits(), ArmISA::MISCREG_CPSR, ArmISA::MISCREG_HSCTLR, ArmISA::MISCREG_ID_AA64AFR0_EL1, ArmISA::MISCREG_ID_AA64AFR1_EL1, ArmISA::MISCREG_ID_AA64DFR0_EL1, ArmISA::MISCREG_ID_AA64DFR1_EL1, ArmISA::MISCREG_ID_AA64ISAR0_EL1, ArmISA::MISCREG_ID_AA64ISAR1_EL1, ArmISA::MISCREG_ID_AA64MMFR0_EL1, ArmISA::MISCREG_ID_AA64MMFR1_EL1, ArmISA::MISCREG_ID_AA64PFR0_EL1, ArmISA::MISCREG_ID_DFR0, ArmISA::MISCREG_ID_DFR0_EL1, ArmISA::MISCREG_MPIDR_EL1, ArmISA::MISCREG_RVBAR_EL1, ArmISA::MISCREG_RVBAR_EL2, ArmISA::MISCREG_RVBAR_EL3, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SCTLR_EL3, ArmISA::MISCREG_SCTLR_NS, miscRegs, ArmISA::MODE_EL1H, ArmISA::MODE_EL2H, ArmISA::MODE_EL3H, panic, physAddrRange64, ArmSystem::resetAddr64(), system, ULL, and updateRegMap().

Referenced by clear().

Enums::DecoderFlavour ArmISA::ISA::decoderFlavour ( ) const

inline

Definition at line 391 of file isa.hh.

References _decoderFlavour.

int ArmISA::ISA::flattenCCIndex ( int  reg ) const

inline

Definition at line 220 of file isa.hh.

References X86ISA::reg.

int ArmISA::ISA::flattenFloatIndex ( int  reg ) const

inline

Definition at line 213 of file isa.hh.

References X86ISA::reg.

int ArmISA::ISA::flattenIntIndex ( int  reg ) const

inline

Definition at line 181 of file isa.hh.

References ArmISA::el, ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::flattenIntRegModeIndex(), ArmISA::INTREG_SP0, ArmISA::INTREG_SP1, ArmISA::INTREG_SP2, ArmISA::INTREG_SP3, ArmISA::INTREG_SPX, intRegMap, ArmISA::MISCREG_CPSR, miscRegs, ArmISA::NUM_ARCH_INTREGS, ArmISA::NUM_INTREGS, ArmISA::opModeToEL(), panic, and X86ISA::reg.

int ArmISA::ISA::flattenMiscIndex ( int  reg ) const

inline

Definition at line 227 of file isa.hh.

References haveSecurity, highestELIs64, ArmISA::inSecureState(), ArmISA::MISCREG_BANKED, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_MAIR0, ArmISA::MISCREG_MAIR1, ArmISA::MISCREG_MUTEX, ArmISA::MISCREG_NMRR, ArmISA::MISCREG_NMRR_MAIR1, ArmISA::MISCREG_NMRR_MAIR1_NS, ArmISA::MISCREG_NMRR_MAIR1_S, ArmISA::MISCREG_PMCCFILTR, ArmISA::MISCREG_PMSELR, ArmISA::MISCREG_PMXEVTYPER, ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, ArmISA::MISCREG_PRRR, ArmISA::MISCREG_PRRR_MAIR0, ArmISA::MISCREG_PRRR_MAIR0_NS, ArmISA::MISCREG_PRRR_MAIR0_S, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SPSR, ArmISA::MISCREG_SPSR_ABT, ArmISA::MISCREG_SPSR_EL1, ArmISA::MISCREG_SPSR_EL2, ArmISA::MISCREG_SPSR_EL3, ArmISA::MISCREG_SPSR_FIQ, ArmISA::MISCREG_SPSR_HYP, ArmISA::MISCREG_SPSR_IRQ, ArmISA::MISCREG_SPSR_MON, ArmISA::MISCREG_SPSR_SVC, ArmISA::MISCREG_SPSR_UND, ArmISA::MISCREG_TTBCR, ArmISA::miscRegInfo, miscRegs, ArmISA::MODE_ABORT, ArmISA::MODE_EL0T, ArmISA::MODE_EL1H, ArmISA::MODE_EL1T, ArmISA::MODE_EL2H, ArmISA::MODE_EL2T, ArmISA::MODE_EL3H, ArmISA::MODE_EL3T, ArmISA::MODE_FIQ, ArmISA::MODE_HYP, ArmISA::MODE_IRQ, ArmISA::MODE_MON, ArmISA::MODE_SVC, ArmISA::MODE_UNDEFINED, ArmISA::MODE_USER, panic, readMiscRegNoEffect(), X86ISA::reg, and warn.

Referenced by getMiscIndices().

BaseISADevice & ArmISA::ISA::getGenericTimer ( ThreadContext *  tc )

protected

Definition at line 1985 of file isa.cc.

References ThreadContext::contextId(), ArmSystem::getGenericTimer(), panic, system, and timer.

Referenced by readMiscReg(), and setMiscReg().

std::pair<int,int> ArmISA::ISA::getMiscIndices ( int  misc_reg ) const

inline

Definition at line 341 of file isa.hh.

References flattenMiscIndex(), haveSecurity, highestELIs64, ArmISA::inSecureState(), lookUpMiscReg, ArmISA::MISCREG_BANKED_CHILD, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_SCR, ArmISA::miscRegInfo, and miscRegs.

Referenced by readMiscRegNoEffect(), and setMiscRegNoEffect().

const ArmISAParams * ArmISA::ISA::params

(

)

const

Definition at line 254 of file isa.cc.

References SimObject::_params.

Referenced by clear().

MiscReg ArmISA::ISA::readMiscReg	(	int	misc_reg,
		ThreadContext *	tc
	)

Definition at line 495 of file isa.cc.

References System::cacheLineSize(), ArmISA::CCREG_C, ArmISA::CCREG_NZ, ArmISA::CCREG_V, ArmISA::daif, DPRINTF, ArmISA::FpscrExcMask, ArmISA::FpscrQcMask, ThreadContext::getCpuPtr(), getGenericTimer(), ArmSystem::getGenericTimer(), ArmISA::getMPIDR(), ThreadContext::getSystemPtr(), haveSecurity, haveVirtualization, ArmISA::inSecureState(), ArmISA::INTREG_SP0, ArmISA::INTREG_SP1, ArmISA::INTREG_SP2, ArmISA::mask, ArmISA::MISCREG_ACTLR, ArmISA::MISCREG_AIDR, ArmISA::MISCREG_CCSIDR, ArmISA::MISCREG_CLIDR, ArmISA::MISCREG_CNTFRQ, ArmISA::MISCREG_CNTHP_CTL, ArmISA::MISCREG_CNTHP_CVAL, ArmISA::MISCREG_CNTKCTL_EL1, ArmISA::MISCREG_CNTPCT, ArmISA::MISCREG_CNTPS_CVAL_EL1, ArmISA::MISCREG_CNTV_CVAL_EL0, ArmISA::MISCREG_CNTVOFF_EL2, ArmISA::MISCREG_CPACR, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_CPSR_Q, ArmISA::MISCREG_CTR, ArmISA::MISCREG_CTR_EL0, ArmISA::MISCREG_CURRENTEL, ArmISA::MISCREG_DAIF, ArmISA::MISCREG_DBGDIDR, ArmISA::MISCREG_DBGDSCRint, ArmISA::MISCREG_DCZID_EL0, ArmISA::MISCREG_DFAR_S, ArmISA::MISCREG_FPCR, ArmISA::MISCREG_FPSCR, ArmISA::MISCREG_FPSCR_EXC, ArmISA::MISCREG_FPSCR_QC, ArmISA::MISCREG_FPSR, ArmISA::MISCREG_HCPTR, ArmISA::MISCREG_HCR, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_HDFAR, ArmISA::MISCREG_HIFAR, ArmISA::MISCREG_HSCTLR, ArmISA::MISCREG_HVBAR, ArmISA::MISCREG_ID_AA64PFR0_EL1, ArmISA::MISCREG_ID_AA64PFR1_EL1, ArmISA::MISCREG_ID_AFR0, ArmISA::MISCREG_ID_PFR0, ArmISA::MISCREG_ID_PFR1, ArmISA::MISCREG_IFAR_S, ArmISA::MISCREG_IMPLEMENTED, ArmISA::MISCREG_ISR, ArmISA::MISCREG_ISR_EL1, ArmISA::MISCREG_JIDR, ArmISA::MISCREG_JMCR, ArmISA::MISCREG_JOSCR, ArmISA::MISCREG_L2CTLR, ArmISA::MISCREG_MIDR, ArmISA::MISCREG_MPIDR, ArmISA::MISCREG_MPIDR_EL1, ArmISA::MISCREG_NSACR, ArmISA::MISCREG_NZCV, ArmISA::MISCREG_PMCR, ArmISA::MISCREG_PMEVCNTR0_EL0, ArmISA::MISCREG_PMEVTYPER5_EL0, ArmISA::MISCREG_PMINTENSET_EL1, ArmISA::MISCREG_PMOVSSET, ArmISA::MISCREG_PMOVSSET_EL0, ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, ArmISA::MISCREG_REVIDR, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SCTLR, ArmISA::MISCREG_SCTLR_EL1, ArmISA::MISCREG_SCTLR_EL2, ArmISA::MISCREG_SCTLR_EL3, ArmISA::MISCREG_SP_EL0, ArmISA::MISCREG_SP_EL1, ArmISA::MISCREG_SP_EL2, ArmISA::MISCREG_SPSEL, ArmISA::MISCREG_TCMTR, ArmISA::MISCREG_VMPIDR, ArmISA::MISCREG_VPIDR, ArmISA::MISCREG_WARN_NOT_FAIL, ArmISA::miscRegInfo, ArmISA::miscRegName, miscRegs, ArmISA::MODE_HYP, ArmISA::MODE_MON, System::numContexts(), panic, pc, ThreadContext::pcState(), pmu, ThreadContext::readCCReg(), ThreadContext::readIntReg(), ArmISA::BaseISADevice::readMiscReg(), readMiscRegNoEffect(), system, ThreadContext::threadId(), ArmISA::unflattenMiscReg(), X86ISA::val, warn, and warn_once.

Referenced by assert32(), assert64(), and setMiscReg().

MiscReg ArmISA::ISA::readMiscRegNoEffect

(

int

misc_reg

)

const

Definition at line 483 of file isa.cc.

References getMiscIndices(), ArmISA::mask, miscRegs, and ArmISA::NumMiscRegs.

Referenced by flattenMiscIndex(), ArmISA::PMU::isFiltered(), readMiscReg(), and setMiscReg().

void ArmISA::ISA::serialize ( CheckpointOut &  cp ) const

inlinevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 362 of file isa.hh.

References DPRINTF, haveLargeAsid64, haveLPAE, haveSecurity, haveVirtualization, highestELIs64, miscRegs, ArmISA::NumMiscRegs, physAddrRange64, SERIALIZE_ARRAY, and SERIALIZE_SCALAR.

void ArmISA::ISA::setMiscReg	(	int	misc_reg,
		const MiscReg &	val,
		ThreadContext *	tc
	)

Definition at line 824 of file isa.cc.

References ArmISA::asid, assert32(), assert64(), ArmISA::attr, bits(), ArmISA::CCREG_C, ArmISA::CCREG_NZ, ArmISA::CCREG_V, ThreadContext::contextId(), ArmISA::CpsrMaskQ, ArmISA::daif, DPRINTF, ArmISA::el, ArmISA::FpscrExcMask, ArmISA::FpscrQcMask, Request::funcMasterId, ThreadContext::getCheckerCpuPtr(), ThreadContext::getDecoderPtr(), ThreadContext::getDTBPtr(), CheckerCPU::getDTBPtr(), ArmISA::ArmFault::getFsr(), getGenericTimer(), ThreadContext::getITBPtr(), CheckerCPU::getITBPtr(), Request::getPaddr(), ThreadContext::getSystemPtr(), System::getThreadContext(), haveLargeAsid64, haveLPAE, haveSecurity, haveVirtualization, ArmISA::TLB::HypMode, ArmISA::inSecureState(), ArmISA::INTREG_SP0, ArmISA::INTREG_SP1, ArmISA::INTREG_SP2, ArmISA::ArmFault::iss(), ArmISA::ArmFault::isStage2(), ArmISA::mask, mbits(), ArmISA::MISCREG_ACTLR, ArmISA::MISCREG_AMAIR0, ArmISA::MISCREG_AMAIR1, ArmISA::MISCREG_AT_S12E0R_Xt, ArmISA::MISCREG_AT_S12E0W_Xt, ArmISA::MISCREG_AT_S12E1R_Xt, ArmISA::MISCREG_AT_S12E1W_Xt, ArmISA::MISCREG_AT_S1E0R_Xt, ArmISA::MISCREG_AT_S1E0W_Xt, ArmISA::MISCREG_AT_S1E1R_Xt, ArmISA::MISCREG_AT_S1E1W_Xt, ArmISA::MISCREG_AT_S1E2R_Xt, ArmISA::MISCREG_AT_S1E2W_Xt, ArmISA::MISCREG_AT_S1E3R_Xt, ArmISA::MISCREG_AT_S1E3W_Xt, ArmISA::MISCREG_ATS12NSOPR, ArmISA::MISCREG_ATS12NSOPW, ArmISA::MISCREG_ATS12NSOUR, ArmISA::MISCREG_ATS12NSOUW, ArmISA::MISCREG_ATS1CPR, ArmISA::MISCREG_ATS1CPW, ArmISA::MISCREG_ATS1CUR, ArmISA::MISCREG_ATS1CUW, ArmISA::MISCREG_ATS1HR, ArmISA::MISCREG_ATS1HW, ArmISA::MISCREG_CNTFRQ, ArmISA::MISCREG_CNTHP_CTL, ArmISA::MISCREG_CNTHP_CVAL, ArmISA::MISCREG_CNTKCTL_EL1, ArmISA::MISCREG_CNTPCT, ArmISA::MISCREG_CNTPS_CVAL_EL1, ArmISA::MISCREG_CNTV_CVAL_EL0, ArmISA::MISCREG_CNTVOFF_EL2, ArmISA::MISCREG_CONTEXTIDR, ArmISA::MISCREG_CPACR, ArmISA::MISCREG_CPACR_EL1, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_CPSR_Q, ArmISA::MISCREG_CPTR_EL2, ArmISA::MISCREG_CPTR_EL3, ArmISA::MISCREG_CSSELR, ArmISA::MISCREG_CURRENTEL, ArmISA::MISCREG_DACR, ArmISA::MISCREG_DAIF, ArmISA::MISCREG_DC_ZVA_Xt, ArmISA::MISCREG_DFAR_S, ArmISA::MISCREG_DFSR, ArmISA::MISCREG_DTLBIALL, ArmISA::MISCREG_DTLBIASID, ArmISA::MISCREG_DTLBIMVA, ArmISA::MISCREG_FPCR, ArmISA::MISCREG_FPEXC, ArmISA::MISCREG_FPSCR, ArmISA::MISCREG_FPSCR_EXC, ArmISA::MISCREG_FPSCR_QC, ArmISA::MISCREG_FPSID, ArmISA::MISCREG_FPSR, ArmISA::MISCREG_HCPTR, ArmISA::MISCREG_HCR, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_HDFAR, ArmISA::MISCREG_HIFAR, ArmISA::MISCREG_HSCTLR, ArmISA::MISCREG_HSTR, ArmISA::MISCREG_ID_AA64AFR0_EL1, ArmISA::MISCREG_ID_AA64AFR1_EL1, ArmISA::MISCREG_ID_AA64DFR0_EL1, ArmISA::MISCREG_ID_AA64DFR1_EL1, ArmISA::MISCREG_ID_AA64ISAR0_EL1, ArmISA::MISCREG_ID_AA64ISAR1_EL1, ArmISA::MISCREG_ID_AA64MMFR0_EL1, ArmISA::MISCREG_ID_AA64MMFR1_EL1, ArmISA::MISCREG_ID_AA64PFR0_EL1, ArmISA::MISCREG_ID_AA64PFR1_EL1, ArmISA::MISCREG_ID_DFR0, ArmISA::MISCREG_ID_ISAR0, ArmISA::MISCREG_ID_ISAR1, ArmISA::MISCREG_ID_ISAR2, ArmISA::MISCREG_ID_ISAR3, ArmISA::MISCREG_ID_ISAR4, ArmISA::MISCREG_ID_ISAR5, ArmISA::MISCREG_ID_MMFR0, ArmISA::MISCREG_ID_MMFR1, ArmISA::MISCREG_ID_MMFR2, ArmISA::MISCREG_ID_MMFR3, ArmISA::MISCREG_ID_PFR0, ArmISA::MISCREG_ID_PFR1, ArmISA::MISCREG_IFAR_S, ArmISA::MISCREG_IFSR, ArmISA::MISCREG_IMPLEMENTED, ArmISA::MISCREG_ITLBIALL, ArmISA::MISCREG_ITLBIASID, ArmISA::MISCREG_ITLBIMVA, ArmISA::MISCREG_L2CTLR, ArmISA::MISCREG_MAIR0, ArmISA::MISCREG_MAIR1, ArmISA::MISCREG_MIDR, ArmISA::MISCREG_MPIDR, ArmISA::MISCREG_MVFR0, ArmISA::MISCREG_MVFR1, ArmISA::MISCREG_NMRR, ArmISA::MISCREG_NSACR, ArmISA::MISCREG_NZCV, ArmISA::MISCREG_PAR, ArmISA::MISCREG_PAR_EL1, ArmISA::MISCREG_PMCR, ArmISA::MISCREG_PMEVCNTR0_EL0, ArmISA::MISCREG_PMEVTYPER5_EL0, ArmISA::MISCREG_PMINTENSET_EL1, ArmISA::MISCREG_PMOVSSET, ArmISA::MISCREG_PMOVSSET_EL0, ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, ArmISA::MISCREG_PRRR, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SCTLR, ArmISA::MISCREG_SCTLR_EL1, ArmISA::MISCREG_SCTLR_EL2, ArmISA::MISCREG_SCTLR_EL3, ArmISA::MISCREG_SCTLR_NS, ArmISA::MISCREG_SCTLR_S, ArmISA::MISCREG_SP_EL0, ArmISA::MISCREG_SP_EL1, ArmISA::MISCREG_SP_EL2, ArmISA::MISCREG_SPSEL, ArmISA::MISCREG_SPSR_EL1, ArmISA::MISCREG_SPSR_EL2, ArmISA::MISCREG_SPSR_EL3, ArmISA::MISCREG_TCR_EL1, ArmISA::MISCREG_TCR_EL2, ArmISA::MISCREG_TCR_EL3, ArmISA::MISCREG_TLBI_ALLE1, ArmISA::MISCREG_TLBI_ALLE1IS, ArmISA::MISCREG_TLBI_ALLE3, ArmISA::MISCREG_TLBI_ALLE3IS, ArmISA::MISCREG_TLBI_ASIDE1_Xt, ArmISA::MISCREG_TLBI_ASIDE1IS_Xt, ArmISA::MISCREG_TLBI_IPAS2E1_Xt, ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt, ArmISA::MISCREG_TLBI_IPAS2LE1_Xt, ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt, ArmISA::MISCREG_TLBI_VAAE1_Xt, ArmISA::MISCREG_TLBI_VAAE1IS_Xt, ArmISA::MISCREG_TLBI_VAALE1_Xt, ArmISA::MISCREG_TLBI_VAALE1IS_Xt, ArmISA::MISCREG_TLBI_VAE1_Xt, ArmISA::MISCREG_TLBI_VAE1IS_Xt, ArmISA::MISCREG_TLBI_VAE2_Xt, ArmISA::MISCREG_TLBI_VAE2IS_Xt, ArmISA::MISCREG_TLBI_VAE3_Xt, ArmISA::MISCREG_TLBI_VAE3IS_Xt, ArmISA::MISCREG_TLBI_VALE1_Xt, ArmISA::MISCREG_TLBI_VALE1IS_Xt, ArmISA::MISCREG_TLBI_VALE2_Xt, ArmISA::MISCREG_TLBI_VALE2IS_Xt, ArmISA::MISCREG_TLBI_VALE3_Xt, ArmISA::MISCREG_TLBI_VALE3IS_Xt, ArmISA::MISCREG_TLBI_VMALLE1, ArmISA::MISCREG_TLBI_VMALLE1IS, ArmISA::MISCREG_TLBI_VMALLS12E1, ArmISA::MISCREG_TLBI_VMALLS12E1IS, ArmISA::MISCREG_TLBIALL, ArmISA::MISCREG_TLBIALLH, ArmISA::MISCREG_TLBIALLHIS, ArmISA::MISCREG_TLBIALLIS, ArmISA::MISCREG_TLBIALLNSNH, ArmISA::MISCREG_TLBIALLNSNHIS, ArmISA::MISCREG_TLBIASID, ArmISA::MISCREG_TLBIASIDIS, ArmISA::MISCREG_TLBIMVA, ArmISA::MISCREG_TLBIMVAA, ArmISA::MISCREG_TLBIMVAAIS, ArmISA::MISCREG_TLBIMVAH, ArmISA::MISCREG_TLBIMVAHIS, ArmISA::MISCREG_TLBIMVAIS, ArmISA::MISCREG_TLBTR, ArmISA::MISCREG_TTBCR, ArmISA::MISCREG_TTBR0, ArmISA::MISCREG_TTBR0_EL1, ArmISA::MISCREG_TTBR0_EL2, ArmISA::MISCREG_TTBR0_EL3, ArmISA::MISCREG_TTBR1, ArmISA::MISCREG_TTBR1_EL1, ArmISA::MISCREG_VTTBR, ArmISA::MISCREG_WARN_NOT_FAIL, ArmISA::miscRegInfo, ArmISA::miscRegName, miscRegs, ArmISA::mode, ArmISA::MODE_MON, ArmISA::TLB::MustBeOne, NoFault, ArmISA::TLB::NormalTran, System::numContexts(), panic, pc, ThreadContext::pcState(), ThreadContext::pcStateNoRecord(), pmu, BaseTLB::Read, readMiscReg(), ThreadContext::readMiscReg(), readMiscRegNoEffect(), ArmISA::TLB::S12E0Tran, ArmISA::TLB::S12E1Tran, ArmISA::TLB::S1CTran, ArmISA::TLB::S1E0Tran, ArmISA::TLB::S1E1Tran, ArmISA::TLB::S1E2Tran, ArmISA::TLB::S1E3Tran, ArmISA::TLB::S1S2NsTran, ThreadContext::setCCReg(), Request::setContext(), ThreadContext::setIntReg(), ArmISA::BaseISADevice::setMiscReg(), setMiscRegNoEffect(), Request::setVirt(), ArmISA::sp, tlbiALL(), tlbiALLN(), tlbiMVA(), tlbiVA(), ArmISA::unflattenMiscReg(), updateRegMap(), ArmISA::TLB::UserMode, ArmISA::va, X86ISA::val, warn, warn_once, BaseTLB::Write, and X86ISA::x.

void ArmISA::ISA::setMiscRegNoEffect	(	int	misc_reg,
		const MiscReg &	val
	)

Definition at line 805 of file isa.cc.

References bits(), DPRINTF, getMiscIndices(), miscRegs, ArmISA::NumMiscRegs, and X86ISA::val.

Referenced by setMiscReg().

void ArmISA::ISA::startup ( ThreadContext *  tc )

inline

Definition at line 389 of file isa.hh.

void ArmISA::ISA::tlbiALL ( ThreadContext *  tc, bool  secure_lookup, uint8_t  target_el  )

private

Definition at line 1923 of file isa.cc.

References ThreadContext::getCheckerCpuPtr(), ThreadContext::getDTBPtr(), CheckerCPU::getDTBPtr(), ThreadContext::getITBPtr(), CheckerCPU::getITBPtr(), ThreadContext::getSystemPtr(), System::getThreadContext(), System::numContexts(), and X86ISA::x.

Referenced by setMiscReg().

void ArmISA::ISA::tlbiALLN ( ThreadContext *  tc, bool  hyp, uint8_t  target_el  )

private

Definition at line 1944 of file isa.cc.

References ThreadContext::getCheckerCpuPtr(), ThreadContext::getDTBPtr(), CheckerCPU::getDTBPtr(), ThreadContext::getITBPtr(), CheckerCPU::getITBPtr(), ThreadContext::getSystemPtr(), System::getThreadContext(), System::numContexts(), and X86ISA::x.

Referenced by setMiscReg().

void ArmISA::ISA::tlbiMVA ( ThreadContext *  tc, MiscReg  newVal, bool  secure_lookup, bool  hyp, uint8_t  target_el  )

private

Definition at line 1962 of file isa.cc.

References ThreadContext::getCheckerCpuPtr(), ThreadContext::getDTBPtr(), CheckerCPU::getDTBPtr(), ThreadContext::getITBPtr(), CheckerCPU::getITBPtr(), ThreadContext::getSystemPtr(), System::getThreadContext(), mbits(), System::numContexts(), and X86ISA::x.

Referenced by setMiscReg().

void ArmISA::ISA::tlbiVA ( ThreadContext *  tc, MiscReg  newVal, uint16_t  asid, bool  secure_lookup, uint8_t  target_el  )

private

Definition at line 1897 of file isa.cc.

References bits(), ThreadContext::getCheckerCpuPtr(), ThreadContext::getDTBPtr(), CheckerCPU::getDTBPtr(), ThreadContext::getITBPtr(), CheckerCPU::getITBPtr(), ThreadContext::getSystemPtr(), System::getThreadContext(), haveLargeAsid64, ArmISA::mask, System::numContexts(), ArmISA::va, and X86ISA::x.

Referenced by setMiscReg().

void ArmISA::ISA::unserialize ( CheckpointIn &  cp )

inlinevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 374 of file isa.hh.

References DPRINTF, haveLargeAsid64, haveLPAE, haveSecurity, haveVirtualization, highestELIs64, ArmISA::MISCREG_CPSR, miscRegs, ArmISA::NumMiscRegs, physAddrRange64, UNSERIALIZE_ARRAY, UNSERIALIZE_SCALAR, and updateRegMap().

void ArmISA::ISA::updateRegMap ( CPSR  cpsr )

inlineprotected

Definition at line 110 of file isa.hh.

References ArmISA::IntReg64Map, ArmISA::IntRegAbtMap, ArmISA::IntRegFiqMap, ArmISA::IntRegHypMap, ArmISA::IntRegIrqMap, intRegMap, ArmISA::IntRegMonMap, ArmISA::IntRegSvcMap, ArmISA::IntRegUndMap, ArmISA::IntRegUsrMap, ArmISA::MODE_ABORT, ArmISA::MODE_FIQ, ArmISA::MODE_HYP, ArmISA::MODE_IRQ, ArmISA::MODE_MON, ArmISA::MODE_SVC, ArmISA::MODE_SYSTEM, ArmISA::MODE_UNDEFINED, ArmISA::MODE_USER, and panic.

Referenced by clear(), clear64(), setMiscReg(), and unserialize().

Member Data Documentation

const Enums::DecoderFlavour ArmISA::ISA::_decoderFlavour

protected

Definition at line 70 of file isa.hh.

Referenced by decoderFlavour().

DummyISADevice ArmISA::ISA::dummyDevice

protected

Dummy device for to handle non-existing ISA devices.

Definition at line 73 of file isa.hh.

bool ArmISA::ISA::haveLargeAsid64

protected

Definition at line 86 of file isa.hh.

Referenced by clear64(), serialize(), setMiscReg(), tlbiVA(), and unserialize().

bool ArmISA::ISA::haveLPAE

protected

Definition at line 84 of file isa.hh.

Referenced by clear(), serialize(), setMiscReg(), and unserialize().

bool ArmISA::ISA::haveSecurity

protected

Definition at line 83 of file isa.hh.

Referenced by clear(), clear64(), flattenMiscIndex(), getMiscIndices(), readMiscReg(), serialize(), setMiscReg(), and unserialize().

bool ArmISA::ISA::haveVirtualization

protected

Definition at line 85 of file isa.hh.

Referenced by clear64(), readMiscReg(), serialize(), setMiscReg(), and unserialize().

bool ArmISA::ISA::highestELIs64

protected

Definition at line 82 of file isa.hh.

Referenced by flattenMiscIndex(), getMiscIndices(), serialize(), and unserialize().

const IntRegIndex* ArmISA::ISA::intRegMap

protected

Definition at line 107 of file isa.hh.

Referenced by flattenIntIndex(), and updateRegMap().

std::vector<struct MiscRegLUTEntry> ArmISA::ISA::lookUpMiscReg

protected

Translation table accessible via the value of the register.

Definition at line 104 of file isa.hh.

Referenced by getMiscIndices().

MiscReg ArmISA::ISA::miscRegs[NumMiscRegs]

protected

Definition at line 106 of file isa.hh.

Referenced by clear(), clear64(), flattenIntIndex(), flattenMiscIndex(), getMiscIndices(), readMiscReg(), readMiscRegNoEffect(), serialize(), setMiscReg(), setMiscRegNoEffect(), and unserialize().

const struct MiscRegInitializerEntry ArmISA::ISA::MiscRegSwitch[]

staticprotected

Register table noting all translations.

Definition at line 101 of file isa.hh.

uint8_t ArmISA::ISA::physAddrRange64

protected

Definition at line 87 of file isa.hh.

Referenced by clear64(), serialize(), and unserialize().

BaseISADevice* ArmISA::ISA::pmu

protected

Definition at line 76 of file isa.hh.

Referenced by readMiscReg(), and setMiscReg().

ArmSystem* ArmISA::ISA::system

protected

Definition at line 67 of file isa.hh.

Referenced by clear(), clear64(), getGenericTimer(), and readMiscReg().

std::unique_ptr<BaseISADevice> ArmISA::ISA::timer

protected

Definition at line 79 of file isa.hh.

Referenced by getGenericTimer().

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The documentation for this class was generated from the following files:

• arch/arm/isa.cc
• arch/arm/isa.hh