pmu.hh

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/*
 * Copyright (c) 2011-2014 ARM Limited
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 * to a hardware implementation of the functionality of the software
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 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
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 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Dam Sunwoo
 *          Matt Horsnell
 *          Andreas Sandberg
 */
#ifndef __ARCH_ARM_PMU_HH__
#define __ARCH_ARM_PMU_HH__

#include <map>
#include <memory>
#include <vector>

#include "arch/arm/isa_device.hh"
#include "arch/arm/registers.hh"
#include "sim/probe/probe.hh"
#include "sim/sim_object.hh"

class ArmPMUParams;
class Platform;
class ThreadContext;

namespace ArmISA {


class PMU : public SimObject, public ArmISA::BaseISADevice {
  public:
    PMU(const ArmPMUParams *p);
    ~PMU();

    void addEventProbe(unsigned int id, SimObject *obj, const char *name);

  public: // SimObject and related interfaces
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;

    void drainResume() override;


  public: // ISA Device interface
    void setMiscReg(int misc_reg, MiscReg val) override;
    MiscReg readMiscReg(int misc_reg) override;

  protected: // PMU register types and constants
    BitUnion32(PMCR_t)
        // PMU Enable
        Bitfield<0> e;
        // Event counter reset
        Bitfield<1> p;
        // Cycle counter reset
        Bitfield<2> c;
        // Cycle counter divider enable
        Bitfield<3> d;
        // Export enable
        Bitfield<4> x;
        // Disable PMCCNTR when event counting is prohibited
        Bitfield<5> dp;
        // Long Cycle counter enable
        Bitfield<6> lc;
        // Number of event counters implemented
        Bitfield<15, 11> n;
        // Implementation ID
        Bitfield<23, 16> idcode;
        // Implementer code
        Bitfield<31, 24> imp;
    EndBitUnion(PMCR_t)

    BitUnion32(PMSELR_t)
        // Performance counter selector
        Bitfield<4, 0> sel;
    EndBitUnion(PMSELR_t)

    BitUnion32(PMEVTYPER_t)
        Bitfield<9, 0> evtCount;

        // Secure EL3 filtering
        Bitfield<26> m;
        // Non-secure EL2 mode filtering
        Bitfield<27> nsh;
        // Non-secure EL0 mode filtering
        Bitfield<28> nsu;
        // Non-secure EL1 mode filtering
        Bitfield<29> nsk;
        // EL0 filtering
        Bitfield<30> u;
        // EL1 filtering
        Bitfield<31> p;
    EndBitUnion(PMEVTYPER_t)

    typedef unsigned int CounterId;

    static const CounterId PMCCNTR = 31;

    typedef unsigned int EventTypeId;

    static const EventTypeId ARCH_EVENT_SW_INCR = 0x00;

  protected: /* High-level register and interrupt handling */
    MiscReg readMiscRegInt(int misc_reg);

    void setControlReg(PMCR_t val);

    void resetEventCounts();

    void raiseInterrupt();

    uint64_t getCounterValue(CounterId id) const {
        return isValidCounter(id) ? getCounter(id).value : 0;
    }

    void setCounterValue(CounterId id, uint64_t val);

    PMEVTYPER_t getCounterTypeRegister(CounterId id) const;

    void setCounterTypeRegister(CounterId id, PMEVTYPER_t type);

  protected: /* Probe handling and counter state */
    class ProbeListener : public ProbeListenerArgBase<uint64_t>
    {
      public:
        ProbeListener(PMU &_pmu, CounterId _id,
                      ProbeManager *pm, const std::string &name)
            : ProbeListenerArgBase(pm, name),
              pmu(_pmu), id(_id) {}

        void notify(const uint64_t &val) override
        {
            pmu.handleEvent(id, val);
        }

      protected:
        PMU &pmu;
        const CounterId id;
    };
    typedef std::unique_ptr<ProbeListener> ProbeListenerUPtr;

    struct EventType {
        EventType(SimObject *_obj, const std::string &_name)
            : obj(_obj), name(_name) {}

        std::unique_ptr<ProbeListener> create(PMU &pmu, CounterId cid) const
        {
            std::unique_ptr<ProbeListener> ptr;
            ptr.reset(new ProbeListener(pmu, cid,
                                        obj->getProbeManager(), name));
            return ptr;
        }

        SimObject *const obj;
        const std::string name;

      private:
        // Disable the default constructor
        EventType();
    };

    struct CounterState : public Serializable {
        CounterState()
            : eventId(0), filter(0), value(0), enabled(false),
              overflow64(false) {

            listeners.reserve(4);
        }

        void serialize(CheckpointOut &cp) const override;
        void unserialize(CheckpointIn &cp)  override;

        bool add(uint64_t delta);

      public: /* Serializable state */
        EventTypeId eventId;

        PMEVTYPER_t filter;

        uint64_t value;

        bool enabled;

        bool overflow64;

      public: /* Configuration */
        std::vector<ProbeListenerUPtr> listeners;
    };

    void handleEvent(CounterId id, uint64_t delta);

    bool isValidCounter(CounterId id) const {
        return id < counters.size() || id == PMCCNTR;
    }

    CounterState &getCounter(CounterId id) {
        assert(isValidCounter(id));
        return id == PMCCNTR ? cycleCounter : counters[id];
    }


    const CounterState &getCounter(CounterId id) const {
        assert(isValidCounter(id));
        return id == PMCCNTR ? cycleCounter : counters[id];
    }

    void updateCounter(CounterId id, CounterState &ctr);

    bool isFiltered(const CounterState &ctr) const;

    void updateAllCounters();

  protected: /* State that needs to be serialized */
    MiscReg reg_pmcnten;

    PMCR_t reg_pmcr;

    PMSELR_t reg_pmselr;

    MiscReg reg_pminten;

    MiscReg reg_pmovsr;

    uint64_t reg_pmceid;

    unsigned clock_remainder;

    std::vector<CounterState> counters;
    CounterState cycleCounter;

  protected: /* Configuration and constants */
    PMCR_t reg_pmcr_conf;
    static const MiscReg reg_pmcr_wr_mask;

    const unsigned int pmuInterrupt;
    Platform *const platform;

    std::multimap<EventTypeId, EventType> pmuEventTypes;
};

} // namespace ArmISA
#endif