SparcISA Namespace Reference

Namespaces
	Kernel

Classes
class	Decoder
class	SparcFaultBase
class	SparcFault
class	PowerOnReset
class	WatchDogReset
class	ExternallyInitiatedReset
class	SoftwareInitiatedReset
class	REDStateException
class	StoreError
class	InstructionAccessException
class	InstructionAccessError
class	IllegalInstruction
class	PrivilegedOpcode
class	FpDisabled
class	FpExceptionIEEE754
class	FpExceptionOther
class	TagOverflow
class	CleanWindow
class	DivisionByZero
class	InternalProcessorError
class	InstructionInvalidTSBEntry
class	DataInvalidTSBEntry
class	DataAccessException
class	DataAccessError
class	DataAccessProtection
class	MemAddressNotAligned
class	LDDFMemAddressNotAligned
class	STDFMemAddressNotAligned
class	PrivilegedAction
class	LDQFMemAddressNotAligned
class	STQFMemAddressNotAligned
class	InstructionRealTranslationMiss
class	DataRealTranslationMiss
class	EnumeratedFault
class	InterruptLevelN
class	HstickMatch
class	TrapLevelZero
class	InterruptVector
class	PAWatchpoint
class	VAWatchpoint
class	FastInstructionAccessMMUMiss
class	FastDataAccessMMUMiss
class	FastDataAccessProtection
class	InstructionBreakpoint
class	CpuMondo
class	DevMondo
class	ResumableError
class	SpillNNormal
class	SpillNOther
class	FillNNormal
class	FillNOther
class	TrapInstruction
class	Interrupts
class	ISA
class	SparcLinuxProcess
class	Sparc32LinuxProcess
	A process with emulated SPARC/Linux syscalls. More...
class	Sparc64LinuxProcess
	A process with emulated 32 bit SPARC/Linux syscalls. More...
struct	VAddr
class	TteTag
class	PageTableEntry
struct	TlbRange
struct	TlbEntry
union	AnyReg
class	RemoteGDB
class	SparcSolarisProcess
	A process with emulated SPARC/Solaris syscalls. More...
class	StackTrace
class	TLB
class	TlbMap

Typedefs
typedef uint32_t	TrapType
typedef uint32_t	FaultPriority
typedef uint64_t	IntReg
typedef uint64_t	MiscReg
typedef float	FloatReg
typedef uint32_t	FloatRegBits
typedef uint8_t	CCReg
typedef uint16_t	RegIndex
typedef uint32_t	MachInst
typedef uint64_t	ExtMachInst
typedef GenericISA::DelaySlotUPCState < MachInst >	PCState

Enumerations
enum	ASI {   ASI_IMPLICIT = 0x00, ASI_NUCLEUS = 0x4, ASI_N = 0x4, ASI_NL = 0xC,   ASI_NUCLEUS_LITTLE = ASI_NL, ASI_AIUP = 0x10, ASI_AS_IF_USER_PRIMARY = ASI_AIUP, ASI_AIUS = 0x11,   ASI_AS_IF_USER_SECONDARY = ASI_AIUS, ASI_REAL = 0x14, ASI_REAL_IO = 0x15, ASI_BLK_AIUP = 0x16,   ASI_BLOCK_AS_IF_USER_PRIMARY = ASI_BLK_AIUP, ASI_BLK_AIUS = 0x17, ASI_BLOCK_AS_IF_USER_SECONDARY = ASI_BLK_AIUS, ASI_AIUP_L = 0x18,   ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUP_L, ASI_AIUS_L = 0x19, ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUS_L, ASI_REAL_L = 0x1C,   ASI_REAL_LITTLE = ASI_REAL_L, ASI_REAL_IO_L = 0x1D, ASI_REAL_IO_LITTLE = ASI_REAL_IO_L, ASI_BLK_AIUP_L = 0x1E,   ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUP_L, ASI_BLK_AIUS_L = 0x1F, ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUS_L, ASI_SCRATCHPAD = 0x20,   ASI_MMU = 0x21, ASI_LDTX_AIUP = 0x22, ASI_LD_TWINX_AS_IF_USER_PRIMARY = ASI_LDTX_AIUP, ASI_LDTX_AIUS = 0x23,   ASI_LD_TWINX_AS_IF_USER_SECONDARY = ASI_LDTX_AIUS, ASI_QUAD_LDD = 0x24, ASI_QUEUE = 0x25, ASI_QUAD_LDD_REAL = 0x26,   ASI_LDTX_REAL = ASI_QUAD_LDD_REAL, ASI_LDTX_N = 0x27, ASI_LD_TWINX_NUCLEUS = ASI_LDTX_N, ASI_ST_BLKINIT_NUCLEUS = ASI_LDTX_N,   ASI_STBI_N = ASI_LDTX_N, ASI_LDTX_AIUP_L = 0x2A, ASI_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L, ASI_ST_BLKINIT_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,   ASI_STBI_AIUP_L = ASI_LDTX_AIUP_L, ASI_LDTX_AIUS_L = 0x2B, ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L, ASI_ST_BLKINIT_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,   ASI_STBI_AIUS_L = ASI_LDTX_AIUS_L, ASI_LTX_L = 0x2C, ASI_TWINX_LITTLE = ASI_LTX_L, ASI_LDTX_REAL_L = 0x2E,   ASI_LD_TWINX_REAL_LITTLE = ASI_LDTX_REAL_L, ASI_LDTX_NL = 0x2F, ASI_LD_TWINX_NUCLEUS_LITTLE = ASI_LDTX_NL, ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x31,   ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x32, ASI_DMMU_CTXT_ZERO_CONFIG = 0x33, ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x35, ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x36,   ASI_IMMU_CTXT_ZERO_CONFIG = 0x37, ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x39, ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3A, ASI_DMMU_CTXT_NONZERO_CONFIG = 0x3B,   ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x3D, ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3E, ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F, ASI_STREAM_MA = 0x40,   ASI_CMT_SHARED = 0x41, ASI_SPARC_BIST_CONTROL = 0x42, ASI_INST_MASK_REG = 0x42, ASI_LSU_DIAG_REG = 0x42,   ASI_STM_CTL_REG = 0x44, ASI_LSU_CONTROL_REG = 0x45, ASI_DCACHE_DATA = 0x46, ASI_DCACHE_TAG = 0x47,   ASI_INTR_DISPATCH_STATUS = 0x48, ASI_INTR_RECEIVE = 0x49, ASI_UPA_CONFIG_REGISTER = 0x4A, ASI_SPARC_ERROR_EN_REG = 0x4B,   ASI_SPARC_ERROR_STATUS_REG = 0x4C, ASI_SPARC_ERROR_ADDRESS_REG = 0x4D, ASI_ECACHE_TAG_DATA = 0x4E, ASI_HYP_SCRATCHPAD = 0x4F,   ASI_IMMU = 0x50, ASI_IMMU_TSB_PS0_PTR_REG = 0x51, ASI_IMMU_TSB_PS1_PTR_REG = 0x52, ASI_ITLB_DATA_IN_REG = 0x54,   ASI_ITLB_DATA_ACCESS_REG = 0x55, ASI_ITLB_TAG_READ_REG = 0x56, ASI_IMMU_DEMAP = 0x57, ASI_DMMU = 0x58,   ASI_DMMU_TSB_PS0_PTR_REG = 0x59, ASI_DMMU_TSB_PS1_PTR_REG = 0x5A, ASI_DMMU_TSB_DIRECT_PTR_REG = 0x5B, ASI_DTLB_DATA_IN_REG = 0x5C,   ASI_DTLB_DATA_ACCESS_REG = 0x5D, ASI_DTLB_TAG_READ_REG = 0x5E, ASI_DMMU_DEMAP = 0x5F, ASI_TLB_INVALIDATE_ALL = 0x60,   ASI_CMT_PER_STRAND = 0x63, ASI_ICACHE_INSTR = 0x66, ASI_ICACHE_TAG = 0x67, ASI_SWVR_INTR_RECEIVE = 0x72,   ASI_SWVR_UDB_INTR_W = 0x73, ASI_SWVR_UDB_INTR_R = 0x74, ASI_P = 0x80, ASI_PRIMARY = ASI_P,   ASI_S = 0x81, ASI_SECONDARY = ASI_S, ASI_PNF = 0x82, ASI_PRIMARY_NO_FAULT = ASI_PNF,   ASI_SNF = 0x83, ASI_SECONDARY_NO_FAULT = ASI_SNF, ASI_PL = 0x88, ASI_PRIMARY_LITTLE = ASI_PL,   ASI_SL = 0x89, ASI_SECONDARY_LITTLE = ASI_SL, ASI_PNFL = 0x8A, ASI_PRIMARY_NO_FAULT_LITTLE = ASI_PNFL,   ASI_SNFL = 0x8B, ASI_SECONDARY_NO_FAULT_LITTLE = ASI_SNFL, ASI_PST8_P = 0xC0, ASI_PST8_PRIMARY = ASI_PST8_P,   ASI_PST8_S = 0xC1, ASI_PST8_SECONDARY = ASI_PST8_S, ASI_PST16_P = 0xC2, ASI_PST16_PRIMARY = ASI_PST16_P,   ASI_PST16_S = 0xC3, ASI_PST16_SECONDARY = ASI_PST16_S, ASI_PST32_P = 0xC4, ASI_PST32_PRIMARY = ASI_PST32_P,   ASI_PST32_S = 0xC5, ASI_PST32_SECONDARY = ASI_PST32_S, ASI_PST8_PL = 0xC8, ASI_PST8_PRIMARY_LITTLE = ASI_PST8_PL,   ASI_PST8_SL = 0xC9, ASI_PST8_SECONDARY_LITTLE = ASI_PST8_SL, ASI_PST16_PL = 0xCA, ASI_PST16_PRIMARY_LITTLE = ASI_PST16_PL,   ASI_PST16_SL = 0xCB, ASI_PST16_SECONDARY_LITTLE = ASI_PST16_SL, ASI_PST32_PL = 0xCC, ASI_PST32_PRIMARY_LITTLE = ASI_PST32_PL,   ASI_PST32_SL = 0xCD, ASI_PST32_SECONDARY_LITTLE = ASI_PST32_SL, ASI_FL8_P = 0xD0, ASI_FL8_PRIMARY = ASI_FL8_P,   ASI_FL8_S = 0xD1, ASI_FL8_SECONDARY = ASI_FL8_S, ASI_FL16_P = 0xD2, ASI_FL16_PRIMARY = ASI_FL16_P,   ASI_FL16_S = 0xD3, ASI_FL16_SECONDARY = ASI_FL16_S, ASI_FL8_PL = 0xD8, ASI_FL8_PRIMARY_LITTLE = ASI_FL8_PL,   ASI_FL8_SL = 0xD9, ASI_FL8_SECONDARY_LITTLE = ASI_FL8_SL, ASI_FL16_PL = 0xDA, ASI_FL16_PRIMARY_LITTLE = ASI_FL16_PL,   ASI_FL16_SL = 0xDB, ASI_FL16_SECONDARY_LITTLE = ASI_FL16_SL, ASI_LDTX_P = 0xE2, ASI_LD_TWINX_PRIMARY = ASI_LDTX_P,   ASI_LDTX_S = 0xE3, ASI_LD_TWINX_SECONDARY = ASI_LDTX_S, ASI_LDTX_PL = 0xEA, ASI_LD_TWINX_PRIMARY_LITTLE = ASI_LDTX_PL,   ASI_LDTX_SL = 0xEB, ASI_LD_TWINX_SECONDARY_LITTLE = ASI_LDTX_SL, ASI_BLK_P = 0xF0, ASI_BLOCK_PRIMARY = ASI_BLK_P,   ASI_BLK_S = 0xF1, ASI_BLOCK_SECONDARY = ASI_BLK_S, ASI_BLK_PL = 0xF8, ASI_BLOCK_PRIMARY_LITTLE = ASI_BLK_PL,   ASI_BLK_SL = 0xF9, ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL, MAX_ASI = 0xFF }
enum	InterruptTypes {   IT_TRAP_LEVEL_ZERO, IT_HINTP, IT_INT_VEC, IT_CPU_MONDO,   IT_DEV_MONDO, IT_RES_ERROR, IT_SOFT_INT, NumInterruptTypes }
enum	MiscRegIndex {   MISCREG_ASI, MISCREG_TICK, MISCREG_FPRS, MISCREG_PCR,   MISCREG_PIC, MISCREG_GSR, MISCREG_SOFTINT_SET, MISCREG_SOFTINT_CLR,   MISCREG_SOFTINT, MISCREG_TICK_CMPR, MISCREG_STICK, MISCREG_STICK_CMPR,   MISCREG_TPC, MISCREG_TNPC, MISCREG_TSTATE, MISCREG_TT,   MISCREG_PRIVTICK, MISCREG_TBA, MISCREG_PSTATE, MISCREG_TL,   MISCREG_PIL, MISCREG_CWP, MISCREG_GL, MISCREG_HPSTATE,   MISCREG_HTSTATE, MISCREG_HINTP, MISCREG_HTBA, MISCREG_HVER,   MISCREG_STRAND_STS_REG, MISCREG_HSTICK_CMPR, MISCREG_FSR, MISCREG_MMU_P_CONTEXT,   MISCREG_MMU_S_CONTEXT, MISCREG_MMU_PART_ID, MISCREG_MMU_LSU_CTRL, MISCREG_SCRATCHPAD_R0,   MISCREG_SCRATCHPAD_R1, MISCREG_SCRATCHPAD_R2, MISCREG_SCRATCHPAD_R3, MISCREG_SCRATCHPAD_R4,   MISCREG_SCRATCHPAD_R5, MISCREG_SCRATCHPAD_R6, MISCREG_SCRATCHPAD_R7, MISCREG_QUEUE_CPU_MONDO_HEAD,   MISCREG_QUEUE_CPU_MONDO_TAIL, MISCREG_QUEUE_DEV_MONDO_HEAD, MISCREG_QUEUE_DEV_MONDO_TAIL, MISCREG_QUEUE_RES_ERROR_HEAD,   MISCREG_QUEUE_RES_ERROR_TAIL, MISCREG_QUEUE_NRES_ERROR_HEAD, MISCREG_QUEUE_NRES_ERROR_TAIL, MISCREG_TLB_DATA,   MISCREG_NUMMISCREGS }
enum	DependenceTags { FP_Reg_Base = NumIntRegs, CC_Reg_Base = FP_Reg_Base + NumFloatRegs, Misc_Reg_Base = CC_Reg_Base + NumCCRegs, Max_Reg_Index = Misc_Reg_Base + NumMiscRegs }

Functions
bool	asiIsBlock (ASI asi)
bool	asiIsPrimary (ASI asi)
bool	asiIsSecondary (ASI asi)
bool	asiIsNucleus (ASI asi)
bool	asiIsAsIfUser (ASI asi)
bool	asiIsIO (ASI asi)
bool	asiIsReal (ASI asi)
bool	asiIsLittle (ASI asi)
bool	asiIsTwin (ASI asi)
bool	asiIsPartialStore (ASI asi)
bool	asiIsFloatingLoad (ASI asi)
bool	asiIsNoFault (ASI asi)
bool	asiIsScratchPad (ASI asi)
bool	asiIsCmt (ASI asi)
bool	asiIsQueue (ASI asi)
bool	asiIsInterrupt (ASI asi)
bool	asiIsMmu (ASI asi)
bool	asiIsUnPriv (ASI asi)
bool	asiIsPriv (ASI asi)
bool	asiIsHPriv (ASI asi)
bool	asiIsReg (ASI asi)
bool	asiIsSparcError (ASI asi)
bool	asiIsDtlb (ASI)
void	enterREDState (ThreadContext *tc)
	This causes the thread context to enter RED state. More...
void	doREDFault (ThreadContext *tc, TrapType tt)
	This sets everything up for a RED state trap except for actually jumping to the handler. More...
void	doNormalFault (ThreadContext *tc, TrapType tt, bool gotoHpriv)
	This sets everything up for a normal trap except for actually jumping to the handler. More...
void	getREDVector (MiscReg TT, Addr &PC, Addr &NPC)
void	getHyperVector (ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT)
void	getPrivVector (ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
static PSTATE	buildPstateMask ()
StaticInstPtr	decodeInst (ExtMachInst)
SyscallReturn	getresuidFunc (SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
static SyscallReturn	unameFunc (SyscallDesc *desc, int callnum, Process *process, ThreadContext *tc)
	Target uname() handler. More...
template<class XC >
void	handleLockedSnoop (XC *xc, PacketPtr pkt, Addr cacheBlockMask)
template<class XC >
void	handleLockedRead (XC *xc, Request *req)
template<class XC >
void	handleLockedSnoopHit (XC *xc)
template<class XC >
bool	handleLockedWrite (XC *xc, Request *req, Addr cacheBlockMask)
	BitUnion64 (HPSTATE) Bitfield< 0 > tlz
	EndBitUnion (HPSTATE) BitUnion16(PSTATE) Bitfield< 1 > ie
	EndBitUnion (PSTATE) struct STS
Cycles	handleIprRead (ThreadContext *xc, Packet *pkt)
Cycles	handleIprWrite (ThreadContext *xc, Packet *pkt)
template<class TC >
unsigned	getVirtProcNum (TC *tc)
template<class TC >
unsigned	getTargetThread (TC *tc)
uint64_t	getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp)
void	copyMiscRegs (ThreadContext *src, ThreadContext *dest)
void	copyRegs (ThreadContext *src, ThreadContext *dest)
void	skipFunction (ThreadContext *tc)
void	initCPU (ThreadContext *tc, int cpuId)
PCState	buildRetPC (const PCState &curPC, const PCState &callPC)
static bool	inUserMode (ThreadContext *tc)
template<class TC >
void	zeroRegisters (TC *tc)
	Function to insure ISA semantics about 0 registers. More...
void	startupCPU (ThreadContext *tc, int cpuId)
void	advancePC (PCState &pc, const StaticInstPtr &inst)
uint64_t	getExecutingAsid (ThreadContext *tc)
Addr	vtophys (Addr vaddr)
Addr	vtophys (ThreadContext *tc, Addr addr)

Variables
const int	numFillInsts = 32
const int	numSpillInsts = 32
const MachInst	fillHandler64 [numFillInsts]
const MachInst	fillHandler32 [numFillInsts]
const MachInst	spillHandler64 [numSpillInsts]
const MachInst	spillHandler32 [numSpillInsts]
static const PSTATE	PstateMask = buildPstateMask()
const MachInst	NoopMachInst = 0x01000000
const Addr	SegKPMEnd = ULL(0xfffffffc00000000)
const Addr	SegKPMBase = ULL(0xfffffac000000000)
const Addr	PageShift = 13
const Addr	PageBytes = ULL(1) << PageShift
const Addr	StartVAddrHole = ULL(0x0000800000000000)
const Addr	EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF)
const Addr	VAddrAMask = ULL(0xFFFFFFFF)
const Addr	PAddrImplMask = ULL(0x000000FFFFFFFFFF)
const Addr	BytesInPageMask = ULL(0x1FFF)
const bool	HasUnalignedMemAcc = false
const bool	CurThreadInfoImplemented = false
const int	CurThreadInfoReg = -1
Bitfield< 2 >	hpriv
Bitfield< 5 >	red
Bitfield< 10 >	ibe
Bitfield< 11 >	id
Bitfield< 2 >	priv
Bitfield< 3 >	am
Bitfield< 4 >	pef
Bitfield< 7, 6 >	mm
Bitfield< 8 >	tle
Bitfield< 9 >	cle
Bitfield< 10 >	pid0
Bitfield< 11 >	pid1
const int	NumMiscRegs = MISCREG_NUMMISCREGS
const int	ZeroReg = 0
const int	ReturnAddressReg = 31
const int	ReturnValueReg = 8
const int	StackPointerReg = 14
const int	FramePointerReg = 30
const int	SyscallPseudoReturnReg = 9
const int	NumIntArchRegs = 32
const int	NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs
const int	NumCCRegs = 0
const int	TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs
const int	MaxPTL = 2
const int	MaxTL = 6
const int	MaxGL = 3
const int	MaxPGL = 2
const int	NWindows = 8
const int	NumMicroIntRegs = 9
const int	NumFloatRegs = 64
const int	NumFloatArchRegs = NumFloatRegs

Typedef Documentation

typedef uint8_t SparcISA::CCReg

Definition at line 53 of file registers.hh.

typedef uint64_t SparcISA::ExtMachInst

Definition at line 42 of file types.hh.

typedef uint32_t SparcISA::FaultPriority

Definition at line 44 of file faults.hh.

typedef float SparcISA::FloatReg

Definition at line 49 of file registers.hh.

typedef uint32_t SparcISA::FloatRegBits

Definition at line 50 of file registers.hh.

typedef uint64_t SparcISA::IntReg

Definition at line 47 of file registers.hh.

typedef uint32_t SparcISA::MachInst

Definition at line 41 of file types.hh.

typedef uint64_t SparcISA::MiscReg

Definition at line 48 of file registers.hh.

typedef GenericISA::DelaySlotUPCState<MachInst> SparcISA::PCState

Definition at line 44 of file types.hh.

typedef uint16_t SparcISA::RegIndex

Definition at line 62 of file registers.hh.

typedef uint32_t SparcISA::TrapType

Definition at line 43 of file faults.hh.

Enumeration Type Documentation

enum SparcISA::ASI

Enumerator
ASI_IMPLICIT
ASI_NUCLEUS
ASI_N
ASI_NL
ASI_NUCLEUS_LITTLE
ASI_AIUP
ASI_AS_IF_USER_PRIMARY
ASI_AIUS
ASI_AS_IF_USER_SECONDARY
ASI_REAL
ASI_REAL_IO
ASI_BLK_AIUP
ASI_BLOCK_AS_IF_USER_PRIMARY
ASI_BLK_AIUS
ASI_BLOCK_AS_IF_USER_SECONDARY
ASI_AIUP_L
ASI_AS_IF_USER_PRIMARY_LITTLE
ASI_AIUS_L
ASI_AS_IF_USER_SECONDARY_LITTLE
ASI_REAL_L
ASI_REAL_LITTLE
ASI_REAL_IO_L
ASI_REAL_IO_LITTLE
ASI_BLK_AIUP_L
ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
ASI_BLK_AIUS_L
ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
ASI_SCRATCHPAD
ASI_MMU
ASI_LDTX_AIUP
ASI_LD_TWINX_AS_IF_USER_PRIMARY
ASI_LDTX_AIUS
ASI_LD_TWINX_AS_IF_USER_SECONDARY
ASI_QUAD_LDD
ASI_QUEUE
ASI_QUAD_LDD_REAL
ASI_LDTX_REAL
ASI_LDTX_N
ASI_LD_TWINX_NUCLEUS
ASI_ST_BLKINIT_NUCLEUS
ASI_STBI_N
ASI_LDTX_AIUP_L
ASI_TWINX_AS_IF_USER_PRIMARY_LITTLE
ASI_ST_BLKINIT_AS_IF_USER_PRIMARY_LITTLE
ASI_STBI_AIUP_L
ASI_LDTX_AIUS_L
ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE
ASI_ST_BLKINIT_AS_IF_USER_SECONDARY_LITTLE
ASI_STBI_AIUS_L
ASI_LTX_L
ASI_TWINX_LITTLE
ASI_LDTX_REAL_L
ASI_LD_TWINX_REAL_LITTLE
ASI_LDTX_NL
ASI_LD_TWINX_NUCLEUS_LITTLE
ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0
ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1
ASI_DMMU_CTXT_ZERO_CONFIG
ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0
ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1
ASI_IMMU_CTXT_ZERO_CONFIG
ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0
ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1
ASI_DMMU_CTXT_NONZERO_CONFIG
ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0
ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1
ASI_IMMU_CTXT_NONZERO_CONFIG
ASI_STREAM_MA
ASI_CMT_SHARED
ASI_SPARC_BIST_CONTROL
ASI_INST_MASK_REG
ASI_LSU_DIAG_REG
ASI_STM_CTL_REG
ASI_LSU_CONTROL_REG
ASI_DCACHE_DATA
ASI_DCACHE_TAG
ASI_INTR_DISPATCH_STATUS
ASI_INTR_RECEIVE
ASI_UPA_CONFIG_REGISTER
ASI_SPARC_ERROR_EN_REG
ASI_SPARC_ERROR_STATUS_REG
ASI_SPARC_ERROR_ADDRESS_REG
ASI_ECACHE_TAG_DATA
ASI_HYP_SCRATCHPAD
ASI_IMMU
ASI_IMMU_TSB_PS0_PTR_REG
ASI_IMMU_TSB_PS1_PTR_REG
ASI_ITLB_DATA_IN_REG
ASI_ITLB_DATA_ACCESS_REG
ASI_ITLB_TAG_READ_REG
ASI_IMMU_DEMAP
ASI_DMMU
ASI_DMMU_TSB_PS0_PTR_REG
ASI_DMMU_TSB_PS1_PTR_REG
ASI_DMMU_TSB_DIRECT_PTR_REG
ASI_DTLB_DATA_IN_REG
ASI_DTLB_DATA_ACCESS_REG
ASI_DTLB_TAG_READ_REG
ASI_DMMU_DEMAP
ASI_TLB_INVALIDATE_ALL
ASI_CMT_PER_STRAND
ASI_ICACHE_INSTR
ASI_ICACHE_TAG
ASI_SWVR_INTR_RECEIVE
ASI_SWVR_UDB_INTR_W
ASI_SWVR_UDB_INTR_R
ASI_P
ASI_PRIMARY
ASI_S
ASI_SECONDARY
ASI_PNF
ASI_PRIMARY_NO_FAULT
ASI_SNF
ASI_SECONDARY_NO_FAULT
ASI_PL
ASI_PRIMARY_LITTLE
ASI_SL
ASI_SECONDARY_LITTLE
ASI_PNFL
ASI_PRIMARY_NO_FAULT_LITTLE
ASI_SNFL
ASI_SECONDARY_NO_FAULT_LITTLE
ASI_PST8_P
ASI_PST8_PRIMARY
ASI_PST8_S
ASI_PST8_SECONDARY
ASI_PST16_P
ASI_PST16_PRIMARY
ASI_PST16_S
ASI_PST16_SECONDARY
ASI_PST32_P
ASI_PST32_PRIMARY
ASI_PST32_S
ASI_PST32_SECONDARY
ASI_PST8_PL
ASI_PST8_PRIMARY_LITTLE
ASI_PST8_SL
ASI_PST8_SECONDARY_LITTLE
ASI_PST16_PL
ASI_PST16_PRIMARY_LITTLE
ASI_PST16_SL
ASI_PST16_SECONDARY_LITTLE
ASI_PST32_PL
ASI_PST32_PRIMARY_LITTLE
ASI_PST32_SL
ASI_PST32_SECONDARY_LITTLE
ASI_FL8_P
ASI_FL8_PRIMARY
ASI_FL8_S
ASI_FL8_SECONDARY
ASI_FL16_P
ASI_FL16_PRIMARY
ASI_FL16_S
ASI_FL16_SECONDARY
ASI_FL8_PL
ASI_FL8_PRIMARY_LITTLE
ASI_FL8_SL
ASI_FL8_SECONDARY_LITTLE
ASI_FL16_PL
ASI_FL16_PRIMARY_LITTLE
ASI_FL16_SL
ASI_FL16_SECONDARY_LITTLE
ASI_LDTX_P
ASI_LD_TWINX_PRIMARY
ASI_LDTX_S
ASI_LD_TWINX_SECONDARY
ASI_LDTX_PL
ASI_LD_TWINX_PRIMARY_LITTLE
ASI_LDTX_SL
ASI_LD_TWINX_SECONDARY_LITTLE
ASI_BLK_P
ASI_BLOCK_PRIMARY
ASI_BLK_S
ASI_BLOCK_SECONDARY
ASI_BLK_PL
ASI_BLOCK_PRIMARY_LITTLE
ASI_BLK_SL
ASI_BLOCK_SECONDARY_LITTLE
MAX_ASI

Definition at line 38 of file asi.hh.

enum SparcISA::DependenceTags

Enumerator
FP_Reg_Base
CC_Reg_Base
Misc_Reg_Base
Max_Reg_Index

Definition at line 82 of file registers.hh.

enum SparcISA::InterruptTypes

Enumerator
IT_TRAP_LEVEL_ZERO
IT_HINTP
IT_INT_VEC
IT_CPU_MONDO
IT_DEV_MONDO
IT_RES_ERROR
IT_SOFT_INT
NumInterruptTypes

Definition at line 70 of file isa_traits.hh.

enum SparcISA::MiscRegIndex

Enumerator
MISCREG_ASI	Ancillary State Registers.
MISCREG_TICK
MISCREG_FPRS
MISCREG_PCR
MISCREG_PIC
MISCREG_GSR
MISCREG_SOFTINT_SET
MISCREG_SOFTINT_CLR
MISCREG_SOFTINT
MISCREG_TICK_CMPR
MISCREG_STICK
MISCREG_STICK_CMPR
MISCREG_TPC	Privilged Registers.
MISCREG_TNPC
MISCREG_TSTATE
MISCREG_TT
MISCREG_PRIVTICK
MISCREG_TBA
MISCREG_PSTATE
MISCREG_TL
MISCREG_PIL
MISCREG_CWP
MISCREG_GL
MISCREG_HPSTATE	Hyper privileged registers.
MISCREG_HTSTATE
MISCREG_HINTP
MISCREG_HTBA
MISCREG_HVER
MISCREG_STRAND_STS_REG
MISCREG_HSTICK_CMPR
MISCREG_FSR	Floating Point Status Register.
MISCREG_MMU_P_CONTEXT	MMU Internal Registers.
MISCREG_MMU_S_CONTEXT
MISCREG_MMU_PART_ID
MISCREG_MMU_LSU_CTRL
MISCREG_SCRATCHPAD_R0	Scratchpad regiscers.
MISCREG_SCRATCHPAD_R1
MISCREG_SCRATCHPAD_R2
MISCREG_SCRATCHPAD_R3
MISCREG_SCRATCHPAD_R4
MISCREG_SCRATCHPAD_R5
MISCREG_SCRATCHPAD_R6
MISCREG_SCRATCHPAD_R7
MISCREG_QUEUE_CPU_MONDO_HEAD
MISCREG_QUEUE_CPU_MONDO_TAIL
MISCREG_QUEUE_DEV_MONDO_HEAD
MISCREG_QUEUE_DEV_MONDO_TAIL
MISCREG_QUEUE_RES_ERROR_HEAD
MISCREG_QUEUE_RES_ERROR_TAIL
MISCREG_QUEUE_NRES_ERROR_HEAD
MISCREG_QUEUE_NRES_ERROR_TAIL
MISCREG_TLB_DATA
MISCREG_NUMMISCREGS

Definition at line 40 of file miscregs.hh.

Function Documentation

void SparcISA::advancePC ( PCState &  pc, const StaticInstPtr &  inst  )

inline

Definition at line 89 of file utility.hh.

References StaticInst::advancePC().

bool SparcISA::asiIsAsIfUser

(

ASI

asi

)

Definition at line 118 of file asi.cc.

References ASI_AIUP, ASI_AIUP_L, ASI_AIUS, ASI_AIUS_L, ASI_BLK_AIUP, ASI_BLK_AIUP_L, ASI_BLK_AIUS, ASI_BLK_AIUS_L, ASI_LDTX_AIUP, ASI_LDTX_AIUP_L, ASI_LDTX_AIUS, and ASI_LDTX_AIUS_L.

Referenced by SparcISA::TLB::translateData().

bool SparcISA::asiIsBlock

(

ASI

asi

)

Definition at line 38 of file asi.cc.

References ASI_BLK_AIUP, ASI_BLK_AIUP_L, ASI_BLK_AIUS, ASI_BLK_AIUS_L, ASI_BLK_P, ASI_BLK_PL, ASI_BLK_S, and ASI_BLK_SL.

Referenced by SparcISA::TLB::translateData().

bool SparcISA::asiIsCmt

(

ASI

asi

)

Definition at line 249 of file asi.cc.

References ASI_CMT_PER_STRAND, and ASI_CMT_SHARED.

Referenced by asiIsReg(), and SparcISA::TLB::translateData().

bool SparcISA::asiIsDtlb

(

ASI

)

bool SparcISA::asiIsFloatingLoad

(

ASI

asi

)

Definition at line 220 of file asi.cc.

References ASI_FL16_P, ASI_FL16_PL, ASI_FL16_S, ASI_FL16_SL, ASI_FL8_P, ASI_FL8_PL, ASI_FL8_S, and ASI_FL8_SL.

bool SparcISA::asiIsHPriv

(

ASI

asi

)

Definition at line 298 of file asi.cc.

Referenced by SparcISA::TLB::translateData().

bool SparcISA::asiIsInterrupt

(

ASI

asi

)

Definition at line 262 of file asi.cc.

References ASI_SWVR_INTR_RECEIVE, ASI_SWVR_UDB_INTR_R, and ASI_SWVR_UDB_INTR_W.

Referenced by asiIsReg(), and SparcISA::TLB::translateData().

bool SparcISA::asiIsIO

(

ASI

asi

)

Definition at line 135 of file asi.cc.

References ASI_REAL_IO, and ASI_REAL_IO_L.

bool SparcISA::asiIsLittle

(

ASI

asi

)

Definition at line 153 of file asi.cc.

References ASI_AIUP_L, ASI_AIUS_L, ASI_BLK_AIUP_L, ASI_BLK_AIUS_L, ASI_BLK_PL, ASI_BLK_SL, ASI_FL16_PL, ASI_FL16_SL, ASI_FL8_PL, ASI_FL8_SL, ASI_LDTX_AIUP_L, ASI_LDTX_AIUS_L, ASI_LDTX_NL, ASI_LDTX_PL, ASI_LDTX_REAL_L, ASI_LDTX_SL, ASI_LTX_L, ASI_NL, ASI_PL, ASI_PNFL, ASI_PST16_PL, ASI_PST16_SL, ASI_PST32_PL, ASI_PST32_SL, ASI_PST8_PL, ASI_PST8_SL, ASI_REAL_IO_L, ASI_REAL_L, ASI_SL, and ASI_SNFL.

Referenced by SparcISA::TLB::translateData().

bool SparcISA::asiIsMmu

(

ASI

asi

)

Definition at line 270 of file asi.cc.

References ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0, ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0, ASI_IMMU, ASI_IMMU_CTXT_NONZERO_CONFIG, ASI_IMMU_CTXT_ZERO_CONFIG, ASI_IMMU_TSB_PS1_PTR_REG, ASI_ITLB_DATA_IN_REG, ASI_LSU_CONTROL_REG, ASI_MMU, and ASI_TLB_INVALIDATE_ALL.

Referenced by asiIsReg(), and SparcISA::TLB::translateData().

bool SparcISA::asiIsNoFault

(

ASI

asi

)

Definition at line 233 of file asi.cc.

References ASI_PNF, ASI_PNFL, ASI_SNF, and ASI_SNFL.

Referenced by SparcISA::TLB::translateData().

bool SparcISA::asiIsNucleus

(

ASI

asi

)

Definition at line 109 of file asi.cc.

References ASI_LDTX_N, ASI_LDTX_NL, ASI_N, and ASI_NL.

Referenced by SparcISA::TLB::translateData().

bool SparcISA::asiIsPartialStore

(

ASI

asi

)

Definition at line 203 of file asi.cc.

References ASI_PST16_P, ASI_PST16_PL, ASI_PST16_S, ASI_PST16_SL, ASI_PST32_P, ASI_PST32_PL, ASI_PST32_S, ASI_PST32_SL, ASI_PST8_P, ASI_PST8_PL, ASI_PST8_S, and ASI_PST8_SL.

Referenced by SparcISA::TLB::translateData().

bool SparcISA::asiIsPrimary

(

ASI

asi

)

Definition at line 51 of file asi.cc.

References ASI_AIUP, ASI_AIUP_L, ASI_BLK_AIUP, ASI_BLK_AIUP_L, ASI_BLK_P, ASI_BLK_PL, ASI_FL16_P, ASI_FL16_PL, ASI_FL8_P, ASI_FL8_PL, ASI_LDTX_AIUP, ASI_LDTX_AIUP_L, ASI_LDTX_P, ASI_LDTX_PL, ASI_P, ASI_PL, ASI_PNF, ASI_PNFL, ASI_PST16_P, ASI_PST16_PL, ASI_PST32_P, ASI_PST32_PL, ASI_PST8_P, and ASI_PST8_PL.

Referenced by SparcISA::TLB::translateData().

bool SparcISA::asiIsPriv

(

ASI

asi

)

Definition at line 291 of file asi.cc.

bool SparcISA::asiIsQueue

(

ASI

asi

)

Definition at line 256 of file asi.cc.

References ASI_QUEUE.

Referenced by SparcISA::TLB::translateData().

bool SparcISA::asiIsReal

(

ASI

asi

)

Definition at line 142 of file asi.cc.

References ASI_LDTX_REAL, ASI_LDTX_REAL_L, ASI_REAL, ASI_REAL_IO, ASI_REAL_IO_L, and ASI_REAL_L.

Referenced by SparcISA::FastDataAccessMMUMiss::invoke(), and SparcISA::TLB::translateData().

bool SparcISA::asiIsReg

(

ASI

asi

)

Definition at line 304 of file asi.cc.

References asiIsCmt(), asiIsInterrupt(), asiIsMmu(), asiIsScratchPad(), and asiIsSparcError().

bool SparcISA::asiIsScratchPad

(

ASI

asi

)

Definition at line 242 of file asi.cc.

References ASI_HYP_SCRATCHPAD, and ASI_SCRATCHPAD.

Referenced by asiIsReg(), and SparcISA::TLB::translateData().

bool SparcISA::asiIsSecondary

(

ASI

asi

)

Definition at line 80 of file asi.cc.

References ASI_AIUS, ASI_AIUS_L, ASI_BLK_AIUS, ASI_BLK_AIUS_L, ASI_BLK_S, ASI_BLK_SL, ASI_FL16_S, ASI_FL16_SL, ASI_FL8_S, ASI_FL8_SL, ASI_LDTX_AIUS, ASI_LDTX_AIUS_L, ASI_LDTX_S, ASI_LDTX_SL, ASI_PST16_S, ASI_PST16_SL, ASI_PST32_S, ASI_PST32_SL, ASI_PST8_S, ASI_PST8_SL, ASI_S, ASI_SL, ASI_SNF, and ASI_SNFL.

Referenced by SparcISA::TLB::translateData().

bool SparcISA::asiIsSparcError

(

ASI

asi

)

Definition at line 312 of file asi.cc.

References ASI_SPARC_ERROR_EN_REG, and ASI_SPARC_ERROR_STATUS_REG.

Referenced by asiIsReg(), and SparcISA::TLB::translateData().

bool SparcISA::asiIsTwin

(

ASI

asi

)

Definition at line 188 of file asi.cc.

References ASI_LDTX_AIUP, ASI_LDTX_AIUP_L, ASI_LDTX_N, ASI_LDTX_NL, ASI_LDTX_P, ASI_LDTX_PL, ASI_LDTX_S, ASI_LDTX_SL, and ASI_QUEUE.

Referenced by SparcISA::TLB::translateData().

bool SparcISA::asiIsUnPriv

(

ASI

asi

)

Definition at line 285 of file asi.cc.

Referenced by SparcISA::TLB::translateData().

SparcISA::BitUnion64

(

HPSTATE

)

static PSTATE SparcISA::buildPstateMask ( )

static

Definition at line 47 of file isa.cc.

References ArmISA::mask.

PCState SparcISA::buildRetPC ( const PCState &  curPC, const PCState &  callPC  )

inline

Definition at line 47 of file utility.hh.

References GenericISA::SimplePCState< MachInst >::npc(), GenericISA::SimplePCState< MachInst >::pc(), and GenericISA::DelaySlotUPCState< MachInst >::uEnd().

void SparcISA::copyMiscRegs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

Definition at line 68 of file utility.cc.

References ArmISA::i, MaxTL, MISCREG_ASI, MISCREG_CWP, MISCREG_FPRS, MISCREG_FSR, MISCREG_GL, MISCREG_HINTP, MISCREG_HPSTATE, MISCREG_HSTICK_CMPR, MISCREG_HTBA, MISCREG_MMU_LSU_CTRL, MISCREG_MMU_P_CONTEXT, MISCREG_MMU_PART_ID, MISCREG_MMU_S_CONTEXT, MISCREG_PIL, MISCREG_PSTATE, MISCREG_QUEUE_CPU_MONDO_HEAD, MISCREG_QUEUE_CPU_MONDO_TAIL, MISCREG_QUEUE_DEV_MONDO_HEAD, MISCREG_QUEUE_DEV_MONDO_TAIL, MISCREG_QUEUE_NRES_ERROR_HEAD, MISCREG_QUEUE_NRES_ERROR_TAIL, MISCREG_QUEUE_RES_ERROR_HEAD, MISCREG_QUEUE_RES_ERROR_TAIL, MISCREG_SCRATCHPAD_R0, MISCREG_SCRATCHPAD_R1, MISCREG_SCRATCHPAD_R2, MISCREG_SCRATCHPAD_R3, MISCREG_SCRATCHPAD_R4, MISCREG_SCRATCHPAD_R5, MISCREG_SCRATCHPAD_R6, MISCREG_SCRATCHPAD_R7, MISCREG_SOFTINT, MISCREG_STICK, MISCREG_STICK_CMPR, MISCREG_STRAND_STS_REG, MISCREG_TBA, MISCREG_TICK, MISCREG_TICK_CMPR, MISCREG_TL, MISCREG_TNPC, MISCREG_TPC, MISCREG_TSTATE, MISCREG_TT, ThreadContext::readMiscRegNoEffect(), ThreadContext::setMiscReg(), ThreadContext::setMiscRegNoEffect(), and MipsISA::tl.

Referenced by copyRegs().

void SparcISA::copyRegs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

Definition at line 204 of file utility.cc.

References copyMiscRegs(), ArmISA::i, MaxGL, MISCREG_CWP, MISCREG_GL, NumCCRegs, NumFloatArchRegs, NumIntArchRegs, NumMicroIntRegs, NWindows, ThreadContext::pcState(), ThreadContext::readFloatRegBits(), ThreadContext::readIntReg(), ThreadContext::readMiscRegNoEffect(), ThreadContext::setFloatRegBits(), ThreadContext::setIntReg(), ThreadContext::setMiscReg(), and X86ISA::x.

StaticInstPtr SparcISA::decodeInst

(

ExtMachInst

)

void SparcISA::doNormalFault	(	ThreadContext *	tc,
		TrapType	tt,
		bool	gotoHpriv
	)

This sets everything up for a normal trap except for actually jumping to the handler.

Definition at line 375 of file faults.cc.

References ArmISA::mask, MaxGL, MaxPGL, MISCREG_ASI, MISCREG_CWP, MISCREG_GL, MISCREG_HPSTATE, MISCREG_HTSTATE, MISCREG_PSTATE, MISCREG_TL, MISCREG_TNPC, MISCREG_TPC, MISCREG_TSTATE, MISCREG_TT, GenericISA::SimplePCState< MachInst >::npc(), AlphaISA::NumIntArchRegs, NWindows, pc, GenericISA::SimplePCState< MachInst >::pc(), ThreadContext::pcState(), ThreadContext::readIntReg(), ThreadContext::readMiscRegNoEffect(), replaceBits(), ThreadContext::setMiscReg(), and ThreadContext::setMiscRegNoEffect().

Referenced by SparcISA::SparcFaultBase::invoke(), SparcISA::SpillNNormal::invoke(), and SparcISA::FillNNormal::invoke().

void SparcISA::doREDFault	(	ThreadContext *	tc,
		TrapType	tt
	)

This sets everything up for a RED state trap except for actually jumping to the handler.

Definition at line 296 of file faults.cc.

References ArmISA::mask, MaxGL, MISCREG_ASI, MISCREG_CWP, MISCREG_GL, MISCREG_HPSTATE, MISCREG_HTSTATE, MISCREG_PSTATE, MISCREG_TL, MISCREG_TNPC, MISCREG_TPC, MISCREG_TSTATE, MISCREG_TT, GenericISA::SimplePCState< MachInst >::npc(), AlphaISA::NumIntArchRegs, NWindows, pc, GenericISA::SimplePCState< MachInst >::pc(), ThreadContext::pcState(), priv, ThreadContext::readIntReg(), ThreadContext::readMiscRegNoEffect(), replaceBits(), ThreadContext::setMiscReg(), and ThreadContext::setMiscRegNoEffect().

Referenced by SparcISA::SparcFaultBase::invoke().

SparcISA::EndBitUnion

(

HPSTATE

)

SparcISA::EndBitUnion

(

PSTATE

)

Definition at line 137 of file miscregs.hh.

void SparcISA::enterREDState

(

ThreadContext *

tc

)

This causes the thread context to enter RED state.

This causes the side effects which go with entering RED state because of a trap.

Definition at line 275 of file faults.cc.

References MISCREG_HPSTATE, MISCREG_PSTATE, ThreadContext::readMiscRegNoEffect(), and ThreadContext::setMiscReg().

Referenced by SparcISA::SparcFaultBase::invoke(), and SparcISA::PowerOnReset::invoke().

uint64_t SparcISA::getArgument	(	ThreadContext *	tc,
		int &	number,
		uint16_t	size,
		bool	fp
	)

Definition at line 48 of file utility.cc.

References FullSystem, ThreadContext::getVirtProxy(), ArmISA::NumArgumentRegs, panic, PortProxy::read(), ThreadContext::readIntReg(), ArmISA::sp, and StackPointerReg.

uint64_t SparcISA::getExecutingAsid ( ThreadContext *  tc )

inline

Definition at line 95 of file utility.hh.

References MISCREG_MMU_P_CONTEXT, and ThreadContext::readMiscRegNoEffect().

void SparcISA::getHyperVector	(	ThreadContext *	tc,
		Addr &	PC,
		Addr &	NPC,
		MiscReg	TT
	)

Definition at line 475 of file faults.cc.

References ArmISA::mask, MISCREG_HTBA, and ThreadContext::readMiscRegNoEffect().

Referenced by SparcISA::SparcFaultBase::invoke().

void SparcISA::getPrivVector	(	ThreadContext *	tc,
		Addr &	PC,
		Addr &	NPC,
		MiscReg	TT,
		MiscReg	TL
	)

Definition at line 483 of file faults.cc.

References ArmISA::mask, MISCREG_TBA, and ThreadContext::readMiscRegNoEffect().

Referenced by SparcISA::SparcFaultBase::invoke().

void SparcISA::getREDVector	(	MiscReg	TT,
		Addr &	PC,
		Addr &	NPC
	)

Definition at line 466 of file faults.cc.

References ULL.

Referenced by SparcISA::SparcFaultBase::invoke(), and SparcISA::PowerOnReset::invoke().

SyscallReturn SparcISA::getresuidFunc	(	SyscallDesc *	desc,
		int	num,
		Process *	p,
		ThreadContext *	tc
	)

Definition at line 61 of file syscalls.cc.

References BufferArg::bufferPtr(), BaseBufferArg::copyOut(), ThreadContext::getMemProxy(), Process::getSyscallArg(), BigEndianGuest::htog(), id, and MipsISA::index.

template<class TC >

unsigned SparcISA::getTargetThread ( TC *  tc )

inline

Definition at line 62 of file mt.hh.

References fatal.

template<class TC >

unsigned SparcISA::getVirtProcNum ( TC *  tc )

inline

Definition at line 53 of file mt.hh.

References fatal.

Cycles SparcISA::handleIprRead ( ThreadContext *  xc, Packet *  pkt  )

inline

Definition at line 49 of file mmapped_ipr.hh.

References ThreadContext::getDTBPtr(), GenericISA::handleGenericIprRead(), and GenericISA::isGenericIprAccess().

Cycles SparcISA::handleIprWrite ( ThreadContext *  xc, Packet *  pkt  )

inline

Definition at line 58 of file mmapped_ipr.hh.

References ThreadContext::getDTBPtr(), GenericISA::handleGenericIprWrite(), and GenericISA::isGenericIprAccess().

template<class XC >

void SparcISA::handleLockedRead ( XC *  xc, Request *  req  )

inline

Definition at line 53 of file locked_mem.hh.

template<class XC >

void SparcISA::handleLockedSnoop ( XC *  xc, PacketPtr  pkt, Addr  cacheBlockMask  )

inline

Definition at line 47 of file locked_mem.hh.

template<class XC >

void SparcISA::handleLockedSnoopHit ( XC *  xc )

inline

Definition at line 59 of file locked_mem.hh.

template<class XC >

bool SparcISA::handleLockedWrite ( XC *  xc, Request *  req, Addr  cacheBlockMask  )

inline

Definition at line 66 of file locked_mem.hh.

void SparcISA::initCPU	(	ThreadContext *	tc,
		int	cpuId
	)

Definition at line 258 of file utility.cc.

static bool SparcISA::inUserMode ( ThreadContext *  tc )

inlinestatic

Definition at line 58 of file utility.hh.

References MISCREG_HPSTATE, MISCREG_PSTATE, and ThreadContext::readMiscRegNoEffect().

void SparcISA::skipFunction

(

ThreadContext *

tc

)

Definition at line 249 of file utility.cc.

References ThreadContext::pcState(), ThreadContext::readIntReg(), and ReturnAddressReg.

void SparcISA::startupCPU ( ThreadContext *  tc, int  cpuId  )

inline

Definition at line 75 of file utility.hh.

References ThreadContext::activate(), and FullSystem.

static SyscallReturn SparcISA::unameFunc ( SyscallDesc *  desc, int  callnum, Process *  process, ThreadContext *  tc  )

static

Target uname() handler.

Definition at line 42 of file syscalls.cc.

References ThreadContext::getMemProxy(), Process::getSyscallArg(), MipsISA::index, and name().

Addr SparcISA::vtophys ( Addr  vaddr )

inline

Definition at line 48 of file vtophys.cc.

References panic.

Addr SparcISA::vtophys ( ThreadContext *  tc, Addr  addr  )

inline

Definition at line 61 of file vtophys.cc.

References addr, betoh(), bits(), DPRINTF, ThreadContext::getDTBPtr(), ThreadContext::getITBPtr(), ThreadContext::getPhysProxy(), SparcISA::TLB::GetTsbPtr(), hpriv, SparcISA::TLB::lookup(), MISCREG_TLB_DATA, panic, SparcISA::PageTableEntry::populate(), SparcISA::TlbEntry::pte, PortProxy::read(), ThreadContext::readMiscRegNoEffect(), MipsISA::tbe, SparcISA::PageTableEntry::translate(), SparcISA::TteTag::va(), VAddrAMask, SparcISA::TteTag::valid(), and X86ISA::x.

template<class TC >

void SparcISA::zeroRegisters

(

TC *

tc

)

Function to insure ISA semantics about 0 registers.

Parameters

tc	The thread context.

Variable Documentation

Bitfield<3> SparcISA::am

Definition at line 130 of file miscregs.hh.

Referenced by LinuxArmSystem::initState().

const Addr SparcISA::BytesInPageMask = ULL(0x1FFF)

Definition at line 68 of file isa_traits.hh.

Bitfield<9> SparcISA::cle

Definition at line 134 of file miscregs.hh.

const bool SparcISA::CurThreadInfoImplemented = false

Definition at line 85 of file isa_traits.hh.

const int SparcISA::CurThreadInfoReg = -1

Definition at line 86 of file isa_traits.hh.

const Addr SparcISA::EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF)

Definition at line 65 of file isa_traits.hh.

Referenced by SparcISA::TLB::validVirtualAddress().

const MachInst SparcISA::fillHandler32[numFillInsts]

Definition at line 81 of file handlers.hh.

Referenced by Sparc32Process::argsInit().

const MachInst SparcISA::fillHandler64[numFillInsts]

Definition at line 45 of file handlers.hh.

Referenced by Sparc64Process::argsInit().

const int SparcISA::FramePointerReg = 30

Definition at line 70 of file registers.hh.

const bool SparcISA::HasUnalignedMemAcc = false

Definition at line 83 of file isa_traits.hh.

Bitfield<2> SparcISA::hpriv

Definition at line 121 of file miscregs.hh.

Referenced by SparcISA::FastDataAccessMMUMiss::invoke(), SparcISA::TLB::translateData(), SparcISA::TLB::translateInst(), and vtophys().

Bitfield<10> SparcISA::ibe

Definition at line 123 of file miscregs.hh.

Bitfield<11> SparcISA::id

Definition at line 124 of file miscregs.hh.

Referenced by Profiler::addAddressTraceSample(), ArmISA::PMU::addEventProbe(), ArmV8KvmCPU::dump(), ArmKvmCPU::dumpKvmStateMisc(), flit::flit(), ArmISA::PMU::getCounter(), BaseKvmCPU::getOneReg(), getresuidFunc(), ArmISA::PMU::handleEvent(), IDToInt(), LSQUnit< Impl >::init(), InputUnit::InputUnit(), intToID(), OutputUnit::OutputUnit(), OutVcState::OutVcState(), TrafficGen::parseConfig(), RubyPort::MemSlavePort::recvTimingReq(), System::registerThreadContext(), Minor::Fetch1::FetchRequest::reportData(), ThreadState::setContextId(), Network::setFromNetQueue(), BaseKvmCPU::setOneReg(), ThreadState::setThreadId(), Network::setToNetQueue(), Request::taskId(), BaseXBar::updatePortCache(), and VirtualChannel::VirtualChannel().

const int SparcISA::MaxGL = 3

Definition at line 39 of file sparc_traits.hh.

Referenced by copyRegs(), doNormalFault(), doREDFault(), and SparcISA::PowerOnReset::invoke().

const int SparcISA::MaxPGL = 2

Definition at line 40 of file sparc_traits.hh.

Referenced by doNormalFault().

const int SparcISA::MaxPTL = 2

Definition at line 37 of file sparc_traits.hh.

Referenced by SparcISA::SparcFaultBase::invoke().

const int SparcISA::MaxTL = 6

Definition at line 38 of file sparc_traits.hh.

Referenced by copyMiscRegs(), SparcISA::SparcFaultBase::invoke(), SparcISA::PowerOnReset::invoke(), SparcISA::ISA::readFSReg(), SparcISA::ISA::serialize(), and SparcISA::ISA::unserialize().

Bitfield<7, 6> SparcISA::mm

Definition at line 132 of file miscregs.hh.

Referenced by DumpStatsPCEvent::process(), and ElfObject::tryFile().

const MachInst SparcISA::NoopMachInst = 0x01000000

Definition at line 51 of file isa_traits.hh.

const int SparcISA::NumCCRegs = 0

Definition at line 77 of file registers.hh.

Referenced by copyRegs().

const int SparcISA::numFillInsts = 32

Definition at line 42 of file handlers.hh.

Referenced by SparcProcess::argsInit(), Sparc32Process::argsInit(), and Sparc64Process::argsInit().

const int SparcISA::NumFloatArchRegs = NumFloatRegs

Definition at line 51 of file sparc_traits.hh.

Referenced by copyRegs().

const int SparcISA::NumFloatRegs = 64

Definition at line 50 of file sparc_traits.hh.

const int SparcISA::NumIntArchRegs = 32

Definition at line 75 of file registers.hh.

Referenced by Trace::SparcNativeTrace::check(), copyRegs(), SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), and SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs().

const int SparcISA::NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs

Definition at line 76 of file registers.hh.

Referenced by SparcISA::ISA::flattenIntIndex(), SparcISA::ISA::installGlobals(), and SparcISA::ISA::installWindow().

const int SparcISA::NumMicroIntRegs = 9

Definition at line 45 of file sparc_traits.hh.

Referenced by copyRegs(), and SparcISA::ISA::reloadRegMap().

const int SparcISA::NumMiscRegs = MISCREG_NUMMISCREGS

Definition at line 158 of file miscregs.hh.

Referenced by getMiscRegName().

const int SparcISA::numSpillInsts = 32

Definition at line 43 of file handlers.hh.

Referenced by Sparc32Process::argsInit(), and Sparc64Process::argsInit().

const int SparcISA::NWindows = 8

Definition at line 43 of file sparc_traits.hh.

Referenced by cloneFunc(), copyRegs(), doNormalFault(), doREDFault(), Sparc32Process::flushWindows(), Sparc64Process::flushWindows(), SparcProcess::initState(), SparcISA::ISA::readFSReg(), SparcISA::ISA::reloadRegMap(), and SparcISA::ISA::setMiscReg().

const Addr SparcISA::PAddrImplMask = ULL(0x000000FFFFFFFFFF)

Definition at line 67 of file isa_traits.hh.

Referenced by SparcISA::TLB::translateData(), and SparcISA::TLB::translateInst().

const Addr SparcISA::PageBytes = ULL(1) << PageShift

Definition at line 59 of file isa_traits.hh.

Referenced by SparcProcess::argsInit(), Sparc32Process::Sparc32Process(), and Sparc64Process::Sparc64Process().

const Addr SparcISA::PageShift = 13

Definition at line 58 of file isa_traits.hh.

Bitfield<4> SparcISA::pef

Definition at line 131 of file miscregs.hh.

Bitfield<10> SparcISA::pid0

Definition at line 135 of file miscregs.hh.

Bitfield<11> SparcISA::pid1

Definition at line 136 of file miscregs.hh.

Bitfield<2> SparcISA::priv

Definition at line 129 of file miscregs.hh.

Referenced by doREDFault(), PacketFifoEntry::serialize(), SparcISA::TLB::translateData(), SparcISA::TLB::translateInst(), and PacketFifoEntry::unserialize().

const PSTATE SparcISA::PstateMask = buildPstateMask()

static

Definition at line 61 of file isa.cc.

Referenced by SparcISA::ISA::setMiscReg(), and SparcISA::ISA::setMiscRegNoEffect().

Bitfield<5> SparcISA::red

Definition at line 122 of file miscregs.hh.

Referenced by SparcISA::FastDataAccessMMUMiss::invoke(), main(), SparcISA::TLB::translateData(), and SparcISA::TLB::translateInst().

const int SparcISA::ReturnAddressReg = 31

Definition at line 67 of file registers.hh.

Referenced by skipFunction().

const int SparcISA::ReturnValueReg = 8

Definition at line 68 of file registers.hh.

const Addr SparcISA::SegKPMBase = ULL(0xfffffac000000000)

Definition at line 56 of file isa_traits.hh.

const Addr SparcISA::SegKPMEnd = ULL(0xfffffffc00000000)

Definition at line 55 of file isa_traits.hh.

const MachInst SparcISA::spillHandler32[numSpillInsts]

Definition at line 153 of file handlers.hh.

Referenced by Sparc32Process::argsInit().

const MachInst SparcISA::spillHandler64[numSpillInsts]

Definition at line 117 of file handlers.hh.

Referenced by Sparc64Process::argsInit().

const int SparcISA::StackPointerReg = 14

Definition at line 69 of file registers.hh.

Referenced by getArgument().

const Addr SparcISA::StartVAddrHole = ULL(0x0000800000000000)

Definition at line 64 of file isa_traits.hh.

Referenced by SparcISA::TLB::validVirtualAddress().

const int SparcISA::SyscallPseudoReturnReg = 9

Definition at line 73 of file registers.hh.

Bitfield<8> SparcISA::tle

Definition at line 133 of file miscregs.hh.

const int SparcISA::TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs

Definition at line 79 of file registers.hh.

const Addr SparcISA::VAddrAMask = ULL(0xFFFFFFFF)

Definition at line 66 of file isa_traits.hh.

Referenced by SparcISA::TLB::translateData(), SparcISA::TLB::translateInst(), and vtophys().

const int SparcISA::ZeroReg = 0

Definition at line 65 of file registers.hh.