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utility.cc
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1 /*
2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  *
28  * Authors: Gabe Black
29  * Ali Saidi
30  */
31 
32 #include "arch/sparc/utility.hh"
33 
34 #include "arch/sparc/faults.hh"
35 #include "arch/sparc/vtophys.hh"
36 #include "mem/fs_translating_port_proxy.hh"
37 
38 namespace SparcISA {
39 
40 
41 // The caller uses %o0-%05 for the first 6 arguments even if their floating
42 // point. Double precision floating point values take two registers/args.
43 // Quads, structs, and unions are passed as pointers. All arguments beyond
44 // the sixth are passed on the stack past the 16 word window save area,
45 // space for the struct/union return pointer, and space reserved for the
46 // first 6 arguments which the caller may use but doesn't have to.
47 uint64_t
48 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
49 {
50  if (!FullSystem) {
51  panic("getArgument() only implemented for full system\n");
52  M5_DUMMY_RETURN
53  }
54 
55  const int NumArgumentRegs = 6;
56  if (number < NumArgumentRegs) {
57  return tc->readIntReg(8 + number);
58  } else {
59  Addr sp = tc->readIntReg(StackPointerReg);
60  FSTranslatingPortProxy &vp = tc->getVirtProxy();
61  uint64_t arg = vp.read<uint64_t>(sp + 92 +
62  (number-NumArgumentRegs) * sizeof(uint64_t));
63  return arg;
64  }
65 }
66 
67 void
68 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
69 {
70 
71  uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
72 
73  // Read all the trap level dependent registers and save them off
74  for (int i = 1; i <= MaxTL; i++) {
75  src->setMiscRegNoEffect(MISCREG_TL, i);
76  dest->setMiscRegNoEffect(MISCREG_TL, i);
77 
78  dest->setMiscRegNoEffect(MISCREG_TT,
79  src->readMiscRegNoEffect(MISCREG_TT));
80  dest->setMiscRegNoEffect(MISCREG_TPC,
81  src->readMiscRegNoEffect(MISCREG_TPC));
82  dest->setMiscRegNoEffect(MISCREG_TNPC,
83  src->readMiscRegNoEffect(MISCREG_TNPC));
84  dest->setMiscRegNoEffect(MISCREG_TSTATE,
85  src->readMiscRegNoEffect(MISCREG_TSTATE));
86  }
87 
88  // Save off the traplevel
89  dest->setMiscRegNoEffect(MISCREG_TL, tl);
90  src->setMiscRegNoEffect(MISCREG_TL, tl);
91 
92 
93  // ASRs
94 // dest->setMiscRegNoEffect(MISCREG_Y,
95 // src->readMiscRegNoEffect(MISCREG_Y));
96 // dest->setMiscRegNoEffect(MISCREG_CCR,
97 // src->readMiscRegNoEffect(MISCREG_CCR));
98  dest->setMiscReg(MISCREG_ASI,
99  src->readMiscRegNoEffect(MISCREG_ASI));
100  dest->setMiscRegNoEffect(MISCREG_TICK,
101  src->readMiscRegNoEffect(MISCREG_TICK));
102  dest->setMiscRegNoEffect(MISCREG_FPRS,
103  src->readMiscRegNoEffect(MISCREG_FPRS));
104  dest->setMiscRegNoEffect(MISCREG_SOFTINT,
105  src->readMiscRegNoEffect(MISCREG_SOFTINT));
106  dest->setMiscRegNoEffect(MISCREG_TICK_CMPR,
107  src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
108  dest->setMiscRegNoEffect(MISCREG_STICK,
109  src->readMiscRegNoEffect(MISCREG_STICK));
110  dest->setMiscRegNoEffect(MISCREG_STICK_CMPR,
111  src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
112 
113  // Priv Registers
114  dest->setMiscRegNoEffect(MISCREG_TICK,
115  src->readMiscRegNoEffect(MISCREG_TICK));
116  dest->setMiscRegNoEffect(MISCREG_TBA,
117  src->readMiscRegNoEffect(MISCREG_TBA));
118  dest->setMiscRegNoEffect(MISCREG_PSTATE,
119  src->readMiscRegNoEffect(MISCREG_PSTATE));
120  dest->setMiscRegNoEffect(MISCREG_PIL,
121  src->readMiscRegNoEffect(MISCREG_PIL));
122  dest->setMiscReg(MISCREG_CWP,
123  src->readMiscRegNoEffect(MISCREG_CWP));
124 // dest->setMiscRegNoEffect(MISCREG_CANSAVE,
125 // src->readMiscRegNoEffect(MISCREG_CANSAVE));
126 // dest->setMiscRegNoEffect(MISCREG_CANRESTORE,
127 // src->readMiscRegNoEffect(MISCREG_CANRESTORE));
128 // dest->setMiscRegNoEffect(MISCREG_OTHERWIN,
129 // src->readMiscRegNoEffect(MISCREG_OTHERWIN));
130 // dest->setMiscRegNoEffect(MISCREG_CLEANWIN,
131 // src->readMiscRegNoEffect(MISCREG_CLEANWIN));
132 // dest->setMiscRegNoEffect(MISCREG_WSTATE,
133 // src->readMiscRegNoEffect(MISCREG_WSTATE));
134  dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
135 
136  // Hyperprivilged registers
137  dest->setMiscRegNoEffect(MISCREG_HPSTATE,
138  src->readMiscRegNoEffect(MISCREG_HPSTATE));
139  dest->setMiscRegNoEffect(MISCREG_HINTP,
140  src->readMiscRegNoEffect(MISCREG_HINTP));
141  dest->setMiscRegNoEffect(MISCREG_HTBA,
142  src->readMiscRegNoEffect(MISCREG_HTBA));
143  dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
144  src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
145  dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
146  src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
147 
148  // FSR
149  dest->setMiscRegNoEffect(MISCREG_FSR,
150  src->readMiscRegNoEffect(MISCREG_FSR));
151 
152  // Strand Status Register
153  dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
154  src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
155 
156  // MMU Registers
157  dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
158  src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
159  dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
160  src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
161  dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
162  src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
163  dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
164  src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
165 
166  // Scratchpad Registers
167  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
168  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
169  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
170  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
171  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
172  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
173  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
174  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
175  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
176  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
177  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
178  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
179  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
180  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
181  dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
182  src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
183 
184  // Queue Registers
185  dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
186  src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
187  dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
188  src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
189  dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
190  src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
191  dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
192  src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
193  dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
194  src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
195  dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
196  src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
197  dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
198  src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
199  dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
200  src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
201 }
202 
203 void
204 copyRegs(ThreadContext *src, ThreadContext *dest)
205 {
206  // First loop through the integer registers.
207  int old_gl = src->readMiscRegNoEffect(MISCREG_GL);
208  int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP);
209  // Globals
210  for (int x = 0; x < MaxGL; ++x) {
211  src->setMiscReg(MISCREG_GL, x);
212  dest->setMiscReg(MISCREG_GL, x);
213  // Skip %g0 which is always zero.
214  for (int y = 1; y < 8; y++)
215  dest->setIntReg(y, src->readIntReg(y));
216  }
217  // Locals and ins. Outs are all also ins.
218  for (int x = 0; x < NWindows; ++x) {
219  src->setMiscReg(MISCREG_CWP, x);
220  dest->setMiscReg(MISCREG_CWP, x);
221  for (int y = 16; y < 32; y++)
222  dest->setIntReg(y, src->readIntReg(y));
223  }
224  // Microcode reg and pseudo int regs (misc regs in the integer regfile).
225  for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y)
226  dest->setIntReg(y, src->readIntReg(y));
227 
228  // Restore src's GL, CWP
229  src->setMiscReg(MISCREG_GL, old_gl);
230  src->setMiscReg(MISCREG_CWP, old_cwp);
231 
232 
233  // Then loop through the floating point registers.
234  for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
235  dest->setFloatRegBits(i, src->readFloatRegBits(i));
236  }
237 
238  // Would need to add condition-code regs if implemented
239  assert(NumCCRegs == 0);
240 
241  // Copy misc. registers
242  copyMiscRegs(src, dest);
243 
244  // Lastly copy PC/NPC
245  dest->pcState(src->pcState());
246 }
247 
248 void
249 skipFunction(ThreadContext *tc)
250 {
251  TheISA::PCState newPC = tc->pcState();
252  newPC.set(tc->readIntReg(ReturnAddressReg));
253  tc->pcState(newPC);
254 }
255 
256 
257 void
258 initCPU(ThreadContext *tc, int cpuId)
259 {
260  static Fault por = std::make_shared<PowerOnReset>();
261  if (cpuId == 0)
262  por->invoke(tc);
263 }
264 
265 } // namespace SPARC_ISA
FSTranslatingPortProxy
A TranslatingPortProxy in FS mode translates a virtual address to a physical address and then calls t...
Definition: fs_translating_port_proxy.hh:73
ArmISA::i
Bitfield< 7 > i
Definition: miscregs.hh:1378
panic
#define panic(...)
Definition: misc.hh:153
SparcISA::MaxGL
const int MaxGL
Definition: sparc_traits.hh:39
MipsISA::fp
Bitfield< 0 > fp
Definition: pra_constants.hh:246
ThreadContext::readMiscRegNoEffect
virtual MiscReg readMiscRegNoEffect(int misc_reg) const =0
ArmISA::sp
Bitfield< 0 > sp
Definition: miscregs.hh:1386
FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:146
ThreadContext::setMiscReg
virtual void setMiscReg(int misc_reg, const MiscReg &val)=0
ThreadContext::setIntReg
virtual void setIntReg(int reg_idx, uint64_t val)=0
SparcISA::ReturnAddressReg
const int ReturnAddressReg
Definition: registers.hh:67
ThreadContext::readFloatRegBits
virtual FloatRegBits readFloatRegBits(int reg_idx)=0
ThreadContext::pcState
virtual TheISA::PCState pcState()=0
SparcISA::MISCREG_MMU_P_CONTEXT
MMU Internal Registers.
Definition: miscregs.hh:89
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Definition: thread_context.hh:93
ThreadContext::setFloatRegBits
virtual void setFloatRegBits(int reg_idx, FloatRegBits val)=0
SparcISA::skipFunction
void skipFunction(ThreadContext *tc)
Definition: utility.cc:249
SparcISA::NumIntArchRegs
const int NumIntArchRegs
Definition: registers.hh:75
SparcISA::copyRegs
void copyRegs(ThreadContext *src, ThreadContext *dest)
Definition: utility.cc:204
MipsISA::tl
Bitfield< 23, 20 > tl
Definition: pra_constants.hh:253
SparcISA::getArgument
uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
Definition: utility.cc:48
SparcISA::initCPU
void initCPU(ThreadContext *tc, int cpuId)
Definition: utility.cc:258
ThreadContext::readIntReg
virtual uint64_t readIntReg(int reg_idx)=0
SparcISA::MISCREG_HPSTATE
Hyper privileged registers.
Definition: miscregs.hh:77
PortProxy::read
T read(Addr address) const
Read sizeof(T) bytes from address and return as object T.
Definition: port_proxy.hh:146
SparcISA::NumFloatArchRegs
const int NumFloatArchRegs
Definition: sparc_traits.hh:51
ArmISA::NumArgumentRegs
const int NumArgumentRegs
Definition: registers.hh:95
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
SparcISA::MISCREG_ASI
Ancillary State Registers.
Definition: miscregs.hh:45
ThreadContext::getVirtProxy
virtual FSTranslatingPortProxy & getVirtProxy()=0
X86ISA::size
int size()
Definition: pagetable.hh:146
SparcISA::MaxTL
const int MaxTL
Definition: sparc_traits.hh:38
SparcISA::MISCREG_TPC
Privilged Registers.
Definition: miscregs.hh:59
SparcISA::MISCREG_SCRATCHPAD_R0
Scratchpad regiscers.
Definition: miscregs.hh:95
AlphaISA::PCState
GenericISA::SimplePCState< MachInst > PCState
Definition: types.hh:43
SparcISA::NWindows
const int NWindows
Definition: sparc_traits.hh:43
SparcISA::StackPointerReg
const int StackPointerReg
Definition: registers.hh:69
fs_translating_port_proxy.hh
TranslatingPortProxy Object Declaration for FS.
SparcISA::NumMicroIntRegs
const int NumMicroIntRegs
Definition: sparc_traits.hh:45
SparcISA::NumCCRegs
const int NumCCRegs
Definition: registers.hh:77
SparcISA::copyMiscRegs
void copyMiscRegs(ThreadContext *src, ThreadContext *dest)
Definition: utility.cc:68
ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val)=0
X86ISA::x
Bitfield< 1 > x
Definition: types.hh:105
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:184
SparcISA::MISCREG_FSR
Floating Point Status Register.
Definition: miscregs.hh:86
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