gem5
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#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/registers.hh"
#include "arch/sparc/tlb.hh"
#include "base/bitfield.hh"
#include "base/misc.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/full_system.hh"
Go to the source code of this file.
Namespaces | |
SparcISA | |
Functions | |
PCState | SparcISA::buildRetPC (const PCState &curPC, const PCState &callPC) |
uint64_t | SparcISA::getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp) |
static bool | SparcISA::inUserMode (ThreadContext *tc) |
template<class TC > | |
void | SparcISA::zeroRegisters (TC *tc) |
Function to insure ISA semantics about 0 registers. More... | |
void | SparcISA::initCPU (ThreadContext *tc, int cpuId) |
void | SparcISA::startupCPU (ThreadContext *tc, int cpuId) |
void | SparcISA::copyRegs (ThreadContext *src, ThreadContext *dest) |
void | SparcISA::copyMiscRegs (ThreadContext *src, ThreadContext *dest) |
void | SparcISA::skipFunction (ThreadContext *tc) |
void | SparcISA::advancePC (PCState &pc, const StaticInstPtr &inst) |
uint64_t | SparcISA::getExecutingAsid (ThreadContext *tc) |