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mmapped_ipr.cc
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1 /*
2  * Copyright (c) 2013 Andreas Sandberg
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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27  *
28  * Authors: Andreas Sandberg
29  */
30 
32 
33 #include "mem/packet.hh"
34 #include "mem/packet_access.hh"
35 #include "sim/pseudo_inst.hh"
36 
37 using namespace GenericISA;
38 
39 static void
41 {
42  const Addr offset(pkt->getAddr() & IPR_IN_CLASS_MASK);
43  const uint8_t func((offset >> 8) & 0xFF);
44  const uint8_t subfunc(offset & 0xFF);
45  uint64_t ret;
46 
47  assert((offset >> 16) == 0);
48  ret = PseudoInst::pseudoInst(xc, func, subfunc);
49  if (pkt->isRead())
50  pkt->set(ret);
51 }
52 
53 Cycles
55 {
56  Addr va(pkt->getAddr());
57  Addr cls(va >> IPR_CLASS_SHIFT);
58 
59  switch (cls) {
61  handlePseudoInst(xc, pkt);
62  break;
63  default:
64  panic("Unhandled generic IPR read: 0x%x\n", va);
65  }
66 
67  return Cycles(1);
68 }
69 
70 Cycles
72 {
73  Addr va(pkt->getAddr());
74  Addr cls(va >> IPR_CLASS_SHIFT);
75 
76  switch (cls) {
78  handlePseudoInst(xc, pkt);
79  break;
80  default:
81  panic("Unhandled generic IPR write: 0x%x\n", va);
82  }
83 
84  return Cycles(1);
85 }
const Addr IPR_IN_CLASS_MASK
Mask to extract the offset in within a generic IPR class.
Definition: mmapped_ipr.hh:60
void set(T v, ByteOrder endian)
Set the value in the data pointer to v using the specified endianness.
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
const int IPR_CLASS_SHIFT
Memory requests with the MMAPPED_IPR flag are generally mapped to registers.
Definition: mmapped_ipr.hh:57
#define panic(...)
Definition: misc.hh:153
Bitfield< 23, 0 > offset
Definition: types.hh:149
Cycles handleGenericIprWrite(ThreadContext *xc, Packet *pkt)
Handle generic IPR writes.
Definition: mmapped_ipr.cc:71
ThreadContext is the external interface to all thread state for anything outside of the CPU...
static void handlePseudoInst(ThreadContext *xc, Packet *pkt)
Definition: mmapped_ipr.cc:40
bool isRead() const
Definition: packet.hh:502
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:245
uint64_t pseudoInst(ThreadContext *tc, uint8_t func, uint8_t subfunc)
Execute a decoded M5 pseudo instruction.
Definition: pseudo_inst.cc:95
Bitfield< 8 > va
Definition: miscregs.hh:1473
Declaration of the Packet class.
ISA-generic helper functions for memory mapped IPR accesses.
Cycles handleGenericIprRead(ThreadContext *xc, Packet *pkt)
Handle generic IPR reads.
Definition: mmapped_ipr.cc:54
const Addr IPR_CLASS_PSEUDO_INST
gem5 pseudo-inst emulation.
Definition: mmapped_ipr.hh:70
Addr getAddr() const
Definition: packet.hh:639

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