31 #ifndef __ARCH_GENERIC_MMAPPED_IPR_HH__
32 #define __ARCH_GENERIC_MMAPPED_IPR_HH__
87 (func << 8) | subfunc;
142 panic(
"Unhandled IPR access\n");
163 panic(
"Unhandled IPR access\n");
const Addr IPR_IN_CLASS_MASK
Mask to extract the offset in within a generic IPR class.
Cycles is a wrapper class for representing cycle counts, i.e.
const int IPR_CLASS_SHIFT
Memory requests with the MMAPPED_IPR flag are generally mapped to registers.
Cycles handleGenericIprWrite(ThreadContext *xc, Packet *pkt)
Handle generic IPR writes.
Cycles handleIprRead(ThreadContext *xc, Packet *pkt)
Helper function to handle IPRs when the target architecture doesn't need its own IPR handling...
Cycles handleIprWrite(ThreadContext *xc, Packet *pkt)
Helper function to handle IPRs when the target architecture doesn't need its own IPR handling...
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Addr iprAddressPseudoInst(uint8_t func, uint8_t subfunc)
Generate a generic IPR address that emulates a pseudo inst.
const RequestPtr req
A pointer to the original request.
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
#define ULL(N)
uint64_t constant
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Flags getFlags()
Accessor for flags.
Declaration of the Packet class.
Cycles handleGenericIprRead(ThreadContext *xc, Packet *pkt)
Handle generic IPR reads.
This request is to a memory mapped register.
The request should be handled by the generic IPR code (only valid together with MMAPPED_IPR) ...
const Addr IPR_CLASS_PSEUDO_INST
gem5 pseudo-inst emulation.
bool isGenericIprAccess(const Packet *pkt)
Check if this is an platform independent IPR access.