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mmapped_ipr.hh
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1 /*
2  * Copyright (c) 2013 Andreas Sandberg
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30 
31 #ifndef __ARCH_GENERIC_MMAPPED_IPR_HH__
32 #define __ARCH_GENERIC_MMAPPED_IPR_HH__
33 
34 #include "base/types.hh"
35 #include "mem/packet.hh"
36 
37 class ThreadContext;
38 
45 namespace GenericISA
46 {
57  const int IPR_CLASS_SHIFT = 48;
58 
60  const Addr IPR_IN_CLASS_MASK = ULL(0x0000FFFFFFFFFFFF);
61 
71 
83  inline Addr
84  iprAddressPseudoInst(uint8_t func, uint8_t subfunc)
85  {
87  (func << 8) | subfunc;
88  }
89 
102  inline bool
104  {
105  Request::Flags flags(pkt->req->getFlags());
106  return (flags & Request::MMAPPED_IPR) &&
107  (flags & Request::GENERIC_IPR);
108  }
109 
126 
138  inline Cycles
140  {
141  if (!isGenericIprAccess(pkt))
142  panic("Unhandled IPR access\n");
143 
144  return handleGenericIprRead(xc, pkt);
145  }
146 
147 
159  inline Cycles
161  {
162  if (!isGenericIprAccess(pkt))
163  panic("Unhandled IPR access\n");
164 
165  return handleGenericIprWrite(xc, pkt);
166  }
167 
168 } // namespace GenericISA
169 
170 
171 
172 #endif
const Addr IPR_IN_CLASS_MASK
Mask to extract the offset in within a generic IPR class.
Definition: mmapped_ipr.hh:60
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
const int IPR_CLASS_SHIFT
Memory requests with the MMAPPED_IPR flag are generally mapped to registers.
Definition: mmapped_ipr.hh:57
#define panic(...)
Definition: misc.hh:153
Cycles handleGenericIprWrite(ThreadContext *xc, Packet *pkt)
Handle generic IPR writes.
Definition: mmapped_ipr.cc:71
Cycles handleIprRead(ThreadContext *xc, Packet *pkt)
Helper function to handle IPRs when the target architecture doesn't need its own IPR handling...
Definition: mmapped_ipr.hh:139
Cycles handleIprWrite(ThreadContext *xc, Packet *pkt)
Helper function to handle IPRs when the target architecture doesn't need its own IPR handling...
Definition: mmapped_ipr.hh:160
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Addr iprAddressPseudoInst(uint8_t func, uint8_t subfunc)
Generate a generic IPR address that emulates a pseudo inst.
Definition: mmapped_ipr.hh:84
const RequestPtr req
A pointer to the original request.
Definition: packet.hh:304
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
#define ULL(N)
uint64_t constant
Definition: types.hh:50
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:245
Flags getFlags()
Accessor for flags.
Definition: request.hh:584
Declaration of the Packet class.
Cycles handleGenericIprRead(ThreadContext *xc, Packet *pkt)
Handle generic IPR reads.
Definition: mmapped_ipr.cc:54
This request is to a memory mapped register.
Definition: request.hh:126
The request should be handled by the generic IPR code (only valid together with MMAPPED_IPR) ...
Definition: request.hh:178
const Addr IPR_CLASS_PSEUDO_INST
gem5 pseudo-inst emulation.
Definition: mmapped_ipr.hh:70
bool isGenericIprAccess(const Packet *pkt)
Check if this is an platform independent IPR access.
Definition: mmapped_ipr.hh:103

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