CheckerCPU Class Reference

CheckerCPU class. More...

#include <cpu.hh>

Inheritance diagram for CheckerCPU:

Classes
union	Result

Public Types
typedef CheckerCPUParams	Params
Public Types inherited from ExecContext
typedef TheISA::IntReg	IntReg
typedef TheISA::PCState	PCState
typedef TheISA::FloatReg	FloatReg
typedef TheISA::FloatRegBits	FloatRegBits
typedef TheISA::MiscReg	MiscReg
typedef TheISA::CCReg	CCReg

Public Member Functions
void	init () override
	CheckerCPU (Params *p)
virtual	~CheckerCPU ()
void	setSystem (System *system)
void	setIcachePort (MasterPort *icache_port)
void	setDcachePort (MasterPort *dcache_port)
MasterPort &	getDataPort () override
MasterPort &	getInstPort () override
TheISA::TLB *	getITBPtr ()
TheISA::TLB *	getDTBPtr ()
virtual Counter	totalInsts () const override
virtual Counter	totalOps () const override
void	serialize (CheckpointOut &cp) const override
void	unserialize (CheckpointIn &cp) override
void	setEA (Addr EA) override
	Record the effective address of the instruction. More...
Addr	getEA () const override
	Get the effective address of the instruction. More...
IntReg	readIntRegOperand (const StaticInst *si, int idx) override
	Reads an integer register. More...
FloatReg	readFloatRegOperand (const StaticInst *si, int idx) override
	Reads a floating point register of single register width. More...
FloatRegBits	readFloatRegOperandBits (const StaticInst *si, int idx) override
	Reads a floating point register in its binary format, instead of by value. More...
CCReg	readCCRegOperand (const StaticInst *si, int idx) override
template<class T >
void	setResult (T t)
void	setIntRegOperand (const StaticInst *si, int idx, IntReg val) override
	Sets an integer register to a value. More...
void	setFloatRegOperand (const StaticInst *si, int idx, FloatReg val) override
	Sets a floating point register of single width to a value. More...
void	setFloatRegOperandBits (const StaticInst *si, int idx, FloatRegBits val) override
	Sets the bits of a floating point register of single width to a binary value. More...
void	setCCRegOperand (const StaticInst *si, int idx, CCReg val) override
bool	readPredicate () override
void	setPredicate (bool val) override
TheISA::PCState	pcState () const override
void	pcState (const TheISA::PCState &val) override
Addr	instAddr ()
Addr	nextInstAddr ()
MicroPC	microPC ()
MiscReg	readMiscRegNoEffect (int misc_reg) const
MiscReg	readMiscReg (int misc_reg) override
	Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...
void	setMiscRegNoEffect (int misc_reg, const MiscReg &val)
void	setMiscReg (int misc_reg, const MiscReg &val) override
	Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...
MiscReg	readMiscRegOperand (const StaticInst *si, int idx) override
void	setMiscRegOperand (const StaticInst *si, int idx, const MiscReg &val) override
MiscReg	readRegOtherThread (int misc_reg, ThreadID tid) override
void	setRegOtherThread (int misc_reg, MiscReg val, ThreadID tid) override
void	recordPCChange (const TheISA::PCState &val)
void	demapPage (Addr vaddr, uint64_t asn) override
	Invalidate a page in the DTLB and ITLB. More...
void	armMonitor (Addr address) override
bool	mwait (PacketPtr pkt) override
void	mwaitAtomic (ThreadContext *tc) override
AddressMonitor *	getAddrMonitor () override
void	demapInstPage (Addr vaddr, uint64_t asn)
void	demapDataPage (Addr vaddr, uint64_t asn)
Fault	readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags) override
Fault	writeMem (uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res) override
unsigned int	readStCondFailures () const override
	Returns the number of consecutive store conditional failures. More...
void	setStCondFailures (unsigned int sc_failures) override
	Sets the number of consecutive store conditional failures. More...
Fault	hwrei () override
	Somewhat Alpha-specific function that handles returning from an error or interrupt. More...
bool	simPalCheck (int palFunc) override
	Check for special simulator handling of specific PAL calls. More...
void	wakeup (ThreadID tid) override
void	syscall (int64_t callnum, Fault *fault) override
	Executes a syscall specified by the callnum. More...
void	handleError ()
bool	checkFlags (Request *unverified_req, Addr vAddr, Addr pAddr, int flags)
	Checks if the flags set by the Checker and Checkee match. More...
void	dumpAndExit ()
ThreadContext *	tcBase () override
	Returns a pointer to the ThreadContext. More...
SimpleThread *	threadBase ()
Public Member Functions inherited from ExecContext
virtual Fault	readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags)
	Perform an atomic memory read operation. More...
virtual Fault	initiateMemRead (Addr addr, unsigned int size, Request::Flags flags)
	Initiate a timing memory read operation. More...
virtual Fault	writeMem (uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res)=0
	For atomic-mode contexts, perform an atomic memory write operation. More...

Public Attributes
SimpleThread *	thread
Counter	numLoad
Counter	startNumLoad
Result	unverifiedResult
Request *	unverifiedReq
uint8_t *	unverifiedMemData
bool	changedPC
bool	willChangePC
TheISA::PCState	newPCState
bool	exitOnError
bool	updateOnError
bool	warnOnlyOnLoadError
InstSeqNum	youngestSN

Protected Types
typedef TheISA::MachInst	MachInst
typedef TheISA::FloatReg	FloatReg
typedef TheISA::FloatRegBits	FloatRegBits
typedef TheISA::MiscReg	MiscReg

Protected Member Functions
Addr	dbg_vtophys (Addr addr)

Protected Attributes
MasterID	masterId
	id attached to all issued requests More...
std::vector< Process * >	workload
System *	systemPtr
MasterPort *	icachePort
MasterPort *	dcachePort
ThreadContext *	tc
TheISA::TLB *	itb
TheISA::TLB *	dtb
std::queue< Result >	result
RequestPtr	memReq
StaticInstPtr	curStaticInst
StaticInstPtr	curMacroStaticInst
Counter	numInst
Counter	startNumInst
std::queue< int >	miscRegIdxs

Additional Inherited Members
Static Public Member Functions inherited from BaseCPU
static int	numSimulatedInsts ()
static int	numSimulatedOps ()
static void	wakeup (ThreadID tid)

Detailed Description

CheckerCPU class.

Dynamically verifies instructions as they are completed by making sure that the instruction and its results match the independent execution of the benchmark inside the checker. The checker verifies instructions in order, regardless of the order in which instructions complete. There are certain results that can not be verified, specifically the result of a store conditional or the values of uncached accesses. In these cases, and with instructions marked as "IsUnverifiable", the checker assumes that the value from the main CPU's execution is correct and simply copies that value. It provides a CheckerThreadContext (see checker/thread_context.hh) that provides hooks for updating the Checker's state through any ThreadContext accesses. This allows the checker to be able to correctly verify instructions, even with external accesses to the ThreadContext that change state.

Definition at line 91 of file cpu.hh.

Member Typedef Documentation

typedef TheISA::FloatReg CheckerCPU::FloatReg

protected

Definition at line 95 of file cpu.hh.

typedef TheISA::FloatRegBits CheckerCPU::FloatRegBits

protected

Definition at line 96 of file cpu.hh.

typedef TheISA::MachInst CheckerCPU::MachInst

protected

Definition at line 94 of file cpu.hh.

typedef TheISA::MiscReg CheckerCPU::MiscReg

protected

Definition at line 97 of file cpu.hh.

typedef CheckerCPUParams CheckerCPU::Params

Definition at line 104 of file cpu.hh.

Constructor & Destructor Documentation

CheckerCPU::CheckerCPU

(

Params *

p

)

Definition at line 68 of file cpu.cc.

References changedPC, curMacroStaticInst, curStaticInst, dtb, exitOnError, itb, memReq, numInst, numLoad, startNumInst, startNumLoad, updateOnError, warnOnlyOnLoadError, willChangePC, workload, and youngestSN.

CheckerCPU::~CheckerCPU ( )

virtual

Definition at line 93 of file cpu.cc.

Member Function Documentation

void CheckerCPU::armMonitor ( Addr  address )

inlineoverridevirtual

Implements ExecContext.

Definition at line 359 of file cpu.hh.

bool CheckerCPU::checkFlags	(	Request *	unverified_req,
		Addr	vAddr,
		Addr	pAddr,
		int	flags
	)

Checks if the flags set by the Checker and Checkee match.

Definition at line 340 of file cpu.cc.

References Request::getFlags(), Request::getPaddr(), and Request::getVaddr().

Referenced by readMem(), and writeMem().

Addr CheckerCPU::dbg_vtophys ( Addr  addr )

protected

Definition at line 331 of file cpu.cc.

References tc, and AlphaISA::vtophys().

void CheckerCPU::demapDataPage ( Addr  vaddr, uint64_t  asn  )

inline

Definition at line 372 of file cpu.hh.

References dtb.

void CheckerCPU::demapInstPage ( Addr  vaddr, uint64_t  asn  )

inline

Definition at line 367 of file cpu.hh.

References itb.

void CheckerCPU::demapPage ( Addr  vaddr, uint64_t  asn  )

inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements ExecContext.

Definition at line 352 of file cpu.hh.

References dtb, and itb.

void CheckerCPU::dumpAndExit

(

)

Definition at line 357 of file cpu.cc.

References curTick(), panic, SimpleThread::pcState(), thread, and warn.

Referenced by Checker< Impl >::dumpAndExit(), handleError(), and Checker< O3CPUImpl >::handleError().

AddressMonitor* CheckerCPU::getAddrMonitor ( )

inlineoverridevirtual

Implements ExecContext.

Definition at line 364 of file cpu.hh.

MasterPort& CheckerCPU::getDataPort ( )

inlineoverride

Definition at line 114 of file cpu.hh.

References dcachePort.

TheISA::TLB* CheckerCPU::getDTBPtr ( )

inline

Definition at line 177 of file cpu.hh.

References dtb.

Referenced by ArmISA::ISA::setMiscReg(), ArmISA::ISA::tlbiALL(), ArmISA::ISA::tlbiALLN(), ArmISA::ISA::tlbiMVA(), and ArmISA::ISA::tlbiVA().

Addr CheckerCPU::getEA ( ) const

inlineoverridevirtual

Get the effective address of the instruction.

Note

Only valid for memory ops.

Implements ExecContext.

Definition at line 200 of file cpu.hh.

References panic.

MasterPort& CheckerCPU::getInstPort ( )

inlineoverride

Definition at line 122 of file cpu.hh.

References icachePort.

TheISA::TLB* CheckerCPU::getITBPtr ( )

inline

Definition at line 176 of file cpu.hh.

References itb.

Referenced by ArmISA::ISA::setMiscReg(), ArmISA::ISA::tlbiALL(), ArmISA::ISA::tlbiALLN(), ArmISA::ISA::tlbiMVA(), and ArmISA::ISA::tlbiVA().

void CheckerCPU::handleError ( )

inline

Definition at line 398 of file cpu.hh.

References dumpAndExit(), and exitOnError.

Referenced by readMem(), Checker< Impl >::verify(), and writeMem().

Fault CheckerCPU::hwrei ( )

inlineoverridevirtual

Somewhat Alpha-specific function that handles returning from an error or interrupt.

Implements ExecContext.

Definition at line 390 of file cpu.hh.

References SimpleThread::hwrei(), and thread.

void CheckerCPU::init ( )

override

Definition at line 63 of file cpu.cc.

References name().

Addr CheckerCPU::instAddr ( )

inline

Definition at line 289 of file cpu.hh.

References SimpleThread::instAddr(), and thread.

MicroPC CheckerCPU::microPC ( )

inline

Definition at line 291 of file cpu.hh.

References SimpleThread::microPC(), and thread.

bool CheckerCPU::mwait ( PacketPtr  pkt )

inlineoverridevirtual

Implements ExecContext.

Definition at line 361 of file cpu.hh.

void CheckerCPU::mwaitAtomic ( ThreadContext *  tc )

inlineoverridevirtual

Implements ExecContext.

Definition at line 362 of file cpu.hh.

References SimpleThread::dtb, and thread.

Addr CheckerCPU::nextInstAddr ( )

inline

Definition at line 290 of file cpu.hh.

References SimpleThread::nextInstAddr(), and thread.

TheISA::PCState CheckerCPU::pcState ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 282 of file cpu.hh.

References SimpleThread::pcState(), and thread.

Referenced by Checker< Impl >::advancePC(), Checker< Impl >::handlePendingInt(), and Checker< Impl >::verify().

void CheckerCPU::pcState ( const TheISA::PCState &  val )

inlineoverridevirtual

Implements ExecContext.

Definition at line 283 of file cpu.hh.

References DPRINTF, SimpleThread::pcState(), and thread.

CCReg CheckerCPU::readCCRegOperand ( const StaticInst *  si, int  idx  )

inlineoverridevirtual

Implements ExecContext.

Definition at line 232 of file cpu.hh.

References AlphaISA::CC_Reg_Base, SimpleThread::readCCReg(), StaticInst::srcRegIdx(), and thread.

FloatReg CheckerCPU::readFloatRegOperand ( const StaticInst *  si, int  idx  )

inlineoverridevirtual

Reads a floating point register of single register width.

Implements ExecContext.

Definition at line 219 of file cpu.hh.

References AlphaISA::FP_Reg_Base, SimpleThread::readFloatReg(), StaticInst::srcRegIdx(), and thread.

FloatRegBits CheckerCPU::readFloatRegOperandBits ( const StaticInst *  si, int  idx  )

inlineoverridevirtual

Reads a floating point register in its binary format, instead of by value.

Implements ExecContext.

Definition at line 225 of file cpu.hh.

References AlphaISA::FP_Reg_Base, SimpleThread::readFloatRegBits(), StaticInst::srcRegIdx(), and thread.

IntReg CheckerCPU::readIntRegOperand ( const StaticInst *  si, int  idx  )

inlineoverridevirtual

Reads an integer register.

Implements ExecContext.

Definition at line 214 of file cpu.hh.

References SimpleThread::readIntReg(), StaticInst::srcRegIdx(), and thread.

Fault CheckerCPU::readMem ( Addr  addr, uint8_t *  data, unsigned  size, Request::Flags  flags  )

override

Definition at line 143 of file cpu.cc.

References addr, checkFlags(), ThreadContext::contextId(), Packet::createRead(), curTick(), Packet::dataStatic(), dcachePort, dtb, Request::getFlags(), Request::getPaddr(), Request::getVaddr(), handleError(), Request::isMmappedIpr(), Request::isPrefetch(), Flags< T >::isSet(), Request::isUncacheable(), masterId, memReq, Request::NO_ACCESS, NoFault, SimpleThread::pcState(), BaseTLB::Read, roundDown(), MasterPort::sendFunctional(), X86ISA::size(), tc, thread, unverifiedMemData, unverifiedReq, and warn.

MiscReg CheckerCPU::readMiscReg ( int  misc_reg )

inlineoverridevirtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implements ExecContext.

Definition at line 299 of file cpu.hh.

References SimpleThread::readMiscReg(), and thread.

MiscReg CheckerCPU::readMiscRegNoEffect ( int  misc_reg ) const

inline

Definition at line 294 of file cpu.hh.

References SimpleThread::readMiscRegNoEffect(), and thread.

MiscReg CheckerCPU::readMiscRegOperand ( const StaticInst *  si, int  idx  )

inlineoverridevirtual

Implements ExecContext.

Definition at line 318 of file cpu.hh.

References AlphaISA::Misc_Reg_Base, SimpleThread::readMiscReg(), StaticInst::srcRegIdx(), and thread.

bool CheckerCPU::readPredicate ( )

inlineoverridevirtual

Implements ExecContext.

Definition at line 276 of file cpu.hh.

References SimpleThread::readPredicate(), and thread.

MiscReg CheckerCPU::readRegOtherThread ( int  misc_reg, ThreadID  tid  )

inlineoverridevirtual

Implements ExecContext.

Definition at line 332 of file cpu.hh.

References panic.

unsigned int CheckerCPU::readStCondFailures ( ) const

inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 382 of file cpu.hh.

References SimpleThread::readStCondFailures(), and thread.

void CheckerCPU::recordPCChange ( const TheISA::PCState &  val )

inline

Definition at line 346 of file cpu.hh.

References changedPC, newPCState, and X86ISA::val.

Referenced by CheckerThreadContext< TC >::pcState().

void CheckerCPU::serialize ( CheckpointOut &  cp ) const

override

Definition at line 133 of file cpu.cc.

void CheckerCPU::setCCRegOperand ( const StaticInst *  si, int  idx, CCReg  val  )

inlineoverridevirtual

Implements ExecContext.

Definition at line 269 of file cpu.hh.

References AlphaISA::CC_Reg_Base, StaticInst::destRegIdx(), SimpleThread::setCCReg(), thread, and X86ISA::val.

void CheckerCPU::setDcachePort

(

MasterPort *

dcache_port

)

Definition at line 127 of file cpu.cc.

References dcachePort.

void CheckerCPU::setEA ( Addr  EA )

inlineoverridevirtual

Record the effective address of the instruction.

Note

Only valid for memory ops.

Implements ExecContext.

Definition at line 198 of file cpu.hh.

References panic.

void CheckerCPU::setFloatRegOperand ( const StaticInst *  si, int  idx, FloatReg  val  )

inlineoverridevirtual

Sets a floating point register of single width to a value.

Implements ExecContext.

Definition at line 253 of file cpu.hh.

References StaticInst::destRegIdx(), AlphaISA::FP_Reg_Base, SimpleThread::setFloatReg(), thread, and X86ISA::val.

void CheckerCPU::setFloatRegOperandBits ( const StaticInst *  si, int  idx, FloatRegBits  val  )

inlineoverridevirtual

Sets the bits of a floating point register of single width to a binary value.

Implements ExecContext.

Definition at line 261 of file cpu.hh.

References StaticInst::destRegIdx(), AlphaISA::FP_Reg_Base, SimpleThread::setFloatRegBits(), thread, and X86ISA::val.

void CheckerCPU::setIcachePort

(

MasterPort *

icache_port

)

Definition at line 121 of file cpu.cc.

References icachePort.

void CheckerCPU::setIntRegOperand ( const StaticInst *  si, int  idx, IntReg  val  )

inlineoverridevirtual

Sets an integer register to a value.

Implements ExecContext.

Definition at line 246 of file cpu.hh.

References StaticInst::destRegIdx(), SimpleThread::setIntReg(), thread, and X86ISA::val.

void CheckerCPU::setMiscReg ( int  misc_reg, const MiscReg &  val  )

inlineoverridevirtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implements ExecContext.

Definition at line 311 of file cpu.hh.

References DPRINTF, miscRegIdxs, SimpleThread::setMiscReg(), and thread.

Referenced by setMiscRegOperand().

void CheckerCPU::setMiscRegNoEffect ( int  misc_reg, const MiscReg &  val  )

inline

Definition at line 304 of file cpu.hh.

References DPRINTF, miscRegIdxs, SimpleThread::setMiscRegNoEffect(), and thread.

void CheckerCPU::setMiscRegOperand ( const StaticInst *  si, int  idx, const MiscReg &  val  )

inlineoverridevirtual

Implements ExecContext.

Definition at line 324 of file cpu.hh.

References StaticInst::destRegIdx(), AlphaISA::Misc_Reg_Base, and setMiscReg().

void CheckerCPU::setPredicate ( bool  val )

inlineoverridevirtual

Implements ExecContext.

Definition at line 277 of file cpu.hh.

References SimpleThread::setPredicate(), and thread.

void CheckerCPU::setRegOtherThread ( int  misc_reg, MiscReg  val, ThreadID  tid  )

inlineoverridevirtual

Implements ExecContext.

Definition at line 338 of file cpu.hh.

References panic.

template<class T >

void CheckerCPU::setResult ( T  t )

inline

Definition at line 239 of file cpu.hh.

References result, and CheckerCPU::Result::set().

void CheckerCPU::setStCondFailures ( unsigned int  sc_failures )

inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 386 of file cpu.hh.

void CheckerCPU::setSystem

(

System *

system

)

Definition at line 98 of file cpu.cc.

References dtb, FullSystem, SimpleThread::getTC(), itb, ThreadState::kernelStats, MipsISA::p, ArmISA::system, systemPtr, tc, thread, and workload.

Referenced by BaseSimpleCPU::BaseSimpleCPU().

bool CheckerCPU::simPalCheck ( int  palFunc )

inlineoverridevirtual

Check for special simulator handling of specific PAL calls.

If return value is false, actual PAL call will be suppressed.

Implements ExecContext.

Definition at line 391 of file cpu.hh.

References SimpleThread::simPalCheck(), and thread.

void CheckerCPU::syscall ( int64_t  callnum, Fault *  fault  )

inlineoverridevirtual

Executes a syscall specified by the callnum.

Implements ExecContext.

Definition at line 396 of file cpu.hh.

ThreadContext* CheckerCPU::tcBase ( )

inlineoverridevirtual

Returns a pointer to the ThreadContext.

Implements ExecContext.

Definition at line 409 of file cpu.hh.

References tc.

SimpleThread* CheckerCPU::threadBase ( )

inline

Definition at line 410 of file cpu.hh.

References thread.

virtual Counter CheckerCPU::totalInsts ( ) const

inlineoverridevirtual

Definition at line 179 of file cpu.hh.

virtual Counter CheckerCPU::totalOps ( ) const

inlineoverridevirtual

Definition at line 184 of file cpu.hh.

void CheckerCPU::unserialize ( CheckpointIn &  cp )

override

Definition at line 138 of file cpu.cc.

void CheckerCPU::wakeup ( ThreadID  tid )

inlineoverride

Definition at line 393 of file cpu.hh.

Fault CheckerCPU::writeMem ( uint8_t *  data, unsigned  size, Addr  addr, Request::Flags  flags, uint64_t *  res  )

override

Definition at line 229 of file cpu.cc.

References addr, Request::CACHE_BLOCK_ZERO, checkFlags(), ThreadContext::contextId(), curTick(), dtb, Request::extraDataValid(), Request::getExtraData(), Request::getFlags(), Request::getPaddr(), Request::getVaddr(), handleError(), Request::isPrefetch(), masterId, memReq, NoFault, SimpleThread::pcState(), roundDown(), X86ISA::size(), tc, thread, unverifiedMemData, unverifiedReq, warn, and BaseTLB::Write.

Member Data Documentation

bool CheckerCPU::changedPC

Definition at line 416 of file cpu.hh.

Referenced by CheckerCPU(), and recordPCChange().

StaticInstPtr CheckerCPU::curMacroStaticInst

protected

Definition at line 163 of file cpu.hh.

Referenced by CheckerCPU().

StaticInstPtr CheckerCPU::curStaticInst

protected

Definition at line 162 of file cpu.hh.

Referenced by CheckerCPU().

MasterPort* CheckerCPU::dcachePort

protected

Definition at line 137 of file cpu.hh.

Referenced by getDataPort(), readMem(), and setDcachePort().

TheISA::TLB* CheckerCPU::dtb

protected

Definition at line 142 of file cpu.hh.

Referenced by CheckerCPU(), demapDataPage(), demapPage(), getDTBPtr(), readMem(), setSystem(), and writeMem().

bool CheckerCPU::exitOnError

Definition at line 419 of file cpu.hh.

Referenced by CheckerCPU(), handleError(), and Checker< O3CPUImpl >::handleError().

MasterPort* CheckerCPU::icachePort

protected

Definition at line 136 of file cpu.hh.

Referenced by getInstPort(), and setIcachePort().

TheISA::TLB* CheckerCPU::itb

protected

Definition at line 141 of file cpu.hh.

Referenced by CheckerCPU(), demapInstPage(), demapPage(), getITBPtr(), and setSystem().

MasterID CheckerCPU::masterId

protected

id attached to all issued requests

Definition at line 100 of file cpu.hh.

Referenced by readMem(), and writeMem().

RequestPtr CheckerCPU::memReq

protected

Definition at line 160 of file cpu.hh.

Referenced by CheckerCPU(), readMem(), and writeMem().

std::queue<int> CheckerCPU::miscRegIdxs

protected

Definition at line 169 of file cpu.hh.

Referenced by setMiscReg(), and setMiscRegNoEffect().

TheISA::PCState CheckerCPU::newPCState

Definition at line 418 of file cpu.hh.

Referenced by recordPCChange().

Counter CheckerCPU::numInst

protected

Definition at line 166 of file cpu.hh.

Referenced by CheckerCPU().

Counter CheckerCPU::numLoad

Definition at line 190 of file cpu.hh.

Referenced by CheckerCPU().

std::queue<Result> CheckerCPU::result

protected

Definition at line 157 of file cpu.hh.

Referenced by setResult().

Counter CheckerCPU::startNumInst

protected

Definition at line 167 of file cpu.hh.

Referenced by CheckerCPU().

Counter CheckerCPU::startNumLoad

Definition at line 191 of file cpu.hh.

Referenced by CheckerCPU().

System* CheckerCPU::systemPtr

protected

Definition at line 134 of file cpu.hh.

Referenced by setSystem().

ThreadContext* CheckerCPU::tc

protected

Definition at line 139 of file cpu.hh.

Referenced by dbg_vtophys(), readMem(), setSystem(), tcBase(), and writeMem().

SimpleThread* CheckerCPU::thread

Definition at line 174 of file cpu.hh.

Referenced by dumpAndExit(), hwrei(), instAddr(), microPC(), mwaitAtomic(), nextInstAddr(), pcState(), readCCRegOperand(), readFloatRegOperand(), readFloatRegOperandBits(), readIntRegOperand(), readMem(), readMiscReg(), readMiscRegNoEffect(), readMiscRegOperand(), readPredicate(), readStCondFailures(), setCCRegOperand(), setFloatRegOperand(), setFloatRegOperandBits(), setIntRegOperand(), setMiscReg(), setMiscRegNoEffect(), setPredicate(), setSystem(), simPalCheck(), threadBase(), and writeMem().

uint8_t* CheckerCPU::unverifiedMemData

Definition at line 414 of file cpu.hh.

Referenced by readMem(), and writeMem().

Request* CheckerCPU::unverifiedReq

Definition at line 413 of file cpu.hh.

Referenced by readMem(), and writeMem().

Result CheckerCPU::unverifiedResult

Definition at line 412 of file cpu.hh.

bool CheckerCPU::updateOnError

Definition at line 420 of file cpu.hh.

Referenced by CheckerCPU(), and Checker< O3CPUImpl >::handleError().

bool CheckerCPU::warnOnlyOnLoadError

Definition at line 421 of file cpu.hh.

Referenced by CheckerCPU().

bool CheckerCPU::willChangePC

Definition at line 417 of file cpu.hh.

Referenced by CheckerCPU().

std::vector<Process*> CheckerCPU::workload

protected

Definition at line 132 of file cpu.hh.

Referenced by CheckerCPU(), and setSystem().

InstSeqNum CheckerCPU::youngestSN

Definition at line 423 of file cpu.hh.

Referenced by CheckerCPU().

---

The documentation for this class was generated from the following files:

• cpu/checker/cpu.hh
• cpu/checker/cpu.cc