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gem5
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DefaultIEW handles both single threaded and SMT IEW (issue/execute/writeback). More...
#include <iew.hh>
Public Types | |
| enum | Status { Active, Inactive } |
| Overall IEW stage status. More... | |
| enum | StageStatus { Running, Blocked, Idle, StartSquash, Squashing, Unblocking } |
| Status for Issue, Execute, and Writeback stages. More... | |
Public Member Functions | |
| DefaultIEW (O3CPU *_cpu, DerivO3CPUParams *params) | |
| Constructs a DefaultIEW with the given parameters. More... | |
| std::string | name () const |
| Returns the name of the DefaultIEW stage. More... | |
| void | regStats () |
| Registers statistics. More... | |
| void | regProbePoints () |
| Registers probes. More... | |
| void | startupStage () |
| Initializes stage; sends back the number of free IQ and LSQ entries. More... | |
| void | setTimeBuffer (TimeBuffer< TimeStruct > *tb_ptr) |
| Sets main time buffer used for backwards communication. More... | |
| void | setRenameQueue (TimeBuffer< RenameStruct > *rq_ptr) |
| Sets time buffer for getting instructions coming from rename. More... | |
| void | setIEWQueue (TimeBuffer< IEWStruct > *iq_ptr) |
| Sets time buffer to pass on instructions to commit. More... | |
| void | setActiveThreads (std::list< ThreadID > *at_ptr) |
| Sets pointer to list of active threads. More... | |
| void | setScoreboard (Scoreboard *sb_ptr) |
| Sets pointer to the scoreboard. More... | |
| void | drainSanityCheck () const |
| Perform sanity checks after a drain. More... | |
| bool | isDrained () const |
| Has the stage drained? More... | |
| void | takeOverFrom () |
| Takes over from another CPU's thread. More... | |
| void | squash (ThreadID tid) |
| Squashes instructions in IEW for a specific thread. More... | |
| void | wakeDependents (DynInstPtr &inst) |
| Wakes all dependents of a completed instruction. More... | |
| void | rescheduleMemInst (DynInstPtr &inst) |
| Tells memory dependence unit that a memory instruction needs to be rescheduled. More... | |
| void | replayMemInst (DynInstPtr &inst) |
| Re-executes all rescheduled memory instructions. More... | |
| void | blockMemInst (DynInstPtr &inst) |
| Moves memory instruction onto the list of cache blocked instructions. More... | |
| void | cacheUnblocked () |
| Notifies that the cache has become unblocked. More... | |
| void | instToCommit (DynInstPtr &inst) |
| Sends an instruction to commit through the time buffer. More... | |
| void | skidInsert (ThreadID tid) |
| Inserts unused instructions of a thread into the skid buffer. More... | |
| int | skidCount () |
| Returns the max of the number of entries in all of the skid buffers. More... | |
| bool | skidsEmpty () |
| Returns if all of the skid buffers are empty. More... | |
| void | updateStatus () |
| Updates overall IEW status based on all of the stages' statuses. More... | |
| void | resetEntries () |
| Resets entries of the IQ and the LSQ. More... | |
| void | wakeCPU () |
| Tells the CPU to wakeup if it has descheduled itself due to no activity. More... | |
| void | activityThisCycle () |
| Reports to the CPU that there is activity this cycle. More... | |
| void | activateStage () |
| Tells CPU that the IEW stage is active and running. More... | |
| void | deactivateStage () |
| Tells CPU that the IEW stage is inactive and idle. More... | |
| bool | hasStoresToWB () |
| Returns if the LSQ has any stores to writeback. More... | |
| bool | hasStoresToWB (ThreadID tid) |
| Returns if the LSQ has any stores to writeback. More... | |
| void | checkMisprediction (DynInstPtr &inst) |
| Check misprediction. More... | |
| void | tick () |
| Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle. More... | |
Public Attributes | |
| IQ | instQueue |
| Instruction queue. More... | |
| LSQ | ldstQueue |
| Load / store queue. More... | |
| FUPool * | fuPool |
| Pointer to the functional unit pool. More... | |
| bool | updateLSQNextCycle |
| Records if the LSQ needs to be updated on the next cycle, so that IEW knows if there will be activity on the next cycle. More... | |
Private Types | |
| typedef Impl::CPUPol | CPUPol |
| typedef Impl::DynInstPtr | DynInstPtr |
| typedef Impl::O3CPU | O3CPU |
| typedef CPUPol::IQ | IQ |
| typedef CPUPol::RenameMap | RenameMap |
| typedef CPUPol::LSQ | LSQ |
| typedef CPUPol::TimeStruct | TimeStruct |
| typedef CPUPol::IEWStruct | IEWStruct |
| typedef CPUPol::RenameStruct | RenameStruct |
| typedef CPUPol::IssueStruct | IssueStruct |
Private Member Functions | |
| void | squashDueToBranch (DynInstPtr &inst, ThreadID tid) |
| Sends commit proper information for a squash due to a branch mispredict. More... | |
| void | squashDueToMemOrder (DynInstPtr &inst, ThreadID tid) |
| Sends commit proper information for a squash due to a memory order violation. More... | |
| void | block (ThreadID tid) |
| Sets Dispatch to blocked, and signals back to other stages to block. More... | |
| void | unblock (ThreadID tid) |
| Unblocks Dispatch if the skid buffer is empty, and signals back to other stages to unblock. More... | |
| void | dispatch (ThreadID tid) |
| Determines proper actions to take given Dispatch's status. More... | |
| void | dispatchInsts (ThreadID tid) |
| Dispatches instructions to IQ and LSQ. More... | |
| void | executeInsts () |
| Executes instructions. More... | |
| void | writebackInsts () |
| Writebacks instructions. More... | |
| unsigned | validInstsFromRename () |
| Returns the number of valid, non-squashed instructions coming from rename to dispatch. More... | |
| bool | checkStall (ThreadID tid) |
| Checks if any of the stall conditions are currently true. More... | |
| void | checkSignalsAndUpdate (ThreadID tid) |
| Processes inputs and changes state accordingly. More... | |
| void | emptyRenameInsts (ThreadID tid) |
| Removes instructions from rename from a thread's instruction list. More... | |
| void | sortInsts () |
| Sorts instructions coming from rename into lists separated by thread. More... | |
| void | updateExeInstStats (DynInstPtr &inst) |
| Updates execution stats based on the instruction. More... | |
| void | printAvailableInsts () |
| Debug function to print instructions that are issued this cycle. More... | |
Private Attributes | |
| Status | _status |
| Overall stage status. More... | |
| StageStatus | dispatchStatus [Impl::MaxThreads] |
| Dispatch status. More... | |
| StageStatus | exeStatus |
| Execute status. More... | |
| StageStatus | wbStatus |
| Writeback status. More... | |
| ProbePointArg< DynInstPtr > * | ppMispredict |
| Probe points. More... | |
| ProbePointArg< DynInstPtr > * | ppDispatch |
| ProbePointArg< DynInstPtr > * | ppExecute |
| To probe when instruction execution begins. More... | |
| ProbePointArg< DynInstPtr > * | ppToCommit |
| To probe when instruction execution is complete. More... | |
| TimeBuffer< TimeStruct > * | timeBuffer |
| Pointer to main time buffer used for backwards communication. More... | |
| TimeBuffer< TimeStruct >::wire | toFetch |
| Wire to write information heading to previous stages. More... | |
| TimeBuffer< TimeStruct >::wire | fromCommit |
| Wire to get commit's output from backwards time buffer. More... | |
| TimeBuffer< TimeStruct >::wire | toRename |
| Wire to write information heading to previous stages. More... | |
| TimeBuffer< RenameStruct > * | renameQueue |
| Rename instruction queue interface. More... | |
| TimeBuffer< RenameStruct >::wire | fromRename |
| Wire to get rename's output from rename queue. More... | |
| TimeBuffer< IssueStruct > | issueToExecQueue |
| Issue stage queue. More... | |
| TimeBuffer< IssueStruct >::wire | fromIssue |
| Wire to read information from the issue stage time queue. More... | |
| TimeBuffer< IEWStruct > * | iewQueue |
| IEW stage time buffer. More... | |
| TimeBuffer< IEWStruct >::wire | toCommit |
| Wire to write infromation heading to commit. More... | |
| std::queue< DynInstPtr > | insts [Impl::MaxThreads] |
| Queue of all instructions coming from rename this cycle. More... | |
| std::queue< DynInstPtr > | skidBuffer [Impl::MaxThreads] |
| Skid buffer between rename and IEW. More... | |
| Scoreboard * | scoreboard |
| Scoreboard pointer. More... | |
| O3CPU * | cpu |
| CPU pointer. More... | |
| bool | wroteToTimeBuffer |
| Records if IEW has written to the time buffer this cycle, so that the CPU can deschedule itself if there is no activity. More... | |
| bool | fetchRedirect [Impl::MaxThreads] |
| Records if there is a fetch redirect on this cycle for each thread. More... | |
| bool | updatedQueues |
| Records if the queues have been changed (inserted or issued insts), so that IEW knows to broadcast the updated amount of free entries. More... | |
| Cycles | commitToIEWDelay |
| Commit to IEW delay. More... | |
| Cycles | renameToIEWDelay |
| Rename to IEW delay. More... | |
| Cycles | issueToExecuteDelay |
| Issue to execute delay. More... | |
| unsigned | dispatchWidth |
| Width of dispatch, in instructions. More... | |
| unsigned | issueWidth |
| Width of issue, in instructions. More... | |
| unsigned | wbNumInst |
| Index into queue of instructions being written back. More... | |
| unsigned | wbCycle |
| Cycle number within the queue of instructions being written back. More... | |
| unsigned | wbWidth |
| Writeback width. More... | |
| ThreadID | numThreads |
| Number of active threads. More... | |
| std::list< ThreadID > * | activeThreads |
| Pointer to list of active threads. More... | |
| unsigned | skidBufferMax |
| Maximum size of the skid buffer. More... | |
| Stats::Scalar | iewIdleCycles |
| Stat for total number of idle cycles. More... | |
| Stats::Scalar | iewSquashCycles |
| Stat for total number of squashing cycles. More... | |
| Stats::Scalar | iewBlockCycles |
| Stat for total number of blocking cycles. More... | |
| Stats::Scalar | iewUnblockCycles |
| Stat for total number of unblocking cycles. More... | |
| Stats::Scalar | iewDispatchedInsts |
| Stat for total number of instructions dispatched. More... | |
| Stats::Scalar | iewDispSquashedInsts |
| Stat for total number of squashed instructions dispatch skips. More... | |
| Stats::Scalar | iewDispLoadInsts |
| Stat for total number of dispatched load instructions. More... | |
| Stats::Scalar | iewDispStoreInsts |
| Stat for total number of dispatched store instructions. More... | |
| Stats::Scalar | iewDispNonSpecInsts |
| Stat for total number of dispatched non speculative instructions. More... | |
| Stats::Scalar | iewIQFullEvents |
| Stat for number of times the IQ becomes full. More... | |
| Stats::Scalar | iewLSQFullEvents |
| Stat for number of times the LSQ becomes full. More... | |
| Stats::Scalar | memOrderViolationEvents |
| Stat for total number of memory ordering violation events. More... | |
| Stats::Scalar | predictedTakenIncorrect |
| Stat for total number of incorrect predicted taken branches. More... | |
| Stats::Scalar | predictedNotTakenIncorrect |
| Stat for total number of incorrect predicted not taken branches. More... | |
| Stats::Formula | branchMispredicts |
| Stat for total number of mispredicted branches detected at execute. More... | |
| Stats::Scalar | iewExecutedInsts |
| Stat for total number of executed instructions. More... | |
| Stats::Vector | iewExecLoadInsts |
| Stat for total number of executed load instructions. More... | |
| Stats::Scalar | iewExecSquashedInsts |
| Stat for total number of executed store instructions. More... | |
| Stats::Vector | iewExecutedSwp |
| Number of executed software prefetches. More... | |
| Stats::Vector | iewExecutedNop |
| Number of executed nops. More... | |
| Stats::Vector | iewExecutedRefs |
| Number of executed meomory references. More... | |
| Stats::Vector | iewExecutedBranches |
| Number of executed branches. More... | |
| Stats::Formula | iewExecStoreInsts |
| Number of executed store instructions. More... | |
| Stats::Formula | iewExecRate |
| Number of instructions executed per cycle. More... | |
| Stats::Vector | iewInstsToCommit |
| Number of instructions sent to commit. More... | |
| Stats::Vector | writebackCount |
| Number of instructions that writeback. More... | |
| Stats::Vector | producerInst |
| Number of instructions that wake consumers. More... | |
| Stats::Vector | consumerInst |
| Number of instructions that wake up from producers. More... | |
| Stats::Formula | wbRate |
| Number of instructions per cycle written back. More... | |
| Stats::Formula | wbFanout |
| Average number of woken instructions per writeback. More... | |
DefaultIEW handles both single threaded and SMT IEW (issue/execute/writeback).
It handles the dispatching of instructions to the LSQ/IQ as part of the issue stage, and has the IQ try to issue instructions each cycle. The execute latency is actually tied into the issue latency to allow the IQ to be able to do back-to-back scheduling without having to speculatively schedule instructions. This happens by having the IQ have access to the functional units, and the IQ gets the execution latencies from the FUs when it issues instructions. Instructions reach the execute stage on the last cycle of their execution, which is when the IQ knows to wake up any dependent instructions, allowing back to back scheduling. The execute portion of IEW separates memory instructions from non-memory instructions, either telling the LSQ to execute the instruction, or executing the instruction directly. The writeback portion of IEW completes the instructions by waking up any dependents, and marking the register ready on the scoreboard.
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| enum DefaultIEW::StageStatus |
| enum DefaultIEW::Status |
| DefaultIEW< Impl >::DefaultIEW | ( | O3CPU * | _cpu, |
| DerivO3CPUParams * | params | ||
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Constructs a DefaultIEW with the given parameters.
Definition at line 68 of file iew_impl.hh.
References DefaultIEW< Impl >::_status, DefaultIEW< Impl >::Active, DefaultIEW< Impl >::dispatchStatus, DefaultIEW< Impl >::dispatchWidth, DefaultIEW< Impl >::exeStatus, fatal, DefaultIEW< Impl >::fetchRedirect, DefaultIEW< Impl >::fromIssue, TimeBuffer< T >::getWire(), DefaultIEW< Impl >::Idle, DefaultIEW< Impl >::instQueue, DefaultIEW< Impl >::issueToExecQueue, DefaultIEW< Impl >::issueToExecuteDelay, DefaultIEW< Impl >::issueWidth, DefaultIEW< Impl >::numThreads, DefaultIEW< Impl >::renameToIEWDelay, DefaultIEW< Impl >::Running, DefaultIEW< Impl >::skidBufferMax, DefaultIEW< Impl >::updateLSQNextCycle, DefaultIEW< Impl >::wbStatus, and DefaultIEW< Impl >::wbWidth.
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Tells CPU that the IEW stage is active and running.
Definition at line 885 of file iew_impl.hh.
References DPRINTF.
| void DefaultIEW< Impl >::activityThisCycle | ( | ) |
Reports to the CPU that there is activity this cycle.
Definition at line 877 of file iew_impl.hh.
References DPRINTF.
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Sets Dispatch to blocked, and signals back to other stages to block.
Definition at line 533 of file iew_impl.hh.
References DPRINTF.
| void DefaultIEW< Impl >::blockMemInst | ( | DynInstPtr & | inst | ) |
Moves memory instruction onto the list of cache blocked instructions.
Definition at line 590 of file iew_impl.hh.
| void DefaultIEW< Impl >::cacheUnblocked | ( | ) |
Notifies that the cache has become unblocked.
Definition at line 597 of file iew_impl.hh.
| void DefaultIEW< Impl >::checkMisprediction | ( | DynInstPtr & | inst | ) |
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Processes inputs and changes state accordingly.
Definition at line 771 of file iew_impl.hh.
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Checks if any of the stall conditions are currently true.
Definition at line 754 of file iew_impl.hh.
References DPRINTF.
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Tells CPU that the IEW stage is inactive and idle.
Definition at line 893 of file iew_impl.hh.
References DPRINTF.
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Determines proper actions to take given Dispatch's status.
Definition at line 901 of file iew_impl.hh.
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| void DefaultIEW< Impl >::drainSanityCheck | ( | ) | const |
Perform sanity checks after a drain.
Definition at line 410 of file iew_impl.hh.
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Removes instructions from rename from a thread's instruction list.
Definition at line 849 of file iew_impl.hh.
References DPRINTF.
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Returns if the LSQ has any stores to writeback.
Definition at line 227 of file iew.hh.
References LSQ< Impl >::hasStoresToWB(), and DefaultIEW< Impl >::ldstQueue.
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Returns if the LSQ has any stores to writeback.
Definition at line 230 of file iew.hh.
References LSQ< Impl >::hasStoresToWB(), and DefaultIEW< Impl >::ldstQueue.
| void DefaultIEW< Impl >::instToCommit | ( | DynInstPtr & | inst | ) |
Sends an instruction to commit through the time buffer.
Definition at line 604 of file iew_impl.hh.
References DPRINTF.
| bool DefaultIEW< Impl >::isDrained | ( | ) | const |
| std::string DefaultIEW< Impl >::name | ( | ) | const |
Returns the name of the DefaultIEW stage.
Definition at line 117 of file iew_impl.hh.
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Debug function to print instructions that are issued this cycle.
Definition at line 1153 of file iew_impl.hh.
| void DefaultIEW< Impl >::regProbePoints | ( | ) |
Registers probes.
Probe point with dynamic instruction as the argument used to probe when an instruction starts to execute.
Probe point with dynamic instruction as the argument used to probe when an instruction execution completes and it is marked ready to commit.
Definition at line 124 of file iew_impl.hh.
| void DefaultIEW< Impl >::regStats | ( | ) |
Registers statistics.
Definition at line 144 of file iew_impl.hh.
References name(), and Stats::total.
| void DefaultIEW< Impl >::replayMemInst | ( | DynInstPtr & | inst | ) |
Re-executes all rescheduled memory instructions.
Definition at line 583 of file iew_impl.hh.
| void DefaultIEW< Impl >::rescheduleMemInst | ( | DynInstPtr & | inst | ) |
Tells memory dependence unit that a memory instruction needs to be rescheduled.
It will re-execute once replayMemInst() is called.
Definition at line 576 of file iew_impl.hh.
| void DefaultIEW< Impl >::resetEntries | ( | ) |
Resets entries of the IQ and the LSQ.
Definition at line 746 of file iew_impl.hh.
| void DefaultIEW< Impl >::setActiveThreads | ( | std::list< ThreadID > * | at_ptr | ) |
Sets pointer to list of active threads.
Definition at line 364 of file iew_impl.hh.
| void DefaultIEW< Impl >::setIEWQueue | ( | TimeBuffer< IEWStruct > * | iq_ptr | ) |
Sets time buffer to pass on instructions to commit.
Definition at line 354 of file iew_impl.hh.
References TimeBuffer< T >::getWire().
| void DefaultIEW< Impl >::setRenameQueue | ( | TimeBuffer< RenameStruct > * | rq_ptr | ) |
Sets time buffer for getting instructions coming from rename.
Definition at line 344 of file iew_impl.hh.
References TimeBuffer< T >::getWire().
| void DefaultIEW< Impl >::setScoreboard | ( | Scoreboard * | sb_ptr | ) |
Sets pointer to the scoreboard.
Definition at line 374 of file iew_impl.hh.
| void DefaultIEW< Impl >::setTimeBuffer | ( | TimeBuffer< TimeStruct > * | tb_ptr | ) |
Sets main time buffer used for backwards communication.
Definition at line 326 of file iew_impl.hh.
References TimeBuffer< T >::getWire().
| int DefaultIEW< Impl >::skidCount | ( | ) |
Returns the max of the number of entries in all of the skid buffers.
Definition at line 669 of file iew_impl.hh.
| void DefaultIEW< Impl >::skidInsert | ( | ThreadID | tid | ) |
Inserts unused instructions of a thread into the skid buffer.
Definition at line 647 of file iew_impl.hh.
References DPRINTF, and X86ISA::size().
| bool DefaultIEW< Impl >::skidsEmpty | ( | ) |
Returns if all of the skid buffers are empty.
Definition at line 688 of file iew_impl.hh.
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Sorts instructions coming from rename into lists separated by thread.
Definition at line 835 of file iew_impl.hh.
References ArmISA::i.
| void DefaultIEW< Impl >::squash | ( | ThreadID | tid | ) |
Squashes instructions in IEW for a specific thread.
Definition at line 448 of file iew_impl.hh.
References DPRINTF.
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Sends commit proper information for a squash due to a branch mispredict.
Definition at line 481 of file iew_impl.hh.
References AlphaISA::advancePC(), DPRINTF, and pc.
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Sends commit proper information for a squash due to a memory order violation.
Definition at line 506 of file iew_impl.hh.
References DPRINTF.
| void DefaultIEW< Impl >::startupStage | ( | ) |
Initializes stage; sends back the number of free IQ and LSQ entries.
Definition at line 304 of file iew_impl.hh.
| void DefaultIEW< Impl >::takeOverFrom | ( | ) |
Takes over from another CPU's thread.
Definition at line 420 of file iew_impl.hh.
| void DefaultIEW< Impl >::tick | ( | ) |
Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle.
Definition at line 1452 of file iew_impl.hh.
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Unblocks Dispatch if the skid buffer is empty, and signals back to other stages to unblock.
Definition at line 552 of file iew_impl.hh.
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Updates execution stats based on the instruction.
Definition at line 1580 of file iew_impl.hh.
| void DefaultIEW< Impl >::updateStatus | ( | ) |
Updates overall IEW status based on all of the stages' statuses.
Definition at line 705 of file iew_impl.hh.
References DPRINTF.
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Returns the number of valid, non-squashed instructions coming from rename to dispatch.
Definition at line 633 of file iew_impl.hh.
References ArmISA::i.
| void DefaultIEW< Impl >::wakeCPU | ( | ) |
Tells the CPU to wakeup if it has descheduled itself due to no activity.
Used mainly by the LdWritebackEvent.
Definition at line 870 of file iew_impl.hh.
| void DefaultIEW< Impl >::wakeDependents | ( | DynInstPtr & | inst | ) |
Wakes all dependents of a completed instruction.
Definition at line 569 of file iew_impl.hh.
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Writebacks instructions.
In our model, the instruction's execute() function atomically reads registers, executes, and writes registers. Thus this writeback only wakes up dependent instructions, and informs the scoreboard of registers becoming ready.
Definition at line 1406 of file iew_impl.hh.
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Overall stage status.
Definition at line 118 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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Dispatch status.
Definition at line 120 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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Width of dispatch, in instructions.
Definition at line 391 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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Execute status.
Definition at line 122 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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Records if there is a fetch redirect on this cycle for each thread.
Definition at line 370 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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Wire to read information from the issue stage time queue.
Definition at line 322 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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| FUPool* DefaultIEW< Impl >::fuPool |
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| IQ DefaultIEW< Impl >::instQueue |
Instruction queue.
Definition at line 356 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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Issue stage queue.
Definition at line 319 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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Issue to execute delay.
What this actually represents is the amount of time it takes for an instruction to wake up, be scheduled, and sent to a FU for execution.
Definition at line 388 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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Width of issue, in instructions.
Definition at line 394 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
| LSQ DefaultIEW< Impl >::ldstQueue |
Load / store queue.
Definition at line 359 of file iew.hh.
Referenced by DefaultIEW< Impl >::hasStoresToWB().
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Number of active threads.
Definition at line 410 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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Rename to IEW delay.
Definition at line 381 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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Scoreboard pointer.
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Maximum size of the skid buffer.
Definition at line 416 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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| bool DefaultIEW< Impl >::updateLSQNextCycle |
Records if the LSQ needs to be updated on the next cycle, so that IEW knows if there will be activity on the next cycle.
Definition at line 366 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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Cycle number within the queue of instructions being written back.
Used in case there are too many instructions writing back at the current cycle and writesbacks need to be scheduled for the future. See comments in instToCommit().
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Writeback status.
Definition at line 124 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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Writeback width.
Definition at line 407 of file iew.hh.
Referenced by DefaultIEW< Impl >::DefaultIEW().
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