43 #ifndef __CPU_O3_IEW_HH__
44 #define __CPU_O3_IEW_HH__
54 #include "debug/IEW.hh"
57 struct DerivO3CPUParams;
84 typedef typename Impl::CPUPol
CPUPol;
86 typedef typename Impl::O3CPU
O3CPU;
88 typedef typename CPUPol::IQ
IQ;
90 typedef typename CPUPol::LSQ
LSQ;
139 std::string
name()
const;
334 std::queue<DynInstPtr>
insts[Impl::MaxThreads];
484 #endif // __CPU_O3_IEW_HH__
Cycles renameToIEWDelay
Rename to IEW delay.
Stats::Vector iewExecutedBranches
Number of executed branches.
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets main time buffer used for backwards communication.
unsigned issueWidth
Width of issue, in instructions.
Scoreboard * scoreboard
Scoreboard pointer.
bool fetchRedirect[Impl::MaxThreads]
Records if there is a fetch redirect on this cycle for each thread.
StageStatus exeStatus
Execute status.
Stats::Scalar iewDispStoreInsts
Stat for total number of dispatched store instructions.
Stats::Scalar iewExecutedInsts
Stat for total number of executed instructions.
Cycles is a wrapper class for representing cycle counts, i.e.
bool hasStoresToWB(ThreadID tid)
Returns if the LSQ has any stores to writeback.
void setIEWQueue(TimeBuffer< IEWStruct > *iq_ptr)
Sets time buffer to pass on instructions to commit.
Status
Overall IEW stage status.
Stats::Scalar iewIdleCycles
Stat for total number of idle cycles.
bool updatedQueues
Records if the queues have been changed (inserted or issued insts), so that IEW knows to broadcast th...
void setRenameQueue(TimeBuffer< RenameStruct > *rq_ptr)
Sets time buffer for getting instructions coming from rename.
Stats::Scalar iewUnblockCycles
Stat for total number of unblocking cycles.
Stats::Scalar iewSquashCycles
Stat for total number of squashing cycles.
void startupStage()
Initializes stage; sends back the number of free IQ and LSQ entries.
Stats::Formula iewExecRate
Number of instructions executed per cycle.
void unblock(ThreadID tid)
Unblocks Dispatch if the skid buffer is empty, and signals back to other stages to unblock...
Stats::Scalar iewLSQFullEvents
Stat for number of times the LSQ becomes full.
void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a memory order violation.
DefaultIEW handles both single threaded and SMT IEW (issue/execute/writeback).
Stats::Scalar iewIQFullEvents
Stat for number of times the IQ becomes full.
void checkMisprediction(DynInstPtr &inst)
Check misprediction.
ThreadID numThreads
Number of active threads.
void printAvailableInsts()
Debug function to print instructions that are issued this cycle.
Cycles issueToExecuteDelay
Issue to execute delay.
TimeBuffer< TimeStruct > * timeBuffer
Pointer to main time buffer used for backwards communication.
Stats::Vector iewExecutedRefs
Number of executed meomory references.
DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
Constructs a DefaultIEW with the given parameters.
bool hasStoresToWB()
Returns whether or not there are any stores to write back to memory.
void blockMemInst(DynInstPtr &inst)
Moves memory instruction onto the list of cache blocked instructions.
void squash(ThreadID tid)
Squashes instructions in IEW for a specific thread.
std::queue< DynInstPtr > insts[Impl::MaxThreads]
Queue of all instructions coming from rename this cycle.
A vector of scalar stats.
bool checkStall(ThreadID tid)
Checks if any of the stall conditions are currently true.
std::list< ThreadID > * activeThreads
Pointer to list of active threads.
unsigned wbNumInst
Index into queue of instructions being written back.
unsigned dispatchWidth
Width of dispatch, in instructions.
TimeBuffer< TimeStruct >::wire toFetch
Wire to write information heading to previous stages.
Declaration of Statistics objects.
This is a simple scalar statistic, like a counter.
StageStatus wbStatus
Writeback status.
unsigned validInstsFromRename()
Returns the number of valid, non-squashed instructions coming from rename to dispatch.
TimeBuffer< IEWStruct > * iewQueue
IEW stage time buffer.
Stats::Vector iewExecutedSwp
Number of executed software prefetches.
ProbePointArg< DynInstPtr > * ppToCommit
To probe when instruction execution is complete.
Stats::Vector writebackCount
Number of instructions that writeback.
Stats::Scalar iewDispNonSpecInsts
Stat for total number of dispatched non speculative instructions.
Implements a simple scoreboard to track which registers are ready.
void cacheUnblocked()
Notifies that the cache has become unblocked.
bool hasStoresToWB()
Returns if the LSQ has any stores to writeback.
IQ instQueue
Instruction queue.
TimeBuffer< IssueStruct >::wire fromIssue
Wire to read information from the issue stage time queue.
CPUPol::IssueStruct IssueStruct
void activateStage()
Tells CPU that the IEW stage is active and running.
void instToCommit(DynInstPtr &inst)
Sends an instruction to commit through the time buffer.
Pool of FU's, specific to the new CPU model.
void dispatchInsts(ThreadID tid)
Dispatches instructions to IQ and LSQ.
std::queue< DynInstPtr > skidBuffer[Impl::MaxThreads]
Skid buffer between rename and IEW.
Status _status
Overall stage status.
TimeBuffer< IssueStruct > issueToExecQueue
Issue stage queue.
ProbePointArg< DynInstPtr > * ppDispatch
Stats::Scalar iewExecSquashedInsts
Stat for total number of executed store instructions.
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's output from backwards time buffer.
Stats::Scalar iewDispLoadInsts
Stat for total number of dispatched load instructions.
void takeOverFrom()
Takes over from another CPU's thread.
Stats::Formula wbRate
Number of instructions per cycle written back.
Stats::Scalar iewDispatchedInsts
Stat for total number of instructions dispatched.
void tick()
Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle...
bool isDrained() const
Has the stage drained?
void emptyRenameInsts(ThreadID tid)
Removes instructions from rename from a thread's instruction list.
void checkSignalsAndUpdate(ThreadID tid)
Processes inputs and changes state accordingly.
unsigned wbWidth
Writeback width.
CPUPol::TimeStruct TimeStruct
void wakeCPU()
Tells the CPU to wakeup if it has descheduled itself due to no activity.
unsigned wbCycle
Cycle number within the queue of instructions being written back.
Stats::Vector iewExecutedNop
Number of executed nops.
Cycles commitToIEWDelay
Commit to IEW delay.
Stats::Scalar iewDispSquashedInsts
Stat for total number of squashed instructions dispatch skips.
bool updateLSQNextCycle
Records if the LSQ needs to be updated on the next cycle, so that IEW knows if there will be activity...
Stats::Vector producerInst
Number of instructions that wake consumers.
void squashDueToBranch(DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a branch mispredict.
Stats::Scalar predictedTakenIncorrect
Stat for total number of incorrect predicted taken branches.
void activityThisCycle()
Reports to the CPU that there is activity this cycle.
int16_t ThreadID
Thread index/ID type.
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
Stats::Scalar memOrderViolationEvents
Stat for total number of memory ordering violation events.
void regStats()
Registers statistics.
int skidCount()
Returns the max of the number of entries in all of the skid buffers.
void setScoreboard(Scoreboard *sb_ptr)
Sets pointer to the scoreboard.
bool wroteToTimeBuffer
Records if IEW has written to the time buffer this cycle, so that the CPU can deschedule itself if th...
StageStatus
Status for Issue, Execute, and Writeback stages.
Stats::Formula iewExecStoreInsts
Number of executed store instructions.
void executeInsts()
Executes instructions.
TimeBuffer< RenameStruct > * renameQueue
Rename instruction queue interface.
void drainSanityCheck() const
Perform sanity checks after a drain.
void writebackInsts()
Writebacks instructions.
void sortInsts()
Sorts instructions coming from rename into lists separated by thread.
Stats::Vector iewInstsToCommit
Number of instructions sent to commit.
void dispatch(ThreadID tid)
Determines proper actions to take given Dispatch's status.
void skidInsert(ThreadID tid)
Inserts unused instructions of a thread into the skid buffer.
TimeBuffer< RenameStruct >::wire fromRename
Wire to get rename's output from rename queue.
LSQ ldstQueue
Load / store queue.
TimeBuffer< IEWStruct >::wire toCommit
Wire to write infromation heading to commit.
CPUPol::RenameStruct RenameStruct
Stats::Formula branchMispredicts
Stat for total number of mispredicted branches detected at execute.
void rescheduleMemInst(DynInstPtr &inst)
Tells memory dependence unit that a memory instruction needs to be rescheduled.
void deactivateStage()
Tells CPU that the IEW stage is inactive and idle.
bool skidsEmpty()
Returns if all of the skid buffers are empty.
unsigned skidBufferMax
Maximum size of the skid buffer.
Impl::DynInstPtr DynInstPtr
ProbePointArg< DynInstPtr > * ppExecute
To probe when instruction execution begins.
void wakeDependents(DynInstPtr &inst)
Wakes all dependents of a completed instruction.
void resetEntries()
Resets entries of the IQ and the LSQ.
TimeBuffer< TimeStruct >::wire toRename
Wire to write information heading to previous stages.
StageStatus dispatchStatus[Impl::MaxThreads]
Dispatch status.
void updateExeInstStats(DynInstPtr &inst)
Updates execution stats based on the instruction.
ProbePointArg< DynInstPtr > * ppMispredict
Probe points.
void block(ThreadID tid)
Sets Dispatch to blocked, and signals back to other stages to block.
Stats::Scalar predictedNotTakenIncorrect
Stat for total number of incorrect predicted not taken branches.
Stats::Vector iewExecLoadInsts
Stat for total number of executed load instructions.
Stats::Vector consumerInst
Number of instructions that wake up from producers.
void regProbePoints()
Registers probes.
CPUPol::IEWStruct IEWStruct
std::string name() const
Returns the name of the DefaultIEW stage.
CPUPol::RenameMap RenameMap
Stats::Scalar iewBlockCycles
Stat for total number of blocking cycles.
void updateStatus()
Updates overall IEW status based on all of the stages' statuses.
void replayMemInst(DynInstPtr &inst)
Re-executes all rescheduled memory instructions.
FUPool * fuPool
Pointer to the functional unit pool.
Stats::Formula wbFanout
Average number of woken instructions per writeback.