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iew.hh
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40  * Authors: Kevin Lim
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42 
43 #ifndef __CPU_O3_IEW_HH__
44 #define __CPU_O3_IEW_HH__
45 
46 #include <queue>
47 #include <set>
48 
49 #include "base/statistics.hh"
50 #include "cpu/o3/comm.hh"
51 #include "cpu/o3/lsq.hh"
52 #include "cpu/o3/scoreboard.hh"
53 #include "cpu/timebuf.hh"
54 #include "debug/IEW.hh"
55 #include "sim/probe/probe.hh"
56 
57 struct DerivO3CPUParams;
58 class FUPool;
59 
79 template<class Impl>
81 {
82  private:
83  //Typedefs from Impl
84  typedef typename Impl::CPUPol CPUPol;
85  typedef typename Impl::DynInstPtr DynInstPtr;
86  typedef typename Impl::O3CPU O3CPU;
87 
88  typedef typename CPUPol::IQ IQ;
89  typedef typename CPUPol::RenameMap RenameMap;
90  typedef typename CPUPol::LSQ LSQ;
91 
92  typedef typename CPUPol::TimeStruct TimeStruct;
93  typedef typename CPUPol::IEWStruct IEWStruct;
94  typedef typename CPUPol::RenameStruct RenameStruct;
95  typedef typename CPUPol::IssueStruct IssueStruct;
96 
97  public:
101  enum Status {
104  };
105 
107  enum StageStatus {
114  };
115 
116  private:
120  StageStatus dispatchStatus[Impl::MaxThreads];
125 
133 
134  public:
136  DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
137 
139  std::string name() const;
140 
142  void regStats();
143 
145  void regProbePoints();
146 
148  void startupStage();
149 
152 
155 
157  void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
158 
161 
163  void setScoreboard(Scoreboard *sb_ptr);
164 
166  void drainSanityCheck() const;
167 
169  bool isDrained() const;
170 
172  void takeOverFrom();
173 
175  void squash(ThreadID tid);
176 
178  void wakeDependents(DynInstPtr &inst);
179 
183  void rescheduleMemInst(DynInstPtr &inst);
184 
186  void replayMemInst(DynInstPtr &inst);
187 
189  void blockMemInst(DynInstPtr &inst);
190 
192  void cacheUnblocked();
193 
195  void instToCommit(DynInstPtr &inst);
196 
198  void skidInsert(ThreadID tid);
199 
201  int skidCount();
202 
204  bool skidsEmpty();
205 
207  void updateStatus();
208 
210  void resetEntries();
211 
215  void wakeCPU();
216 
218  void activityThisCycle();
219 
221  inline void activateStage();
222 
224  inline void deactivateStage();
225 
227  bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
228 
230  bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
231 
233  void checkMisprediction(DynInstPtr &inst);
234 
235  private:
239  void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
240 
244  void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid);
245 
247  void block(ThreadID tid);
248 
252  void unblock(ThreadID tid);
253 
255  void dispatch(ThreadID tid);
256 
258  void dispatchInsts(ThreadID tid);
259 
264  void executeInsts();
265 
271  void writebackInsts();
272 
276  unsigned validInstsFromRename();
277 
279  bool checkStall(ThreadID tid);
280 
283 
285  void emptyRenameInsts(ThreadID tid);
286 
288  void sortInsts();
289 
290  public:
294  void tick();
295 
296  private:
298  void updateExeInstStats(DynInstPtr &inst);
299 
302 
305 
308 
311 
314 
317 
320 
323 
329 
332 
334  std::queue<DynInstPtr> insts[Impl::MaxThreads];
335 
337  std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
338 
341 
342  private:
345 
350 
352  void printAvailableInsts();
353 
354  public:
357 
360 
367 
368  private:
370  bool fetchRedirect[Impl::MaxThreads];
371 
376 
379 
382 
389 
391  unsigned dispatchWidth;
392 
394  unsigned issueWidth;
395 
397  unsigned wbNumInst;
398 
404  unsigned wbCycle;
405 
407  unsigned wbWidth;
408 
411 
414 
416  unsigned skidBufferMax;
417 
448 
454 // Stats::Scalar iewExecStoreInsts;
469 
482 };
483 
484 #endif // __CPU_O3_IEW_HH__
Cycles renameToIEWDelay
Rename to IEW delay.
Definition: iew.hh:381
Stats::Vector iewExecutedBranches
Number of executed branches.
Definition: iew.hh:464
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets main time buffer used for backwards communication.
Definition: iew_impl.hh:326
unsigned issueWidth
Width of issue, in instructions.
Definition: iew.hh:394
Scoreboard * scoreboard
Scoreboard pointer.
Definition: iew.hh:340
bool fetchRedirect[Impl::MaxThreads]
Records if there is a fetch redirect on this cycle for each thread.
Definition: iew.hh:370
StageStatus exeStatus
Execute status.
Definition: iew.hh:122
Stats::Scalar iewDispStoreInsts
Stat for total number of dispatched store instructions.
Definition: iew.hh:433
Stats::Scalar iewExecutedInsts
Stat for total number of executed instructions.
Definition: iew.hh:450
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
bool hasStoresToWB(ThreadID tid)
Returns if the LSQ has any stores to writeback.
Definition: iew.hh:230
void setIEWQueue(TimeBuffer< IEWStruct > *iq_ptr)
Sets time buffer to pass on instructions to commit.
Definition: iew_impl.hh:354
CPUPol::LSQ LSQ
Definition: iew.hh:90
Status
Overall IEW stage status.
Definition: iew.hh:101
Stats::Scalar iewIdleCycles
Stat for total number of idle cycles.
Definition: iew.hh:419
bool updatedQueues
Records if the queues have been changed (inserted or issued insts), so that IEW knows to broadcast th...
Definition: iew.hh:375
void setRenameQueue(TimeBuffer< RenameStruct > *rq_ptr)
Sets time buffer for getting instructions coming from rename.
Definition: iew_impl.hh:344
Stats::Scalar iewUnblockCycles
Stat for total number of unblocking cycles.
Definition: iew.hh:425
Stats::Scalar iewSquashCycles
Stat for total number of squashing cycles.
Definition: iew.hh:421
void startupStage()
Initializes stage; sends back the number of free IQ and LSQ entries.
Definition: iew_impl.hh:304
Stats::Formula iewExecRate
Number of instructions executed per cycle.
Definition: iew.hh:468
void unblock(ThreadID tid)
Unblocks Dispatch if the skid buffer is empty, and signals back to other stages to unblock...
Definition: iew_impl.hh:552
Stats::Scalar iewLSQFullEvents
Stat for number of times the LSQ becomes full.
Definition: iew.hh:439
void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a memory order violation.
Definition: iew_impl.hh:506
DefaultIEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:80
Stats::Scalar iewIQFullEvents
Stat for number of times the IQ becomes full.
Definition: iew.hh:437
void checkMisprediction(DynInstPtr &inst)
Check misprediction.
Definition: iew_impl.hh:1612
ThreadID numThreads
Number of active threads.
Definition: iew.hh:410
void printAvailableInsts()
Debug function to print instructions that are issued this cycle.
Definition: iew_impl.hh:1153
O3CPU * cpu
CPU pointer.
Definition: iew.hh:344
Cycles issueToExecuteDelay
Issue to execute delay.
Definition: iew.hh:388
TimeBuffer< TimeStruct > * timeBuffer
Pointer to main time buffer used for backwards communication.
Definition: iew.hh:301
Stats::Vector iewExecutedRefs
Number of executed meomory references.
Definition: iew.hh:462
DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
Constructs a DefaultIEW with the given parameters.
Definition: iew_impl.hh:68
bool hasStoresToWB()
Returns whether or not there are any stores to write back to memory.
Definition: lsq_impl.hh:656
void blockMemInst(DynInstPtr &inst)
Moves memory instruction onto the list of cache blocked instructions.
Definition: iew_impl.hh:590
void squash(ThreadID tid)
Squashes instructions in IEW for a specific thread.
Definition: iew_impl.hh:448
std::queue< DynInstPtr > insts[Impl::MaxThreads]
Queue of all instructions coming from rename this cycle.
Definition: iew.hh:334
A vector of scalar stats.
Definition: statistics.hh:2499
bool checkStall(ThreadID tid)
Checks if any of the stall conditions are currently true.
Definition: iew_impl.hh:754
std::list< ThreadID > * activeThreads
Pointer to list of active threads.
Definition: iew.hh:413
unsigned wbNumInst
Index into queue of instructions being written back.
Definition: iew.hh:397
unsigned dispatchWidth
Width of dispatch, in instructions.
Definition: iew.hh:391
TimeBuffer< TimeStruct >::wire toFetch
Wire to write information heading to previous stages.
Definition: iew.hh:304
Definition: lsq.hh:58
Declaration of Statistics objects.
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:2475
StageStatus wbStatus
Writeback status.
Definition: iew.hh:124
unsigned validInstsFromRename()
Returns the number of valid, non-squashed instructions coming from rename to dispatch.
Definition: iew_impl.hh:633
TimeBuffer< IEWStruct > * iewQueue
IEW stage time buffer.
Definition: iew.hh:328
Stats::Vector iewExecutedSwp
Number of executed software prefetches.
Definition: iew.hh:458
ProbePointArg< DynInstPtr > * ppToCommit
To probe when instruction execution is complete.
Definition: iew.hh:132
Stats::Vector writebackCount
Number of instructions that writeback.
Definition: iew.hh:473
Stats::Scalar iewDispNonSpecInsts
Stat for total number of dispatched non speculative instructions.
Definition: iew.hh:435
Impl::CPUPol CPUPol
Definition: iew.hh:84
Implements a simple scoreboard to track which registers are ready.
Definition: scoreboard.hh:56
void cacheUnblocked()
Notifies that the cache has become unblocked.
Definition: iew_impl.hh:597
bool hasStoresToWB()
Returns if the LSQ has any stores to writeback.
Definition: iew.hh:227
IQ instQueue
Instruction queue.
Definition: iew.hh:356
TimeBuffer< IssueStruct >::wire fromIssue
Wire to read information from the issue stage time queue.
Definition: iew.hh:322
CPUPol::IssueStruct IssueStruct
Definition: iew.hh:95
void activateStage()
Tells CPU that the IEW stage is active and running.
Definition: iew_impl.hh:885
void instToCommit(DynInstPtr &inst)
Sends an instruction to commit through the time buffer.
Definition: iew_impl.hh:604
Pool of FU's, specific to the new CPU model.
Definition: fu_pool.hh:71
void dispatchInsts(ThreadID tid)
Dispatches instructions to IQ and LSQ.
Definition: iew_impl.hh:949
std::queue< DynInstPtr > skidBuffer[Impl::MaxThreads]
Skid buffer between rename and IEW.
Definition: iew.hh:337
Status _status
Overall stage status.
Definition: iew.hh:118
TimeBuffer< IssueStruct > issueToExecQueue
Issue stage queue.
Definition: iew.hh:319
ProbePointArg< DynInstPtr > * ppDispatch
Definition: iew.hh:128
Stats::Scalar iewExecSquashedInsts
Stat for total number of executed store instructions.
Definition: iew.hh:456
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's output from backwards time buffer.
Definition: iew.hh:307
Stats::Scalar iewDispLoadInsts
Stat for total number of dispatched load instructions.
Definition: iew.hh:431
void takeOverFrom()
Takes over from another CPU's thread.
Definition: iew_impl.hh:420
Stats::Formula wbRate
Number of instructions per cycle written back.
Definition: iew.hh:479
Stats::Scalar iewDispatchedInsts
Stat for total number of instructions dispatched.
Definition: iew.hh:427
void tick()
Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle...
Definition: iew_impl.hh:1452
bool isDrained() const
Has the stage drained?
Definition: iew_impl.hh:381
void emptyRenameInsts(ThreadID tid)
Removes instructions from rename from a thread's instruction list.
Definition: iew_impl.hh:849
void checkSignalsAndUpdate(ThreadID tid)
Processes inputs and changes state accordingly.
Definition: iew_impl.hh:771
unsigned wbWidth
Writeback width.
Definition: iew.hh:407
CPUPol::TimeStruct TimeStruct
Definition: iew.hh:92
void wakeCPU()
Tells the CPU to wakeup if it has descheduled itself due to no activity.
Definition: iew_impl.hh:870
unsigned wbCycle
Cycle number within the queue of instructions being written back.
Definition: iew.hh:404
Stats::Vector iewExecutedNop
Number of executed nops.
Definition: iew.hh:460
CPUPol::IQ IQ
Definition: iew.hh:88
Cycles commitToIEWDelay
Commit to IEW delay.
Definition: iew.hh:378
Stats::Scalar iewDispSquashedInsts
Stat for total number of squashed instructions dispatch skips.
Definition: iew.hh:429
bool updateLSQNextCycle
Records if the LSQ needs to be updated on the next cycle, so that IEW knows if there will be activity...
Definition: iew.hh:366
Stats::Vector producerInst
Number of instructions that wake consumers.
Definition: iew.hh:475
void squashDueToBranch(DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a branch mispredict.
Definition: iew_impl.hh:481
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2895
Stats::Scalar predictedTakenIncorrect
Stat for total number of incorrect predicted taken branches.
Definition: iew.hh:443
void activityThisCycle()
Reports to the CPU that there is activity this cycle.
Definition: iew_impl.hh:877
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:171
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
Definition: iew_impl.hh:364
Stats::Scalar memOrderViolationEvents
Stat for total number of memory ordering violation events.
Definition: iew.hh:441
void regStats()
Registers statistics.
Definition: iew_impl.hh:144
int skidCount()
Returns the max of the number of entries in all of the skid buffers.
Definition: iew_impl.hh:669
void setScoreboard(Scoreboard *sb_ptr)
Sets pointer to the scoreboard.
Definition: iew_impl.hh:374
bool wroteToTimeBuffer
Records if IEW has written to the time buffer this cycle, so that the CPU can deschedule itself if th...
Definition: iew.hh:349
StageStatus
Status for Issue, Execute, and Writeback stages.
Definition: iew.hh:107
Stats::Formula iewExecStoreInsts
Number of executed store instructions.
Definition: iew.hh:466
void executeInsts()
Executes instructions.
Definition: iew_impl.hh:1176
TimeBuffer< RenameStruct > * renameQueue
Rename instruction queue interface.
Definition: iew.hh:313
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: iew_impl.hh:410
void writebackInsts()
Writebacks instructions.
Definition: iew_impl.hh:1406
void sortInsts()
Sorts instructions coming from rename into lists separated by thread.
Definition: iew_impl.hh:835
Stats::Vector iewInstsToCommit
Number of instructions sent to commit.
Definition: iew.hh:471
void dispatch(ThreadID tid)
Determines proper actions to take given Dispatch's status.
Definition: iew_impl.hh:901
void skidInsert(ThreadID tid)
Inserts unused instructions of a thread into the skid buffer.
Definition: iew_impl.hh:647
TimeBuffer< RenameStruct >::wire fromRename
Wire to get rename's output from rename queue.
Definition: iew.hh:316
LSQ ldstQueue
Load / store queue.
Definition: iew.hh:359
TimeBuffer< IEWStruct >::wire toCommit
Wire to write infromation heading to commit.
Definition: iew.hh:331
CPUPol::RenameStruct RenameStruct
Definition: iew.hh:94
Stats::Formula branchMispredicts
Stat for total number of mispredicted branches detected at execute.
Definition: iew.hh:447
void rescheduleMemInst(DynInstPtr &inst)
Tells memory dependence unit that a memory instruction needs to be rescheduled.
Definition: iew_impl.hh:576
void deactivateStage()
Tells CPU that the IEW stage is inactive and idle.
Definition: iew_impl.hh:893
bool skidsEmpty()
Returns if all of the skid buffers are empty.
Definition: iew_impl.hh:688
unsigned skidBufferMax
Maximum size of the skid buffer.
Definition: iew.hh:416
Impl::DynInstPtr DynInstPtr
Definition: iew.hh:85
ProbePointArg< DynInstPtr > * ppExecute
To probe when instruction execution begins.
Definition: iew.hh:130
void wakeDependents(DynInstPtr &inst)
Wakes all dependents of a completed instruction.
Definition: iew_impl.hh:569
void resetEntries()
Resets entries of the IQ and the LSQ.
Definition: iew_impl.hh:746
TimeBuffer< TimeStruct >::wire toRename
Wire to write information heading to previous stages.
Definition: iew.hh:310
StageStatus dispatchStatus[Impl::MaxThreads]
Dispatch status.
Definition: iew.hh:120
void updateExeInstStats(DynInstPtr &inst)
Updates execution stats based on the instruction.
Definition: iew_impl.hh:1580
ProbePointArg< DynInstPtr > * ppMispredict
Probe points.
Definition: iew.hh:127
void block(ThreadID tid)
Sets Dispatch to blocked, and signals back to other stages to block.
Definition: iew_impl.hh:533
Stats::Scalar predictedNotTakenIncorrect
Stat for total number of incorrect predicted not taken branches.
Definition: iew.hh:445
Impl::O3CPU O3CPU
Definition: iew.hh:86
Stats::Vector iewExecLoadInsts
Stat for total number of executed load instructions.
Definition: iew.hh:452
Stats::Vector consumerInst
Number of instructions that wake up from producers.
Definition: iew.hh:477
void regProbePoints()
Registers probes.
Definition: iew_impl.hh:124
CPUPol::IEWStruct IEWStruct
Definition: iew.hh:93
std::string name() const
Returns the name of the DefaultIEW stage.
Definition: iew_impl.hh:117
CPUPol::RenameMap RenameMap
Definition: iew.hh:89
Stats::Scalar iewBlockCycles
Stat for total number of blocking cycles.
Definition: iew.hh:423
void updateStatus()
Updates overall IEW status based on all of the stages' statuses.
Definition: iew_impl.hh:705
void replayMemInst(DynInstPtr &inst)
Re-executes all rescheduled memory instructions.
Definition: iew_impl.hh:583
FUPool * fuPool
Pointer to the functional unit pool.
Definition: iew.hh:362
Stats::Formula wbFanout
Average number of woken instructions per writeback.
Definition: iew.hh:481

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