gem5
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#include <isa.hh>
Classes | |
class | CP0Event |
Public Types | |
enum | CP0EventType { UpdateCP0 } |
typedef ISA | CP0 |
typedef MipsISAParams | Params |
Public Types inherited from SimObject | |
typedef SimObjectParams | Params |
Public Member Functions | |
void | clear () |
void | configCP () |
unsigned | getVPENum (ThreadID tid) const |
void | updateCP0ReadView (int misc_reg, ThreadID tid) |
MiscReg | readMiscRegNoEffect (int misc_reg, ThreadID tid=0) const |
MiscReg | readMiscReg (int misc_reg, ThreadContext *tc, ThreadID tid=0) |
MiscReg | filterCP0Write (int misc_reg, int reg_sel, const MiscReg &val) |
This method doesn't need to adjust the Control Register Offset since it has already been done in the calling method (setRegWithEffect) More... | |
void | setRegMask (int misc_reg, const MiscReg &val, ThreadID tid=0) |
void | setMiscRegNoEffect (int misc_reg, const MiscReg &val, ThreadID tid=0) |
void | setMiscReg (int misc_reg, const MiscReg &val, ThreadContext *tc, ThreadID tid=0) |
void | scheduleCP0Update (BaseCPU *cpu, Cycles delay=Cycles(0)) |
void | updateCPU (BaseCPU *cpu) |
void | startup (ThreadContext *tc) |
const Params * | params () const |
ISA (Params *p) | |
int | flattenIntIndex (int reg) const |
int | flattenFloatIndex (int reg) const |
int | flattenCCIndex (int reg) const |
int | flattenMiscIndex (int reg) const |
Public Member Functions inherited from SimObject | |
const Params * | params () const |
SimObject (const Params *_params) | |
virtual | ~SimObject () |
virtual const std::string | name () const |
virtual void | init () |
init() is called after all C++ SimObjects have been created and all ports are connected. More... | |
virtual void | loadState (CheckpointIn &cp) |
loadState() is called on each SimObject when restoring from a checkpoint. More... | |
virtual void | initState () |
initState() is called on each SimObject when not restoring from a checkpoint. More... | |
virtual void | regStats () |
Register statistics for this object. More... | |
virtual void | resetStats () |
Reset statistics associated with this object. More... | |
virtual void | regProbePoints () |
Register probe points for this object. More... | |
virtual void | regProbeListeners () |
Register probe listeners for this object. More... | |
ProbeManager * | getProbeManager () |
Get the probe manager for this object. More... | |
virtual void | startup () |
startup() is the final initialization call before simulation. More... | |
DrainState | drain () override |
Provide a default implementation of the drain interface for objects that don't need draining. More... | |
virtual void | memWriteback () |
Write back dirty buffers to memory using functional writes. More... | |
virtual void | memInvalidate () |
Invalidate the contents of memory buffers. More... | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. More... | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. More... | |
Public Member Functions inherited from EventManager | |
EventManager (EventManager &em) | |
EventManager (EventManager *em) | |
EventManager (EventQueue *eq) | |
EventQueue * | eventQueue () const |
void | schedule (Event &event, Tick when) |
void | deschedule (Event &event) |
void | reschedule (Event &event, Tick when, bool always=false) |
void | schedule (Event *event, Tick when) |
void | deschedule (Event *event) |
void | reschedule (Event *event, Tick when, bool always=false) |
void | wakeupEventQueue (Tick when=(Tick)-1) |
void | setCurTick (Tick newVal) |
Public Member Functions inherited from Serializable | |
Serializable () | |
virtual | ~Serializable () |
void | serializeSection (CheckpointOut &cp, const char *name) const |
Serialize an object into a new section. More... | |
void | serializeSection (CheckpointOut &cp, const std::string &name) const |
void | unserializeSection (CheckpointIn &cp, const char *name) |
Unserialize an a child object. More... | |
void | unserializeSection (CheckpointIn &cp, const std::string &name) |
Public Member Functions inherited from Drainable | |
DrainState | drainState () const |
Return the current drain state of an object. More... | |
virtual void | notifyFork () |
Notify a child process of a fork. More... | |
Public Attributes | |
bool | cp0Updated |
std::queue< CP0Event * > | cp0EventRemoveList |
Static Public Attributes | |
static std::string | miscRegNames [NumMiscRegs] |
Static Public Attributes inherited from Serializable | |
static int | ckptCount = 0 |
static int | ckptMaxCount = 0 |
static int | ckptPrevCount = -1 |
Protected Types | |
enum | BankType { perProcessor, perThreadContext, perVirtProcessor } |
Protected Attributes | |
uint8_t | numThreads |
uint8_t | numVpes |
std::vector< std::vector < MiscReg > > | miscRegFile |
std::vector< std::vector < MiscReg > > | miscRegFile_WriteMask |
std::vector< BankType > | bankType |
Protected Attributes inherited from SimObject | |
const SimObjectParams * | _params |
Cached copy of the object parameters. More... | |
Protected Attributes inherited from EventManager | |
EventQueue * | eventq |
A pointer to this object's event queue. More... | |
Additional Inherited Members | |
Static Public Member Functions inherited from SimObject | |
static void | serializeAll (CheckpointOut &cp) |
Serialize all SimObjects in the system. More... | |
static SimObject * | find (const char *name) |
Find the SimObject with the given name and return a pointer to it. More... | |
Static Public Member Functions inherited from Serializable | |
static const std::string & | currentSection () |
Get the fully-qualified name of the active section. More... | |
static void | serializeAll (const std::string &cpt_dir) |
static void | unserializeGlobals (CheckpointIn &cp) |
Protected Member Functions inherited from Drainable | |
Drainable () | |
virtual | ~Drainable () |
virtual void | drainResume () |
Resume execution after a successful drain. More... | |
void | signalDrainDone () const |
Signal that an object is drained. More... | |
typedef ISA MipsISA::ISA::CP0 |
typedef MipsISAParams MipsISA::ISA::Params |
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protected |
MipsISA::ISA::ISA | ( | Params * | p | ) |
Definition at line 92 of file isa.cc.
References bankType, clear(), MipsISA::i, MipsISA::MISCREG_DEBUG, MipsISA::MISCREG_EBASE, MipsISA::MISCREG_LLADDR, MipsISA::MISCREG_SRS_CONF0, MipsISA::MISCREG_SRS_CONF1, MipsISA::MISCREG_SRS_CONF2, MipsISA::MISCREG_SRS_CONF3, MipsISA::MISCREG_SRS_CONF4, MipsISA::MISCREG_STATUS, MipsISA::MISCREG_TC_BIND, MipsISA::MISCREG_TC_CONTEXT, MipsISA::MISCREG_TC_HALT, MipsISA::MISCREG_TC_RESTART, MipsISA::MISCREG_TC_SCHEDULE, MipsISA::MISCREG_TC_SCHEFBACK, MipsISA::MISCREG_TC_STATUS, MipsISA::MISCREG_VPE_CONF0, MipsISA::MISCREG_VPE_CONF1, MipsISA::MISCREG_VPE_CONTROL, MipsISA::MISCREG_VPE_OPT, MipsISA::MISCREG_VPE_SCHEDULE, MipsISA::MISCREG_VPE_SCHEFBACK, MipsISA::MISCREG_YQMASK, miscRegFile, miscRegFile_WriteMask, MipsISA::NumMiscRegs, numThreads, numVpes, perProcessor, perThreadContext, and perVirtProcessor.
void MipsISA::ISA::clear | ( | ) |
Definition at line 152 of file isa.cc.
References MipsISA::i, ArmISA::j, MipsISA::k, miscRegFile, miscRegFile_WriteMask, and MipsISA::NumMiscRegs.
Referenced by ISA().
void MipsISA::ISA::configCP | ( | ) |
Definition at line 165 of file isa.cc.
References cfg, MipsISA::CoreSpecific::CP0_Config1_C2, MipsISA::CoreSpecific::CP0_Config1_DA, MipsISA::CoreSpecific::CP0_Config1_DL, MipsISA::CoreSpecific::CP0_Config1_DS, MipsISA::CoreSpecific::CP0_Config1_EP, MipsISA::CoreSpecific::CP0_Config1_FP, MipsISA::CoreSpecific::CP0_Config1_IA, MipsISA::CoreSpecific::CP0_Config1_IL, MipsISA::CoreSpecific::CP0_Config1_IS, MipsISA::CoreSpecific::CP0_Config1_M, MipsISA::CoreSpecific::CP0_Config1_MD, MipsISA::CoreSpecific::CP0_Config1_MMU, MipsISA::CoreSpecific::CP0_Config1_PC, MipsISA::CoreSpecific::CP0_Config1_WR, MipsISA::CoreSpecific::CP0_Config2_M, MipsISA::CoreSpecific::CP0_Config2_SA, MipsISA::CoreSpecific::CP0_Config2_SL, MipsISA::CoreSpecific::CP0_Config2_SS, MipsISA::CoreSpecific::CP0_Config2_SU, MipsISA::CoreSpecific::CP0_Config2_TA, MipsISA::CoreSpecific::CP0_Config2_TL, MipsISA::CoreSpecific::CP0_Config2_TS, MipsISA::CoreSpecific::CP0_Config2_TU, MipsISA::CoreSpecific::CP0_Config3_DSPP, MipsISA::CoreSpecific::CP0_Config3_LPA, MipsISA::CoreSpecific::CP0_Config3_MT, MipsISA::CoreSpecific::CP0_Config3_SM, MipsISA::CoreSpecific::CP0_Config3_SP, MipsISA::CoreSpecific::CP0_Config3_TL, MipsISA::CoreSpecific::CP0_Config3_VEIC, MipsISA::CoreSpecific::CP0_Config3_VInt, MipsISA::CoreSpecific::CP0_Config_AR, MipsISA::CoreSpecific::CP0_Config_AT, MipsISA::CoreSpecific::CP0_Config_BE, MipsISA::CoreSpecific::CP0_Config_MT, MipsISA::CoreSpecific::CP0_Config_VI, MipsISA::CoreSpecific::CP0_EBase_CPUNum, MipsISA::CoreSpecific::CP0_IntCtl_IPPCI, MipsISA::CoreSpecific::CP0_IntCtl_IPTI, MipsISA::CoreSpecific::CP0_PerfCtr_M, MipsISA::CoreSpecific::CP0_PerfCtr_W, MipsISA::CoreSpecific::CP0_PRId_CompanyID, MipsISA::CoreSpecific::CP0_PRId_CompanyOptions, MipsISA::CoreSpecific::CP0_PRId_ProcessorID, MipsISA::CoreSpecific::CP0_PRId_Revision, MipsISA::CoreSpecific::CP0_SrsCtl_HSS, MipsISA::CoreSpecific::CP0_WatchHi_M, DPRINTF, MipsISA::mask, MipsISA::MISCREG_BADVADDR, MipsISA::MISCREG_CAUSE, MipsISA::MISCREG_CONFIG, MipsISA::MISCREG_CONFIG1, MipsISA::MISCREG_CONFIG2, MipsISA::MISCREG_CONFIG3, MipsISA::MISCREG_CONTEXT, MipsISA::MISCREG_CP0_RANDOM, MipsISA::MISCREG_EBASE, MipsISA::MISCREG_ENTRYLO0, MipsISA::MISCREG_ENTRYLO1, MipsISA::MISCREG_INDEX, MipsISA::MISCREG_INTCTL, MipsISA::MISCREG_LLADDR, MipsISA::MISCREG_MVP_CONF0, MipsISA::MISCREG_PAGEGRAIN, MipsISA::MISCREG_PAGEMASK, MipsISA::MISCREG_PERFCNT0, MipsISA::MISCREG_PRID, MipsISA::MISCREG_SRSCTL, MipsISA::MISCREG_STATUS, MipsISA::MISCREG_TC_BIND, MipsISA::MISCREG_TC_HALT, MipsISA::MISCREG_TC_STATUS, MipsISA::MISCREG_VPE_CONF0, MipsISA::MISCREG_WATCHHI0, numThreads, numVpes, panic, MipsISA::procId, readMiscRegNoEffect(), replaceBits(), setMiscRegNoEffect(), setRegMask(), and ArmISA::status.
This method doesn't need to adjust the Control Register Offset since it has already been done in the calling method (setRegWithEffect)
Definition at line 500 of file isa.cc.
References DPRINTF, miscRegFile, miscRegFile_WriteMask, and X86ISA::val.
Referenced by setMiscReg().
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Definition at line 182 of file isa.hh.
References X86ISA::reg.
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Definition at line 175 of file isa.hh.
References X86ISA::reg.
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Definition at line 169 of file isa.hh.
References X86ISA::reg.
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Definition at line 188 of file isa.hh.
References X86ISA::reg.
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Definition at line 414 of file isa.cc.
References MipsISA::MISCREG_TC_BIND, and miscRegFile.
Referenced by readMiscReg(), readMiscRegNoEffect(), setMiscReg(), setMiscRegNoEffect(), and setRegMask().
const MipsISAParams * MipsISA::ISA::params | ( | ) | const |
Definition at line 146 of file isa.cc.
References SimObject::_params.
MiscReg MipsISA::ISA::readMiscReg | ( | int | misc_reg, |
ThreadContext * | tc, | ||
ThreadID | tid = 0 |
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Definition at line 435 of file isa.cc.
References bankType, DPRINTF, getVPENum(), miscRegFile, miscRegNames, and perThreadContext.
Definition at line 421 of file isa.cc.
References bankType, DPRINTF, getVPENum(), miscRegFile, miscRegNames, and perThreadContext.
Referenced by configCP(), and updateCPU().
Definition at line 520 of file isa.cc.
References cp0Updated, and UpdateCP0.
Referenced by setMiscReg().
void MipsISA::ISA::setMiscReg | ( | int | misc_reg, |
const MiscReg & | val, | ||
ThreadContext * | tc, | ||
ThreadID | tid = 0 |
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Definition at line 476 of file isa.cc.
References bankType, DPRINTF, filterCP0Write(), ThreadContext::getCpuPtr(), getVPENum(), miscRegFile, miscRegNames, perThreadContext, and scheduleCP0Update().
Definition at line 448 of file isa.cc.
References bankType, DPRINTF, getVPENum(), miscRegFile, miscRegNames, perThreadContext, and X86ISA::val.
Referenced by configCP().
Definition at line 461 of file isa.cc.
References bankType, DPRINTF, getVPENum(), miscRegFile_WriteMask, miscRegNames, perThreadContext, and X86ISA::val.
Referenced by configCP().
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void MipsISA::ISA::updateCPU | ( | BaseCPU * | cpu | ) |
Definition at line 532 of file isa.cc.
References cp0Updated, MipsISA::haltThread(), MipsISA::MISCREG_MVP_CONF0, MipsISA::MISCREG_TC_HALT, MipsISA::MISCREG_TC_STATUS, readMiscRegNoEffect(), and MipsISA::restoreThread().
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Definition at line 72 of file isa.hh.
Referenced by ISA(), readMiscReg(), readMiscRegNoEffect(), setMiscReg(), setMiscRegNoEffect(), and setRegMask().
bool MipsISA::ISA::cp0Updated |
Definition at line 113 of file isa.hh.
Referenced by scheduleCP0Update(), and updateCPU().
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Definition at line 70 of file isa.hh.
Referenced by clear(), filterCP0Write(), getVPENum(), ISA(), readMiscReg(), readMiscRegNoEffect(), setMiscReg(), and setMiscRegNoEffect().
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Definition at line 71 of file isa.hh.
Referenced by clear(), filterCP0Write(), ISA(), and setRegMask().
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Definition at line 156 of file isa.hh.
Referenced by readMiscReg(), readMiscRegNoEffect(), setMiscReg(), setMiscRegNoEffect(), and setRegMask().
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Definition at line 61 of file isa.hh.
Referenced by configCP(), and ISA().
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Definition at line 62 of file isa.hh.
Referenced by configCP(), and ISA().