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arch
mips
types.hh
Go to the documentation of this file.
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/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*/
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#ifndef __ARCH_MIPS_TYPES_HH__
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#define __ARCH_MIPS_TYPES_HH__
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#include "
arch/generic/types.hh
"
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#include "
base/types.hh
"
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namespace
MipsISA
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{
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typedef
uint32_t
MachInst
;
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typedef
uint64_t
ExtMachInst
;
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typedef
GenericISA::DelaySlotPCState<MachInst>
PCState
;
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//used in FP convert & round function
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enum
ConvertType
{
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SINGLE_TO_DOUBLE
,
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SINGLE_TO_WORD
,
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SINGLE_TO_LONG
,
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DOUBLE_TO_SINGLE
,
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DOUBLE_TO_WORD
,
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DOUBLE_TO_LONG
,
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LONG_TO_SINGLE
,
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LONG_TO_DOUBLE
,
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LONG_TO_WORD
,
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LONG_TO_PS
,
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WORD_TO_SINGLE
,
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WORD_TO_DOUBLE
,
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WORD_TO_LONG
,
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WORD_TO_PS
,
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PL_TO_SINGLE
,
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PU_TO_SINGLE
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};
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//used in FP convert & round function
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enum
RoundMode
{
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RND_ZERO
,
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RND_DOWN
,
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RND_UP
,
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RND_NEAREST
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};
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struct
CoreSpecific
{
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CoreSpecific
()
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:
CP0_IntCtl_IPTI
(0),
CP0_IntCtl_IPPCI
(0),
CP0_SrsCtl_HSS
(0),
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CP0_PRId_CompanyOptions
(0),
CP0_PRId_CompanyID
(0),
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CP0_PRId_ProcessorID
(0),
CP0_PRId_Revision
(0),
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CP0_EBase_CPUNum
(0),
CP0_Config_BE
(0),
CP0_Config_AT
(0),
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CP0_Config_AR
(0),
CP0_Config_MT
(0),
CP0_Config_VI
(0),
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CP0_Config1_M
(0),
CP0_Config1_MMU
(0),
CP0_Config1_IS
(0),
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CP0_Config1_IL
(0),
CP0_Config1_IA
(0),
CP0_Config1_DS
(0),
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CP0_Config1_DL
(0),
CP0_Config1_DA
(0),
CP0_Config1_C2
(false),
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CP0_Config1_MD
(false),
CP0_Config1_PC
(false),
CP0_Config1_WR
(false),
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CP0_Config1_CA
(false),
CP0_Config1_EP
(false),
CP0_Config1_FP
(false),
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CP0_Config2_M
(false),
CP0_Config2_TU
(0),
CP0_Config2_TS
(0),
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CP0_Config2_TL
(0),
CP0_Config2_TA
(0),
CP0_Config2_SU
(0),
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CP0_Config2_SS
(0),
CP0_Config2_SL
(0),
CP0_Config2_SA
(0),
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CP0_Config3_M
(false),
CP0_Config3_DSPP
(false),
CP0_Config3_LPA
(false),
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CP0_Config3_VEIC
(false),
CP0_Config3_VInt
(false),
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CP0_Config3_SP
(false),
CP0_Config3_MT
(false),
CP0_Config3_SM
(false),
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CP0_Config3_TL
(false),
CP0_WatchHi_M
(false),
CP0_PerfCtr_M
(false),
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CP0_PerfCtr_W
(false),
CP0_PRId
(0),
CP0_Config
(0),
CP0_Config1
(0),
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CP0_Config2
(0),
CP0_Config3
(0)
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{ }
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// MIPS CP0 State - First individual variables
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// Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM,
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// Volume III (PRA)
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unsigned
CP0_IntCtl_IPTI
;
// Page 93, IP Timer Interrupt
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unsigned
CP0_IntCtl_IPPCI
;
// Page 94, IP Performance Counter Interrupt
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unsigned
CP0_SrsCtl_HSS
;
// Page 95, Highest Implemented Shadow Set
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unsigned
CP0_PRId_CompanyOptions
;
// Page 105, Manufacture options
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unsigned
CP0_PRId_CompanyID
;
// Page 105, Company ID - (0-255, 1=>MIPS)
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unsigned
CP0_PRId_ProcessorID
;
// Page 105
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unsigned
CP0_PRId_Revision
;
// Page 105
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unsigned
CP0_EBase_CPUNum
;
// Page 106, CPU Number in a multiprocessor
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//system
112
unsigned
CP0_Config_BE
;
// Page 108, Big/Little Endian mode
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unsigned
CP0_Config_AT
;
//Page 109
114
unsigned
CP0_Config_AR
;
//Page 109
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unsigned
CP0_Config_MT
;
//Page 109
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unsigned
CP0_Config_VI
;
//Page 109
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unsigned
CP0_Config1_M
;
// Page 110
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unsigned
CP0_Config1_MMU
;
// Page 110
119
unsigned
CP0_Config1_IS
;
// Page 110
120
unsigned
CP0_Config1_IL
;
// Page 111
121
unsigned
CP0_Config1_IA
;
// Page 111
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unsigned
CP0_Config1_DS
;
// Page 111
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unsigned
CP0_Config1_DL
;
// Page 112
124
unsigned
CP0_Config1_DA
;
// Page 112
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bool
CP0_Config1_C2
;
// Page 112
126
bool
CP0_Config1_MD
;
// Page 112 - Technically not used in MIPS32
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bool
CP0_Config1_PC
;
// Page 112
128
bool
CP0_Config1_WR
;
// Page 113
129
bool
CP0_Config1_CA
;
// Page 113
130
bool
CP0_Config1_EP
;
// Page 113
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bool
CP0_Config1_FP
;
// Page 113
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bool
CP0_Config2_M
;
// Page 114
133
unsigned
CP0_Config2_TU
;
// Page 114
134
unsigned
CP0_Config2_TS
;
// Page 114
135
unsigned
CP0_Config2_TL
;
// Page 115
136
unsigned
CP0_Config2_TA
;
// Page 115
137
unsigned
CP0_Config2_SU
;
// Page 115
138
unsigned
CP0_Config2_SS
;
// Page 115
139
unsigned
CP0_Config2_SL
;
// Page 116
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unsigned
CP0_Config2_SA
;
// Page 116
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bool
CP0_Config3_M
;
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bool
CP0_Config3_DSPP
;
// Page 117
143
bool
CP0_Config3_LPA
;
// Page 117
144
bool
CP0_Config3_VEIC
;
// Page 118
145
bool
CP0_Config3_VInt
;
// Page 118
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bool
CP0_Config3_SP
;
// Page 118
147
bool
CP0_Config3_MT
;
// Page 119
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bool
CP0_Config3_SM
;
// Page 119
149
bool
CP0_Config3_TL
;
// Page 119
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bool
CP0_WatchHi_M
;
// Page 124
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bool
CP0_PerfCtr_M
;
// Page 130
153
bool
CP0_PerfCtr_W
;
// Page 130
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// Then, whole registers
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unsigned
CP0_PRId
;
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unsigned
CP0_Config
;
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unsigned
CP0_Config1
;
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unsigned
CP0_Config2
;
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unsigned
CP0_Config3
;
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};
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}
// namespace MipsISA
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#endif
types.hh
MipsISA::CoreSpecific::CP0_PerfCtr_M
bool CP0_PerfCtr_M
Definition:
types.hh:152
MipsISA::WORD_TO_LONG
Definition:
types.hh:62
MipsISA::CoreSpecific::CP0_PerfCtr_W
bool CP0_PerfCtr_W
Definition:
types.hh:153
MipsISA::CoreSpecific::CP0_Config1_M
unsigned CP0_Config1_M
Definition:
types.hh:117
MipsISA::CoreSpecific::CP0_IntCtl_IPTI
unsigned CP0_IntCtl_IPTI
Definition:
types.hh:103
MipsISA::CoreSpecific::CP0_Config1_WR
bool CP0_Config1_WR
Definition:
types.hh:128
MipsISA::LONG_TO_WORD
Definition:
types.hh:57
MipsISA::RND_UP
Definition:
types.hh:73
MipsISA::CoreSpecific::CP0_EBase_CPUNum
unsigned CP0_EBase_CPUNum
Definition:
types.hh:110
MipsISA::CoreSpecific::CP0_Config3_TL
bool CP0_Config3_TL
Definition:
types.hh:149
MipsISA::CoreSpecific::CP0_Config_AR
unsigned CP0_Config_AR
Definition:
types.hh:114
MipsISA::CoreSpecific::CP0_Config
unsigned CP0_Config
Definition:
types.hh:158
MipsISA::SINGLE_TO_WORD
Definition:
types.hh:48
MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition:
types.hh:41
MipsISA::CoreSpecific::CP0_Config2
unsigned CP0_Config2
Definition:
types.hh:160
MipsISA::CoreSpecific::CoreSpecific
CoreSpecific()
Definition:
types.hh:78
MipsISA::CoreSpecific::CP0_Config2_SS
unsigned CP0_Config2_SS
Definition:
types.hh:138
MipsISA::CoreSpecific::CP0_Config3_LPA
bool CP0_Config3_LPA
Definition:
types.hh:143
MipsISA::CoreSpecific::CP0_Config1_MMU
unsigned CP0_Config1_MMU
Definition:
types.hh:118
MipsISA::CoreSpecific::CP0_Config1_DS
unsigned CP0_Config1_DS
Definition:
types.hh:122
MipsISA::CoreSpecific::CP0_PRId_ProcessorID
unsigned CP0_PRId_ProcessorID
Definition:
types.hh:108
MipsISA::CoreSpecific::CP0_Config1_MD
bool CP0_Config1_MD
Definition:
types.hh:126
MipsISA::CoreSpecific::CP0_Config1_DA
unsigned CP0_Config1_DA
Definition:
types.hh:124
MipsISA::CoreSpecific::CP0_Config3_SP
bool CP0_Config3_SP
Definition:
types.hh:146
MipsISA::CoreSpecific::CP0_Config1_EP
bool CP0_Config1_EP
Definition:
types.hh:130
MipsISA::MachInst
uint32_t MachInst
Definition:
types.hh:40
MipsISA::CoreSpecific::CP0_Config3_VEIC
bool CP0_Config3_VEIC
Definition:
types.hh:144
MipsISA::CoreSpecific::CP0_Config1_FP
bool CP0_Config1_FP
Definition:
types.hh:131
MipsISA::CoreSpecific::CP0_Config2_M
bool CP0_Config2_M
Definition:
types.hh:132
MipsISA::LONG_TO_PS
Definition:
types.hh:58
MipsISA::CoreSpecific::CP0_Config3_DSPP
bool CP0_Config3_DSPP
Definition:
types.hh:142
MipsISA::CoreSpecific::CP0_Config_AT
unsigned CP0_Config_AT
Definition:
types.hh:113
MipsISA::CoreSpecific::CP0_Config3_M
bool CP0_Config3_M
Definition:
types.hh:141
MipsISA::CoreSpecific::CP0_Config1_IS
unsigned CP0_Config1_IS
Definition:
types.hh:119
MipsISA::CoreSpecific::CP0_Config2_TU
unsigned CP0_Config2_TU
Definition:
types.hh:133
MipsISA::CoreSpecific::CP0_Config1_IA
unsigned CP0_Config1_IA
Definition:
types.hh:121
MipsISA::WORD_TO_PS
Definition:
types.hh:63
MipsISA::WORD_TO_SINGLE
Definition:
types.hh:60
MipsISA::CoreSpecific::CP0_PRId_CompanyID
unsigned CP0_PRId_CompanyID
Definition:
types.hh:107
GenericISA::DelaySlotPCState
Definition:
types.hh:284
MipsISA::CoreSpecific::CP0_Config3
unsigned CP0_Config3
Definition:
types.hh:161
MipsISA::CoreSpecific::CP0_Config_VI
unsigned CP0_Config_VI
Definition:
types.hh:116
MipsISA::PU_TO_SINGLE
Definition:
types.hh:66
MipsISA::CoreSpecific::CP0_Config1_IL
unsigned CP0_Config1_IL
Definition:
types.hh:120
MipsISA::CoreSpecific::CP0_Config3_MT
bool CP0_Config3_MT
Definition:
types.hh:147
MipsISA::LONG_TO_SINGLE
Definition:
types.hh:55
MipsISA::CoreSpecific::CP0_Config2_TS
unsigned CP0_Config2_TS
Definition:
types.hh:134
MipsISA::SINGLE_TO_DOUBLE
Definition:
types.hh:47
MipsISA::CoreSpecific::CP0_Config1_CA
bool CP0_Config1_CA
Definition:
types.hh:129
MipsISA::CoreSpecific::CP0_Config2_TL
unsigned CP0_Config2_TL
Definition:
types.hh:135
MipsISA::CoreSpecific::CP0_PRId
unsigned CP0_PRId
Definition:
types.hh:157
MipsISA::SINGLE_TO_LONG
Definition:
types.hh:49
MipsISA::CoreSpecific::CP0_Config2_TA
unsigned CP0_Config2_TA
Definition:
types.hh:136
types.hh
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
MipsISA::LONG_TO_DOUBLE
Definition:
types.hh:56
MipsISA::WORD_TO_DOUBLE
Definition:
types.hh:61
MipsISA::CoreSpecific::CP0_PRId_CompanyOptions
unsigned CP0_PRId_CompanyOptions
Definition:
types.hh:106
MipsISA::RND_NEAREST
Definition:
types.hh:74
MipsISA::CoreSpecific::CP0_Config1_C2
bool CP0_Config1_C2
Definition:
types.hh:125
MipsISA::CoreSpecific::CP0_Config3_SM
bool CP0_Config3_SM
Definition:
types.hh:148
MipsISA::CoreSpecific::CP0_Config_MT
unsigned CP0_Config_MT
Definition:
types.hh:115
MipsISA::CoreSpecific::CP0_Config1_PC
bool CP0_Config1_PC
Definition:
types.hh:127
MipsISA::CoreSpecific::CP0_Config2_SU
unsigned CP0_Config2_SU
Definition:
types.hh:137
MipsISA::PL_TO_SINGLE
Definition:
types.hh:65
MipsISA::DOUBLE_TO_SINGLE
Definition:
types.hh:51
MipsISA::DOUBLE_TO_WORD
Definition:
types.hh:52
MipsISA::CoreSpecific::CP0_Config_BE
unsigned CP0_Config_BE
Definition:
types.hh:112
MipsISA::CoreSpecific::CP0_PRId_Revision
unsigned CP0_PRId_Revision
Definition:
types.hh:109
MipsISA::CoreSpecific::CP0_IntCtl_IPPCI
unsigned CP0_IntCtl_IPPCI
Definition:
types.hh:104
MipsISA::ConvertType
ConvertType
Definition:
types.hh:46
MipsISA::CoreSpecific
Definition:
types.hh:77
MipsISA::CoreSpecific::CP0_Config1_DL
unsigned CP0_Config1_DL
Definition:
types.hh:123
MipsISA::RoundMode
RoundMode
Definition:
types.hh:70
MipsISA::CoreSpecific::CP0_Config2_SA
unsigned CP0_Config2_SA
Definition:
types.hh:140
MipsISA::CoreSpecific::CP0_Config2_SL
unsigned CP0_Config2_SL
Definition:
types.hh:139
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition:
types.hh:43
MipsISA::DOUBLE_TO_LONG
Definition:
types.hh:53
MipsISA::RND_ZERO
Definition:
types.hh:71
MipsISA::CoreSpecific::CP0_WatchHi_M
bool CP0_WatchHi_M
Definition:
types.hh:151
MipsISA::CoreSpecific::CP0_SrsCtl_HSS
unsigned CP0_SrsCtl_HSS
Definition:
types.hh:105
MipsISA::CoreSpecific::CP0_Config1
unsigned CP0_Config1
Definition:
types.hh:159
MipsISA::RND_DOWN
Definition:
types.hh:72
MipsISA::CoreSpecific::CP0_Config3_VInt
bool CP0_Config3_VInt
Definition:
types.hh:145
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