#include <compute_unit.hh>

Inheritance diagram for ComputeUnit:

Classes
class	CUExitCallback

class	DataPort
	Data access Port. More...

class	DTLBPort
	Data TLB port. More...

class	ITLBPort

class	LDSPort
	the port intended to communicate between the CU and its LDS More...

class	SQCPort

class	waveIdentifier

class	waveQueue

Public Types
typedef ComputeUnitParams	Params

typedef std::unordered_map < Addr, std::pair< int, int > >	pageDataStruct

Public Types inherited from MemObject
typedef MemObjectParams	Params

Public Types inherited from ClockedObject
typedef ClockedObjectParams	Params
	Parameters of ClockedObject. More...

Public Types inherited from SimObject
typedef SimObjectParams	Params

Public Member Functions
void	registerEvent (uint32_t simdId, uint32_t regIdx, uint32_t operandSize, uint64_t when, uint8_t newStatus)

void	updateEvents ()

	ComputeUnit (const Params *p)

	~ComputeUnit ()

int	spBypassLength ()

int	dpBypassLength ()

int	storeBusLength ()

int	loadBusLength ()

int	wfSize () const

void	resizeRegFiles (int num_cregs, int num_sregs, int num_dregs)

void	exec ()

void	initiateFetch (Wavefront *wavefront)

void	fetch (PacketPtr pkt, Wavefront *wavefront)

void	fillKernelState (Wavefront w, NDRange ndr)

void	startWavefront (Wavefront w, int waveId, LdsChunk ldsChunk, NDRange *ndr)

void	StartWorkgroup (NDRange *ndr)

int	ReadyWorkgroup (NDRange *ndr)

bool	isVecAlu (int unitId)

bool	isGlbMem (int unitId)

bool	isShrMem (int unitId)

int	GlbMemUnitId ()

int	ShrMemUnitId ()

int	nextGlbRdBus ()

int	nextLocRdBus ()

int	AllAtBarrier (uint32_t _barrier_id, uint32_t bcnt, uint32_t bslots)

bool	cedeSIMD (int simdId, int wfSlotId)

template<typename c0 , typename c1 >
void	doSmReturn (GPUDynInstPtr gpuDynInst)

virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

void	sendRequest (GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt)

void	sendSyncRequest (GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt)

void	injectGlobalMemFence (GPUDynInstPtr gpuDynInst, bool kernelLaunch=true, RequestPtr req=nullptr)

void	handleMemPacket (PacketPtr pkt, int memport_index)

bool	processTimingPacket (PacketPtr pkt)

void	processFetchReturn (PacketPtr pkt)

void	updatePageDivergenceDist (Addr addr)

MasterID	masterId ()

bool	isDone () const

bool	isSimdDone (uint32_t) const

void	updateInstStats (GPUDynInstPtr gpuDynInst)

void	regStats ()
	Register statistics for this object. More...

LdsState &	getLds () const

int32_t	getRefCounter (const uint32_t dispatchId, const uint32_t wgId) const

int	cacheLineSize () const

bool	sendToLds (GPUDynInstPtr gpuDynInst) __attribute__((warn_unused_result))
	send a general request to the LDS make sure to look at the return value here as your request might be NACK'd and returning false means that you have to have some backup plan More...

LDSPort *	getLdsPort () const

virtual BaseMasterPort &	getMasterPort (const std::string &if_name, PortID idx)
	Get a master port with a given name and index. More...

uint64_t	getAndIncSeqNum ()

Public Member Functions inherited from MemObject
const Params *	params () const

	MemObject (const Params *params)

virtual BaseSlavePort &	getSlavePort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a slave port with a given name and index. More...

Public Member Functions inherited from ClockedObject
	ClockedObject (const ClockedObjectParams *p)

const Params *	params () const

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Enums::PwrState	pwrState () const

std::string	pwrStateName () const

std::vector< double >	pwrStateWeights () const
	Returns the percentage residency for each power state. More...

void	computeStats ()
	Record stats values like state residency by computing the time difference from previous update. More...

void	pwrState (Enums::PwrState)

void	regStats () override
	Register statistics for this object. More...

Public Member Functions inherited from SimObject
const Params *	params () const

	SimObject (const Params *_params)

virtual	~SimObject ()

virtual const std::string	name () const

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	resetStats ()
	Reset statistics associated with this object. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from EventManager
	EventManager (EventManager &em)

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick)-1)

void	setCurTick (Tick newVal)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from Clocked
void	updateClockPeriod () const
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Public Attributes
FetchStage	fetchStage

ScoreboardCheckStage	scoreboardCheckStage

ScheduleStage	scheduleStage

ExecStage	execStage

GlobalMemPipeline	globalMemoryPipe

LocalMemPipeline	localMemoryPipe

std::vector< std::vector < Wavefront * > >	readyList

std::vector< std::vector < std::pair< Wavefront *, WAVE_STATUS > > >	waveStatusList

std::vector< std::pair < Wavefront *, DISPATCH_STATUS > >	dispatchList

int	rrNextMemID

int	rrNextALUWp

std::vector< std::vector < Wavefront * > >	wfList

int	cu_id

std::vector< VectorRegisterFile * >	vrf

int	numSIMDs

int	spBypassPipeLength

int	dpBypassPipeLength

int	issuePeriod

int	numGlbMemUnits

int	numLocMemUnits

std::vector< uint64_t >	lastExecCycle

bool	perLaneTLB

int	prefetchDepth

int	prefetchStride

std::vector< Addr >	lastVaddrCU

std::vector< std::vector< Addr > >	lastVaddrSimd

std::vector< std::vector < std::vector< Addr > > >	lastVaddrWF

Enums::PrefetchType	prefetchType

EXEC_POLICY	exec_policy

bool	xact_cas_mode

bool	debugSegFault

bool	functionalTLB

bool	localMemBarrier

bool	countPages

Shader *	shader

uint32_t	barrier_id

std::vector< WaitClass >	aluPipe

std::vector< WaitClass >	wfWait

std::vector< WaitClass >	vrfToGlobalMemPipeBus

std::vector< WaitClass >	vrfToLocalMemPipeBus

int	nextGlbMemBus

int	nextLocMemBus

WaitClass	glbMemToVrfBus

WaitClass	locMemToVrfBus

uint32_t	vrfToCoalescerBusWidth

uint32_t	coalescerToVrfBusWidth

uint32_t	numCyclesPerStoreTransfer

uint32_t	numCyclesPerLoadTransfer

Tick	req_tick_latency

Tick	resp_tick_latency

std::vector< int >	vectorRegsReserved

uint32_t	numVecRegsPerSimd

std::vector< std::pair < uint32_t, uint32_t > >	regIdxVec

std::vector< uint64_t >	timestampVec

std::vector< uint8_t >	statusVec

std::map< Addr, int >	pagesTouched

Stats::Scalar	vALUInsts

Stats::Formula	vALUInstsPerWF

Stats::Scalar	sALUInsts

Stats::Formula	sALUInstsPerWF

Stats::Scalar	instCyclesVALU

Stats::Scalar	instCyclesSALU

Stats::Scalar	threadCyclesVALU

Stats::Formula	vALUUtilization

Stats::Scalar	ldsNoFlatInsts

Stats::Formula	ldsNoFlatInstsPerWF

Stats::Scalar	flatVMemInsts

Stats::Formula	flatVMemInstsPerWF

Stats::Scalar	flatLDSInsts

Stats::Formula	flatLDSInstsPerWF

Stats::Scalar	vectorMemWrites

Stats::Formula	vectorMemWritesPerWF

Stats::Scalar	vectorMemReads

Stats::Formula	vectorMemReadsPerWF

Stats::Scalar	scalarMemWrites

Stats::Formula	scalarMemWritesPerWF

Stats::Scalar	scalarMemReads

Stats::Formula	scalarMemReadsPerWF

Stats::Scalar	tlbRequests

Stats::Scalar	tlbCycles

Stats::Formula	tlbLatency

Stats::Vector	hitsPerTLBLevel

Stats::Scalar	ldsBankAccesses

Stats::Distribution	ldsBankConflictDist

Stats::Distribution	pageDivergenceDist

Stats::Scalar	dynamicGMemInstrCnt

Stats::Scalar	dynamicLMemInstrCnt

Stats::Scalar	wgBlockedDueLdsAllocation

Stats::Scalar	numInstrExecuted

Stats::Distribution	execRateDist

Stats::Scalar	numVecOpsExecuted

Stats::Scalar	totalCycles

Stats::Formula	vpc

Stats::Formula	ipc

Stats::Distribution	controlFlowDivergenceDist

Stats::Distribution	activeLanesPerGMemInstrDist

Stats::Distribution	activeLanesPerLMemInstrDist

Stats::Formula	numALUInstsExecuted

Stats::Scalar	numTimesWgBlockedDueVgprAlloc

Stats::Scalar	numCASOps

Stats::Scalar	numFailedCASOps

Stats::Scalar	completedWfs

std::vector< bool >	vectorAluInstAvail

int	shrMemInstAvail

int	glbMemInstAvail

pageDataStruct	pageAccesses

CUExitCallback *	cuExitCallback

LDSPort *	ldsPort = nullptr
	The port to access the Local Data Store Can be connected to a LDS object. More...

std::vector< DataPort * >	memPort
	The memory port for SIMD data accesses. More...

std::vector< DTLBPort * >	tlbPort

SQCPort *	sqcPort

ITLBPort *	sqcTLBPort

std::map< unsigned, waveQueue >	xactCasLoadMap

Protected Attributes
MasterID	_masterId

LdsState &	lds

Protected Attributes inherited from ClockedObject
Enums::PwrState	_currPwrState
	To keep track of the current power state. More...

Tick	prvEvalTick

Stats::Scalar	numPwrStateTransitions

Stats::Distribution	pwrStateClkGateDist

Stats::Vector	pwrStateResidencyTicks

Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Private Attributes
const int	_cacheLineSize

uint64_t	globalSeqNum

int	wavefrontSize

GPUStaticInst *	kernelLaunchInst

Additional Inherited Members
Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Get the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)

static void	unserializeGlobals (CheckpointIn &cp)

Static Public Attributes inherited from Serializable
static int	ckptCount = 0

static int	ckptMaxCount = 0

static int	ckptPrevCount = -1

Protected Member Functions inherited from Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

Detailed Description

Definition at line 93 of file compute_unit.hh.

Member Typedef Documentation

typedef std::unordered_map<Addr, std::pair<int, int> > ComputeUnit::pageDataStruct

Definition at line 398 of file compute_unit.hh.

typedef ComputeUnitParams ComputeUnit::Params

Definition at line 134 of file compute_unit.hh.

Constructor & Destructor Documentation

ComputeUnit::ComputeUnit ( const Params * p )

This check is necessary because std::bitset only provides conversion to unsigned long or unsigned long long via to_ulong() or to_ullong(). there are * a few places in the code where to_ullong() is used, however if VSZ is larger than a value the host can support then bitset will throw a runtime exception. we should remove all use of to_long() or to_ullong() so we can have VSZ greater than 64b, however until that is done this assert is required.

Definition at line 59 of file compute_unit.cc.

References coalescerToVrfBusWidth, cuExitCallback, exec_policy, fatal, fatal_if(), ArmISA::i, isPowerOf2(), ArmISA::j, MipsISA::k, lastExecCycle, lastVaddrCU, lastVaddrSimd, lastVaddrWF, lds, memPort, numCyclesPerLoadTransfer, numCyclesPerStoreTransfer, numSIMDs, numVecRegsPerSimd, OLDEST, perLaneTLB, registerExitCallback(), RR, LdsState::setParent(), tlbPort, vrf, vrfToCoalescerBusWidth, wavefrontSize, wfList, wfSize(), and xactCasLoadMap.

ComputeUnit::~ComputeUnit ( )

Definition at line 160 of file compute_unit.cc.

References cuExitCallback, dispatchList, ArmISA::i, ArmISA::j, lastVaddrCU, lastVaddrSimd, ldsPort, Shader::n_wf, numSIMDs, readyList, shader, vectorAluInstAvail, waveStatusList, and wfList.

Member Function Documentation

int ComputeUnit::AllAtBarrier	(	uint32_t	_barrier_id,
		uint32_t	bcnt,
		uint32_t	bslots
	)

Definition at line 446 of file compute_unit.cc.

References Wavefront::barrierCnt, Wavefront::barrierId, cu_id, DPRINTF, Shader::n_wf, numSIMDs, Wavefront::outstandingReqs, Wavefront::S_RUNNING, shader, Wavefront::status, MipsISA::w, and wfList.

Referenced by Wavefront::ready().

int ComputeUnit::cacheLineSize ( ) const

inline

Definition at line 393 of file compute_unit.hh.

References _cacheLineSize.

Referenced by FetchUnit::initiateFetch().

bool ComputeUnit::cedeSIMD	(	int	simdId,
		int	wfSlotId
	)

Definition at line 484 of file compute_unit.cc.

References ComputeUnit::waveIdentifier::simdId, ComputeUnit::waveIdentifier::wfSlotId, xact_cas_mode, and xactCasLoadMap.

Referenced by ScoreboardCheckStage::exec().

template<typename c0 , typename c1 >

void ComputeUnit::doSmReturn ( GPUDynInstPtr gpuDynInst )

int ComputeUnit::dpBypassLength ( )

inline

Definition at line 248 of file compute_unit.hh.

References dpBypassPipeLength.

Referenced by VectorRegisterFile::exec().

void ComputeUnit::exec ( )

Definition at line 532 of file compute_unit.cc.

References FetchStage::exec(), ScheduleStage::exec(), LocalMemPipeline::exec(), GlobalMemPipeline::exec(), ScoreboardCheckStage::exec(), ExecStage::exec(), execStage, fetchStage, globalMemoryPipe, localMemoryPipe, scheduleStage, scoreboardCheckStage, totalCycles, and updateEvents().

void ComputeUnit::fetch	(	PacketPtr	pkt,
		Wavefront *	wavefront
	)

void ComputeUnit::fillKernelState	(	Wavefront *	w,
		NDRange *	ndr
	)

uint64_t ComputeUnit::getAndIncSeqNum ( )

inline

Definition at line 769 of file compute_unit.hh.

References globalSeqNum.

Referenced by StartWorkgroup().

LdsState& ComputeUnit::getLds ( ) const

inline

Definition at line 385 of file compute_unit.hh.

References lds.

Referenced by HsailISA::Ret::execute().

LDSPort* ComputeUnit::getLdsPort ( ) const

inline

Definition at line 705 of file compute_unit.hh.

References ldsPort.

virtual BaseMasterPort& ComputeUnit::getMasterPort	(	const std::string &	if_name,
		PortID	idx
	)

inlinevirtual

Get a master port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic base master port.

Parameters

if_name	Port name
idx	Index in the case of a VectorPort

Returns: A reference to the given port

Reimplemented from MemObject.

Definition at line 722 of file compute_unit.hh.

References csprintf(), fatal, ldsPort, memPort, SimObject::name(), panic, sqcPort, sqcTLBPort, and tlbPort.

int32_t ComputeUnit::getRefCounter	(	const uint32_t	dispatchId,
		const uint32_t	wgId
	)		const

Definition at line 1760 of file compute_unit.cc.

References LdsState::getRefCounter(), and lds.

Referenced by Wavefront::ready().

int ComputeUnit::GlbMemUnitId ( )

inline

Definition at line 268 of file compute_unit.hh.

References GLBMEM_PIPE.

Referenced by ScoreboardCheckStage::exec(), Wavefront::exec(), and Wavefront::updateResources().

void ComputeUnit::handleMemPacket	(	PacketPtr	pkt,
		int	memport_index
	)

void ComputeUnit::init ( )

virtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from SimObject.

Definition at line 548 of file compute_unit.cc.

References aluPipe, BLOCKED, dispatchList, EMPTY, execStage, fatal_if(), fetchStage, Shader::funcargs_size, glbMemInstAvail, glbMemToVrfBus, globalMemoryPipe, ArmISA::i, WaitClass::init(), FetchStage::init(), ScheduleStage::init(), LocalMemPipeline::init(), GlobalMemPipeline::init(), ScoreboardCheckStage::init(), ExecStage::init(), ArmISA::j, localMemoryPipe, locMemToVrfBus, Shader::n_wf, nextGlbMemBus, nextLocMemBus, numGlbMemUnits, numLocMemUnits, numSIMDs, readyList, scheduleStage, scoreboardCheckStage, shader, shrMemInstAvail, Shader::tick_cnt, Shader::ticks(), vectorAluInstAvail, vectorRegsReserved, vrfToGlobalMemPipeBus, vrfToLocalMemPipeBus, wavefrontSize, waveStatusList, wfList, and wfWait.

void ComputeUnit::initiateFetch ( Wavefront * wavefront )

void ComputeUnit::injectGlobalMemFence	(	GPUDynInstPtr	gpuDynInst,
		bool	kernelLaunch = `true`,
		RequestPtr	req = `nullptr`
	)

Definition at line 942 of file compute_unit.cc.

References Request::isAcquire(), Request::isRelease(), Request::KERNEL, masterId(), MemCmd::MemFenceReq, sendSyncRequest(), Request::setFlags(), and Request::setPaddr().

Referenced by HsailISA::Ret::execute(), HsailISA::MemFence::initiateAcc(), and StartWorkgroup().

bool ComputeUnit::isDone ( ) const

bool ComputeUnit::isGlbMem ( int unitId )

inline

Definition at line 266 of file compute_unit.hh.

References GLBMEM_PIPE.

Referenced by ExecStage::collectStatistics().

bool ComputeUnit::isShrMem ( int unitId )

inline

Definition at line 267 of file compute_unit.hh.

References LDSMEM_PIPE.

Referenced by ExecStage::collectStatistics().

bool ComputeUnit::isSimdDone ( uint32_t simdId ) const

Definition at line 1766 of file compute_unit.cc.

References aluPipe, ArmISA::i, Shader::n_wf, numGlbMemUnits, numLocMemUnits, numSIMDs, Wavefront::S_STOPPED, shader, ArmISA::status, vrfToGlobalMemPipeBus, vrfToLocalMemPipeBus, and wfList.

Referenced by isDone().

bool ComputeUnit::isVecAlu ( int unitId )

inline

Definition at line 265 of file compute_unit.hh.

References SIMD0, and SIMD3.

Referenced by ExecStage::collectStatistics().

int ComputeUnit::loadBusLength ( )

inline

Definition at line 250 of file compute_unit.hh.

References numCyclesPerLoadTransfer.

Referenced by LdsState::processPacket().

MasterID ComputeUnit::masterId ( )

inline

Definition at line 293 of file compute_unit.hh.

References _masterId.

Referenced by FetchUnit::initiateFetch(), and injectGlobalMemFence().

int ComputeUnit::nextGlbRdBus ( )

inline

Definition at line 270 of file compute_unit.hh.

References nextGlbMemBus, and numGlbMemUnits.

Referenced by Wavefront::exec(), and Wavefront::updateResources().

int ComputeUnit::nextLocRdBus ( )

inline

Definition at line 271 of file compute_unit.hh.

References nextLocMemBus, and numLocMemUnits.

Referenced by Wavefront::exec(), and Wavefront::updateResources().

void ComputeUnit::processFetchReturn ( PacketPtr pkt )

bool ComputeUnit::processTimingPacket ( PacketPtr pkt )

int ComputeUnit::ReadyWorkgroup ( NDRange * ndr )

Definition at line 364 of file compute_unit.cc.

References LdsState::canReserve(), ArmISA::d, DPRINTF, HsaQueueEntry::dRegCount, HsaQueueEntry::gdSize, ArmISA::i, ArmISA::j, lds, HsaQueueEntry::ldsSize, Shader::n_wf, numSIMDs, numTimesWgBlockedDueVgprAlloc, numVecRegsPerSimd, NDRange::q, Wavefront::S_STOPPED, shader, HsaQueueEntry::sRegCount, ArmISA::status, vrf, wfList, wfSize(), wgBlockedDueLdsAllocation, NDRange::wgId, and HsaQueueEntry::wgSize.

void ComputeUnit::registerEvent	(	uint32_t	simdId,
		uint32_t	regIdx,
		uint32_t	operandSize,
		uint64_t	when,
		uint8_t	newStatus
	)

inline

Definition at line 221 of file compute_unit.hh.

References numVecRegsPerSimd, regIdxVec, statusVec, and timestampVec.

Referenced by VectorRegisterFile::exec().

void ComputeUnit::regStats ( )

virtual

Register statistics for this object.

Reimplemented from SimObject.

Definition at line 1398 of file compute_unit.cc.

References activeLanesPerGMemInstrDist, activeLanesPerLMemInstrDist, completedWfs, controlFlowDivergenceDist, csprintf(), Stats::DataWrap< Derived, InfoProxyType >::desc(), dynamicGMemInstrCnt, dynamicLMemInstrCnt, execRateDist, execStage, fetchStage, flatLDSInsts, flatLDSInstsPerWF, flatVMemInsts, flatVMemInstsPerWF, globalMemoryPipe, hitsPerTLBLevel, ArmISA::i, Stats::VectorBase< Derived, Stor >::init(), Stats::Distribution::init(), instCyclesSALU, instCyclesVALU, ipc, ldsBankAccesses, ldsBankConflictDist, ldsNoFlatInsts, ldsNoFlatInstsPerWF, localMemoryPipe, SimObject::name(), Stats::DataWrap< Derived, InfoProxyType >::name(), numALUInstsExecuted, numCASOps, numFailedCASOps, numInstrExecuted, numTimesWgBlockedDueVgprAlloc, numVecOpsExecuted, pageDivergenceDist, FetchStage::regStats(), ScheduleStage::regStats(), ScoreboardCheckStage::regStats(), ExecStage::regStats(), LocalMemPipeline::regStats(), GlobalMemPipeline::regStats(), ClockedObject::regStats(), sALUInsts, sALUInstsPerWF, scalarMemReads, scalarMemReadsPerWF, scalarMemWrites, scalarMemWritesPerWF, scheduleStage, scoreboardCheckStage, Stats::DataWrapVec< Derived, InfoProxyType >::subname(), threadCyclesVALU, tlbCycles, tlbLatency, tlbRequests, totalCycles, vALUInsts, vALUInstsPerWF, vALUUtilization, vectorMemReads, vectorMemReadsPerWF, vectorMemWrites, vectorMemWritesPerWF, vpc, wfSize(), and wgBlockedDueLdsAllocation.

void ComputeUnit::resizeRegFiles	(	int	num_cregs,
		int	num_sregs,
		int	num_dregs
	)

void ComputeUnit::sendRequest	(	GPUDynInstPtr	gpuDynInst,
		int	index,
		PacketPtr	pkt
	)

Definition at line 744 of file compute_unit.cc.

References Packet::cmd, cu_id, curTick(), Packet::dataStatic(), debugSegFault, DPRINTF, fatal, Process::fixupStackFault(), functionalTLB, Packet::getAddr(), Request::getAsid(), Request::getFlags(), Request::getPaddr(), Request::getPC(), ThreadContext::getProcessPtr(), Packet::getPtr(), Request::getSize(), Packet::getSize(), Request::getVaddr(), Shader::gpuTc, Request::hasPaddr(), Request::hasSize(), hitsPerTLBLevel, MipsISA::index, Packet::isRead(), Packet::isWrite(), Request::masterId(), MemCmd::MemFenceReq, memPort, MipsISA::p, panic, perLaneTLB, Process::pTable, BaseTLB::Read, Packet::req, req_tick_latency, safe_cast(), X86ISA::GpuTLB::TranslationState::saved, EventManager::schedule(), Packet::senderState, Request::setVirt(), shader, X86ISA::size(), Shader::timingSim, tlbCycles, X86ISA::GpuTLB::TranslationState::tlbEntry, tlbPort, tlbRequests, PageTableBase::translate(), updatePageDivergenceDist(), MipsISA::vaddr, and BaseTLB::Write.

void ComputeUnit::sendSyncRequest	(	GPUDynInstPtr	gpuDynInst,
		int	index,
		PacketPtr	pkt
	)

Definition at line 924 of file compute_unit.cc.

References cu_id, curTick(), DPRINTF, Request::getPaddr(), memPort, Packet::req, req_tick_latency, EventManager::schedule(), and Packet::senderState.

Referenced by injectGlobalMemFence().

bool ComputeUnit::sendToLds ( GPUDynInstPtr gpuDynInst )

send a general request to the LDS make sure to look at the return value here as your request might be NACK'd and returning false means that you have to have some backup plan

Definition at line 1797 of file compute_unit.cc.

References ldsPort, MemCmd::ReadReq, Packet::senderState, ComputeUnit::LDSPort::sendTimingReq(), and Request::setPaddr().

Referenced by LocalMemPipeline::exec().

int ComputeUnit::ShrMemUnitId ( )

inline

Definition at line 269 of file compute_unit.hh.

References LDSMEM_PIPE.

Referenced by ScoreboardCheckStage::exec(), Wavefront::exec(), and Wavefront::updateResources().

int ComputeUnit::spBypassLength ( )

inline

Definition at line 247 of file compute_unit.hh.

References spBypassPipeLength.