| _cacheLineSize | ComputeUnit | private |
| _currPwrState | ClockedObject | protected |
| _masterId | ComputeUnit | protected |
| _params | SimObject | protected |
| activeLanesPerGMemInstrDist | ComputeUnit | |
| activeLanesPerLMemInstrDist | ComputeUnit | |
| AllAtBarrier(uint32_t _barrier_id, uint32_t bcnt, uint32_t bslots) | ComputeUnit | |
| aluPipe | ComputeUnit | |
| barrier_id | ComputeUnit | |
| cacheLineSize() const | ComputeUnit | inline |
| cedeSIMD(int simdId, int wfSlotId) | ComputeUnit | |
| ckptCount | Serializable | static |
| ckptMaxCount | Serializable | static |
| ckptPrevCount | Serializable | static |
| Clocked(ClockDomain &clk_domain) | Clocked | inlineprotected |
| Clocked(Clocked &)=delete | Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | Clocked | inline |
| ClockedObject(const ClockedObjectParams *p) | ClockedObject | |
| clockPeriod() const | Clocked | inline |
| coalescerToVrfBusWidth | ComputeUnit | |
| completedWfs | ComputeUnit | |
| computeStats() | ClockedObject | |
| ComputeUnit(const Params *p) | ComputeUnit | |
| controlFlowDivergenceDist | ComputeUnit | |
| countPages | ComputeUnit | |
| cu_id | ComputeUnit | |
| cuExitCallback | ComputeUnit | |
| curCycle() const | Clocked | inline |
| currentSection() | Serializable | static |
| cyclesToTicks(Cycles c) const | Clocked | inline |
| debugSegFault | ComputeUnit | |
| deschedule(Event &event) | EventManager | inline |
| deschedule(Event *event) | EventManager | inline |
| dispatchList | ComputeUnit | |
| doSmReturn(GPUDynInstPtr gpuDynInst) | ComputeUnit | |
| dpBypassLength() | ComputeUnit | inline |
| dpBypassPipeLength | ComputeUnit | |
| drain() override | SimObject | inlinevirtual |
| Drainable() | Drainable | protected |
| drainResume() | Drainable | inlineprotectedvirtual |
| drainState() const | Drainable | inline |
| dynamicGMemInstrCnt | ComputeUnit | |
| dynamicLMemInstrCnt | ComputeUnit | |
| EventManager(EventManager &em) | EventManager | inline |
| EventManager(EventManager *em) | EventManager | inline |
| EventManager(EventQueue *eq) | EventManager | inline |
| eventq | EventManager | protected |
| eventQueue() const | EventManager | inline |
| exec() | ComputeUnit | |
| exec_policy | ComputeUnit | |
| execRateDist | ComputeUnit | |
| execStage | ComputeUnit | |
| fetch(PacketPtr pkt, Wavefront *wavefront) | ComputeUnit | |
| fetchStage | ComputeUnit | |
| fillKernelState(Wavefront *w, NDRange *ndr) | ComputeUnit | |
| find(const char *name) | SimObject | static |
| flatLDSInsts | ComputeUnit | |
| flatLDSInstsPerWF | ComputeUnit | |
| flatVMemInsts | ComputeUnit | |
| flatVMemInstsPerWF | ComputeUnit | |
| frequency() const | Clocked | inline |
| functionalTLB | ComputeUnit | |
| getAndIncSeqNum() | ComputeUnit | inline |
| getLds() const | ComputeUnit | inline |
| getLdsPort() const | ComputeUnit | inline |
| getMasterPort(const std::string &if_name, PortID idx) | ComputeUnit | inlinevirtual |
| getProbeManager() | SimObject | |
| getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const | ComputeUnit | |
| getSlavePort(const std::string &if_name, PortID idx=InvalidPortID) | MemObject | virtual |
| glbMemInstAvail | ComputeUnit | |
| glbMemToVrfBus | ComputeUnit | |
| GlbMemUnitId() | ComputeUnit | inline |
| globalMemoryPipe | ComputeUnit | |
| globalSeqNum | ComputeUnit | private |
| handleMemPacket(PacketPtr pkt, int memport_index) | ComputeUnit | |
| hitsPerTLBLevel | ComputeUnit | |
| init() | ComputeUnit | virtual |
| initiateFetch(Wavefront *wavefront) | ComputeUnit | |
| initState() | SimObject | virtual |
| injectGlobalMemFence(GPUDynInstPtr gpuDynInst, bool kernelLaunch=true, RequestPtr req=nullptr) | ComputeUnit | |
| instCyclesSALU | ComputeUnit | |
| instCyclesVALU | ComputeUnit | |
| ipc | ComputeUnit | |
| isDone() const | ComputeUnit | |
| isGlbMem(int unitId) | ComputeUnit | inline |
| isShrMem(int unitId) | ComputeUnit | inline |
| isSimdDone(uint32_t) const | ComputeUnit | |
| issuePeriod | ComputeUnit | |
| isVecAlu(int unitId) | ComputeUnit | inline |
| kernelLaunchInst | ComputeUnit | private |
| lastExecCycle | ComputeUnit | |
| lastVaddrCU | ComputeUnit | |
| lastVaddrSimd | ComputeUnit | |
| lastVaddrWF | ComputeUnit | |
| lds | ComputeUnit | protected |
| ldsBankAccesses | ComputeUnit | |
| ldsBankConflictDist | ComputeUnit | |
| ldsNoFlatInsts | ComputeUnit | |
| ldsNoFlatInstsPerWF | ComputeUnit | |
| ldsPort | ComputeUnit | |
| loadBusLength() | ComputeUnit | inline |
| loadState(CheckpointIn &cp) | SimObject | virtual |
| localMemBarrier | ComputeUnit | |
| localMemoryPipe | ComputeUnit | |
| locMemToVrfBus | ComputeUnit | |
| masterId() | ComputeUnit | inline |
| memInvalidate() | SimObject | inlinevirtual |
| MemObject(const Params *params) | MemObject | |
| memPort | ComputeUnit | |
| memWriteback() | SimObject | inlinevirtual |
| name() const | SimObject | inlinevirtual |
| nextCycle() const | Clocked | inline |
| nextGlbMemBus | ComputeUnit | |
| nextGlbRdBus() | ComputeUnit | inline |
| nextLocMemBus | ComputeUnit | |
| nextLocRdBus() | ComputeUnit | inline |
| notifyFork() | Drainable | inlinevirtual |
| numALUInstsExecuted | ComputeUnit | |
| numCASOps | ComputeUnit | |
| numCyclesPerLoadTransfer | ComputeUnit | |
| numCyclesPerStoreTransfer | ComputeUnit | |
| numFailedCASOps | ComputeUnit | |
| numGlbMemUnits | ComputeUnit | |
| numInstrExecuted | ComputeUnit | |
| numLocMemUnits | ComputeUnit | |
| numPwrStateTransitions | ClockedObject | protected |
| numSIMDs | ComputeUnit | |
| numTimesWgBlockedDueVgprAlloc | ComputeUnit | |
| numVecOpsExecuted | ComputeUnit | |
| numVecRegsPerSimd | ComputeUnit | |
| operator=(Clocked &)=delete | Clocked | protected |
| pageAccesses | ComputeUnit | |
| pageDataStruct typedef | ComputeUnit | |
| pageDivergenceDist | ComputeUnit | |
| pagesTouched | ComputeUnit | |
| Params typedef | ComputeUnit | |
| params() const | MemObject | inline |
| perLaneTLB | ComputeUnit | |
| prefetchDepth | ComputeUnit | |
| prefetchStride | ComputeUnit | |
| prefetchType | ComputeUnit | |
| processFetchReturn(PacketPtr pkt) | ComputeUnit | |
| processTimingPacket(PacketPtr pkt) | ComputeUnit | |
| prvEvalTick | ClockedObject | protected |
| pwrState() const | ClockedObject | inline |
| pwrState(Enums::PwrState) | ClockedObject | |
| pwrStateClkGateDist | ClockedObject | protected |
| pwrStateName() const | ClockedObject | inline |
| pwrStateResidencyTicks | ClockedObject | protected |
| pwrStateWeights() const | ClockedObject | |
| readyList | ComputeUnit | |
| ReadyWorkgroup(NDRange *ndr) | ComputeUnit | |
| regIdxVec | ComputeUnit | |
| registerEvent(uint32_t simdId, uint32_t regIdx, uint32_t operandSize, uint64_t when, uint8_t newStatus) | ComputeUnit | inline |
| regProbeListeners() | SimObject | virtual |
| regProbePoints() | SimObject | virtual |
| regStats() | ComputeUnit | virtual |
| req_tick_latency | ComputeUnit | |
| reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
| resetClock() const | Clocked | inlineprotected |
| resetStats() | SimObject | virtual |
| resizeRegFiles(int num_cregs, int num_sregs, int num_dregs) | ComputeUnit | |
| resp_tick_latency | ComputeUnit | |
| rrNextALUWp | ComputeUnit | |
| rrNextMemID | ComputeUnit | |
| sALUInsts | ComputeUnit | |
| sALUInstsPerWF | ComputeUnit | |
| scalarMemReads | ComputeUnit | |
| scalarMemReadsPerWF | ComputeUnit | |
| scalarMemWrites | ComputeUnit | |
| scalarMemWritesPerWF | ComputeUnit | |
| schedule(Event &event, Tick when) | EventManager | inline |
| schedule(Event *event, Tick when) | EventManager | inline |
| scheduleStage | ComputeUnit | |
| scoreboardCheckStage | ComputeUnit | |
| sendRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt) | ComputeUnit | |
| sendSyncRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt) | ComputeUnit | |
| sendToLds(GPUDynInstPtr gpuDynInst) __attribute__((warn_unused_result)) | ComputeUnit | |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | ClockedObject | virtual |
| serializeAll(CheckpointOut &cp) | SimObject | static |
| Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| setCurTick(Tick newVal) | EventManager | inline |
| shader | ComputeUnit | |
| shrMemInstAvail | ComputeUnit | |
| ShrMemUnitId() | ComputeUnit | inline |
| signalDrainDone() const | Drainable | inlineprotected |
| SimObject(const Params *_params) | SimObject | |
| spBypassLength() | ComputeUnit | inline |
| spBypassPipeLength | ComputeUnit | |
| sqcPort | ComputeUnit | |
| sqcTLBPort | ComputeUnit | |
| startup() | SimObject | virtual |
| startWavefront(Wavefront *w, int waveId, LdsChunk *ldsChunk, NDRange *ndr) | ComputeUnit | |
| StartWorkgroup(NDRange *ndr) | ComputeUnit | |
| statusVec | ComputeUnit | |
| storeBusLength() | ComputeUnit | inline |
| threadCyclesVALU | ComputeUnit | |
| ticksToCycles(Tick t) const | Clocked | inline |
| timestampVec | ComputeUnit | |
| tlbCycles | ComputeUnit | |
| tlbLatency | ComputeUnit | |
| tlbPort | ComputeUnit | |
| tlbRequests | ComputeUnit | |
| totalCycles | ComputeUnit | |
| unserialize(CheckpointIn &cp) override | ClockedObject | virtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| updateClockPeriod() const | Clocked | inline |
| updateEvents() | ComputeUnit | |
| updateInstStats(GPUDynInstPtr gpuDynInst) | ComputeUnit | |
| updatePageDivergenceDist(Addr addr) | ComputeUnit | |
| vALUInsts | ComputeUnit | |
| vALUInstsPerWF | ComputeUnit | |
| vALUUtilization | ComputeUnit | |
| vectorAluInstAvail | ComputeUnit | |
| vectorMemReads | ComputeUnit | |
| vectorMemReadsPerWF | ComputeUnit | |
| vectorMemWrites | ComputeUnit | |
| vectorMemWritesPerWF | ComputeUnit | |
| vectorRegsReserved | ComputeUnit | |
| voltage() const | Clocked | inline |
| vpc | ComputeUnit | |
| vrf | ComputeUnit | |
| vrfToCoalescerBusWidth | ComputeUnit | |
| vrfToGlobalMemPipeBus | ComputeUnit | |
| vrfToLocalMemPipeBus | ComputeUnit | |
| wakeupEventQueue(Tick when=(Tick)-1) | EventManager | inline |
| wavefrontSize | ComputeUnit | private |
| waveStatusList | ComputeUnit | |
| wfList | ComputeUnit | |
| wfSize() const | ComputeUnit | inline |
| wfWait | ComputeUnit | |
| wgBlockedDueLdsAllocation | ComputeUnit | |
| xact_cas_mode | ComputeUnit | |
| xactCasLoadMap | ComputeUnit | |
| ~Clocked() | Clocked | inlineprotectedvirtual |
| ~ComputeUnit() | ComputeUnit | |
| ~Drainable() | Drainable | protectedvirtual |
| ~Serializable() | Serializable | virtual |
| ~SimObject() | SimObject | virtual |
