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execute.hh
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37  * Authors: Andrew Bardsley
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39 
47 #ifndef __CPU_MINOR_EXECUTE_HH__
48 #define __CPU_MINOR_EXECUTE_HH__
49 
50 #include "cpu/minor/buffers.hh"
51 #include "cpu/minor/cpu.hh"
52 #include "cpu/minor/func_unit.hh"
53 #include "cpu/minor/lsq.hh"
54 #include "cpu/minor/pipe_data.hh"
55 #include "cpu/minor/scoreboard.hh"
56 
57 namespace Minor
58 {
59 
62 class Execute : public Named
63 {
64  protected:
67 
70 
73 
75  unsigned int issueLimit;
76 
78  unsigned int memoryIssueLimit;
79 
81  unsigned int commitLimit;
82 
84  unsigned int memoryCommitLimit;
85 
90 
93 
95  unsigned int numFuncUnits;
96 
100 
103 
106 
110 
113  unsigned int noCostFUIndex;
114 
117 
120 
123 
124  public: /* Public for Pipeline to be able to pass it to Decode */
126 
127  protected:
139  {
140  NotDraining, /* Not draining, possibly running */
141  DrainCurrentInst, /* Draining to end of inst/macroop */
142  DrainHaltFetch, /* Halting Fetch after completing current inst */
143  DrainAllInsts /* Discarding all remaining insts */
144  };
145 
148  ExecuteThreadInfo(unsigned int insts_committed) :
149  inputIndex(0),
151  instsBeingCommitted(insts_committed),
152  streamSeqNum(InstId::firstStreamSeqNum),
153  lastPredictionSeqNum(InstId::firstPredictionSeqNum),
155  { }
156 
158  inputIndex(other.inputIndex),
161  streamSeqNum(other.streamSeqNum),
163  drainState(other.drainState)
164  { }
165 
168 
171 
174  unsigned int inputIndex;
175 
179 
183 
189 
195 
198  };
199 
201 
205 
206  protected:
207  friend std::ostream &operator <<(std::ostream &os, DrainState state);
208 
211  const ForwardInstData *getInput(ThreadID tid);
212 
214  void popInput(ThreadID tid);
215 
219  void tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch);
220 
224  MinorDynInstPtr inst, const TheISA::PCState &target,
225  BranchData &branch);
226 
233  LSQ::LSQRequestPtr response, BranchData &branch,
234  Fault &fault);
235 
247  bool executeMemRefInst(MinorDynInstPtr inst, BranchData &branch,
248  bool &failed_predicate, Fault &fault);
249 
251  bool isInterrupted(ThreadID thread_id) const;
252 
254  bool isInbetweenInsts(ThreadID thread_id) const;
255 
258  bool takeInterrupt(ThreadID thread_id, BranchData &branch);
259 
261  unsigned int issue(ThreadID thread_id);
262 
265  bool tryPCEvents(ThreadID thread_id);
266 
270 
274  ThreadID checkInterrupts(BranchData& branch, bool& interrupted);
275 
278  bool hasInterrupt(ThreadID thread_id);
279 
294  bool commitInst(MinorDynInstPtr inst, bool early_memory_issue,
295  BranchData &branch, Fault &fault, bool &committed,
296  bool &completed_mem_issue);
297 
305  void commit(ThreadID thread_id, bool only_commit_microops, bool discard,
306  BranchData &branch);
307 
309  void setDrainState(ThreadID thread_id, DrainState state);
310 
315 
316  public:
317  Execute(const std::string &name_,
318  MinorCPU &cpu_,
319  MinorCPUParams &params,
322 
323  ~Execute();
324 
325  public:
326 
329 
331  LSQ &getLSQ() { return lsq; }
332 
336 
339  bool instIsHeadInst(MinorDynInstPtr inst);
340 
342  void evaluate();
343 
344  void minorTrace() const;
345 
348  bool isDrained();
349 
351  unsigned int drain();
352  void drainResume();
353 };
354 
355 }
356 
357 #endif /* __CPU_MINOR_EXECUTE_HH__ */
DrainState
Stage cycle-by-cycle state.
Definition: execute.hh:138
void handleMemResponse(MinorDynInstPtr inst, LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault)
Handle extracting mem ref responses from the memory queues and completing the associated instructions...
Definition: execute.cc:320
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
Definition: execute.cc:207
ExecuteThreadInfo(unsigned int insts_committed)
Constructor.
Definition: execute.hh:148
void commit(ThreadID thread_id, bool only_commit_microops, bool discard, BranchData &branch)
Try and commit instructions from the ends of the functional unit pipelines.
Definition: execute.cc:1003
Execute stage.
Definition: execute.hh:62
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
Top level definition of the Minor in-order CPU model.
Contains class definitions for data flowing between pipeline stages in the top-level structure portio...
bool allowEarlyMemIssue
Allow mem refs to leave their FUs before reaching the head of the in flight insts queue if their depe...
Definition: execute.hh:109
Execute function unit descriptions and pipeline implementations.
bool isInbetweenInsts(ThreadID thread_id) const
Are we between instructions? Can we be interrupted?
Definition: execute.cc:1386
unsigned int memoryCommitLimit
Number of memory instructions that can be committed per cycle.
Definition: execute.hh:84
void doInstCommitAccounting(MinorDynInstPtr inst)
Do the stats handling and instruction count and PC event events related to the new instruction/op cou...
Definition: execute.cc:837
ThreadID issuePriority
Definition: execute.hh:203
bool instIsHeadInst(MinorDynInstPtr inst)
Returns true if the given instruction is at the head of the inFlightInsts instruction queue...
Definition: execute.cc:1850
MinorCPU & cpu
Pointer back to the containing CPU.
Definition: execute.hh:72
A collection of MinorFUs.
Definition: func_unit.hh:181
void setDrainState(ThreadID thread_id, DrainState state)
Set the drain state (with useful debugging messages)
Definition: execute.cc:1789
ExecuteThreadInfo(const ExecuteThreadInfo &other)
Definition: execute.hh:157
bool setTraceTimeOnCommit
Modify instruction trace times on commit.
Definition: execute.hh:102
unsigned int memoryIssueLimit
Number of memory ops that can be issued per cycle.
Definition: execute.hh:78
void tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch)
Generate Branch data based (into branch) on an observed (or not) change in PC while executing an inst...
Definition: execute.cc:216
LSQ & getLSQ()
To allow ExecContext to find the LSQ.
Definition: execute.hh:331
unsigned int issue(ThreadID thread_id)
Try and issue instructions from the inputBuffer.
Definition: execute.cc:523
unsigned int commitLimit
Number of instructions that can be committed per cycle.
Definition: execute.hh:81
ThreadID getCommittingThread()
Use the current threading policy to determine the next thread to decode from.
Definition: execute.cc:1658
Id for lines and instructions.
Definition: dyn_inst.hh:70
Queue< QueuedInst, ReportTraitsAdaptor< QueuedInst > > * inFlightInsts
In-order instructions either in FUs or the LSQ.
Definition: execute.hh:167
std::vector< FUPipeline * > funcUnits
The execution functional units.
Definition: execute.hh:122
Wrapper for a queue type to act as a pipeline stage input queue.
Definition: buffers.hh:393
unsigned int numFuncUnits
Number of functional units to produce.
Definition: execute.hh:95
Bitfield< 17 > os
Definition: misc.hh:804
STL vector class.
Definition: stl.hh:40
InstSeqNum lastPredictionSeqNum
A prediction number for use where one isn't available from an instruction.
Definition: execute.hh:194
Derived SenderState to carry data access info.
Definition: lsq.hh:120
InstSeqNum streamSeqNum
Source of sequence number for instuction streams.
Definition: execute.hh:188
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
Definition: cpu.hh:100
Execute(const std::string &name_, MinorCPU &cpu_, MinorCPUParams &params, Latch< ForwardInstData >::Output inp_, Latch< BranchData >::Input out_)
Definition: execute.cc:62
Definition: trace.hh:140
ForwardInstData instsBeingCommitted
Structure for reporting insts currently being processed/retired for MinorTrace.
Definition: execute.hh:182
void drainResume()
Definition: execute.cc:1753
ThreadID getIssuingThread()
Definition: execute.cc:1725
bool takeInterrupt(ThreadID thread_id, BranchData &branch)
Act on an interrupt.
Definition: execute.cc:414
unsigned int noCostFUIndex
The FU index of the non-existent costless FU for instructions which pass the MinorDynInst::isNoCostIn...
Definition: execute.hh:113
std::vector< InputBuffer< ForwardInstData > > inputBuffer
Definition: execute.hh:125
Cycles longestFuLatency
Longest latency of any FU, useful for setting up the activity recoder.
Definition: execute.hh:99
bool tryPCEvents(ThreadID thread_id)
Try to act on PC-related events.
Definition: execute.cc:815
A simple instruction scoreboard for tracking dependencies in Execute.
uint64_t InstSeqNum
Definition: inst_seq.hh:40
unsigned int inputIndex
Index that we've completed upto in getInput data.
Definition: execute.hh:174
Classes for buffer, queue and FIFO behaviour.
Latch< BranchData >::Input out
Input port carrying stream changes to Fetch1.
Definition: execute.hh:69
ThreadID commitPriority
Definition: execute.hh:204
MinorFUPool & fuDescriptions
Descriptions of the functional units we want to generate.
Definition: execute.hh:92
LSQ lsq
Dcache port to pass on to the CPU.
Definition: execute.hh:116
bool hasInterrupt(ThreadID thread_id)
Checks if a specific thread has an interrupt.
Definition: execute.cc:1614
A load/store queue that allows outstanding reads and writes.
bool processMoreThanOneInput
If true, more than one input line can be processed each cycle if there is room to execute more instru...
Definition: execute.hh:89
ThreadID checkInterrupts(BranchData &branch, bool &interrupted)
Check all threads for possible interrupts.
Definition: execute.cc:1579
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:171
DrainState drainState
State progression for draining NotDraining -> ...
Definition: execute.hh:197
Forward data betwen Execute and Fetch1 carrying change-of-address/stream information.
Definition: pipe_data.hh:64
ThreadID interruptPriority
Definition: execute.hh:202
bool lastCommitWasEndOfMacroop
The last commit was the end of a full instruction so an interrupt can safely happen.
Definition: execute.hh:178
bool instIsRightStream(MinorDynInstPtr inst)
Does the given instruction have the right stream sequence number to be committed? ...
Definition: execute.cc:1844
GenericISA::SimplePCState< MachInst > PCState
Definition: types.hh:43
bool executeMemRefInst(MinorDynInstPtr inst, BranchData &branch, bool &failed_predicate, Fault &fault)
Execute a memory reference instruction.
Definition: execute.cc:444
bool commitInst(MinorDynInstPtr inst, bool early_memory_issue, BranchData &branch, Fault &fault, bool &committed, bool &completed_mem_issue)
Commit a single instruction.
Definition: execute.cc:870
std::vector< ExecuteThreadInfo > executeInfo
Definition: execute.hh:200
std::vector< Scoreboard > scoreboard
Scoreboard of instruction dependencies.
Definition: execute.hh:119
void minorTrace() const
Definition: execute.cc:1625
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:79
bool isDrained()
After thread suspension, has Execute been drained of in-flight instructions and memory accesses...
Definition: execute.cc:1818
Encapsulate wires on either input or output of the latch.
Definition: buffers.hh:243
Latch< ForwardInstData >::Output inp
Input port carrying instructions from Decode.
Definition: execute.hh:66
void evaluate()
Pass on input/buffer data to the output if you can.
Definition: execute.cc:1393
unsigned int drain()
Like the drain interface on SimObject.
Definition: execute.cc:1796
std::shared_ptr< FaultBase > Fault
Definition: types.hh:184
MinorCPU::MinorCPUPort & getDcachePort()
Returns the DcachePort owned by this Execute to pass upwards.
Definition: execute.cc:1861
friend std::ostream & operator<<(std::ostream &os, DrainState state)
Definition: execute.cc:1764
unsigned int issueLimit
Number of instructions that can be issued per cycle.
Definition: execute.hh:75
bool setTraceTimeOnIssue
Modify instruction trace times on issue.
Definition: execute.hh:105
Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appro...
Definition: pipe_data.hh:255
Queue< QueuedInst, ReportTraitsAdaptor< QueuedInst > > * inFUMemInsts
Memory ref instructions still in the FUs.
Definition: execute.hh:170
const ForwardInstData * getInput(ThreadID tid)
Get a piece of data to work on from the inputBuffer, or 0 if there is no data.
Definition: execute.cc:194
void updateBranchData(ThreadID tid, BranchData::Reason reason, MinorDynInstPtr inst, const TheISA::PCState &target, BranchData &branch)
Actually create a branch to communicate to Fetch1/Fetch2 and, if that is a stream-changing branch upd...
Definition: execute.cc:294
bool isInterrupted(ThreadID thread_id) const
Has an interrupt been raised.
Definition: execute.cc:408

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