47 #ifndef __CPU_MINOR_EXECUTE_HH__
48 #define __CPU_MINOR_EXECUTE_HH__
248 bool &failed_predicate,
Fault &fault);
296 bool &completed_mem_issue);
305 void commit(
ThreadID thread_id,
bool only_commit_microops,
bool discard,
317 Execute(
const std::string &name_,
319 MinorCPUParams ¶ms,
351 unsigned int drain();
DrainState
Stage cycle-by-cycle state.
void handleMemResponse(MinorDynInstPtr inst, LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault)
Handle extracting mem ref responses from the memory queues and completing the associated instructions...
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
ExecuteThreadInfo(unsigned int insts_committed)
Constructor.
void commit(ThreadID thread_id, bool only_commit_microops, bool discard, BranchData &branch)
Try and commit instructions from the ends of the functional unit pipelines.
Cycles is a wrapper class for representing cycle counts, i.e.
Top level definition of the Minor in-order CPU model.
Contains class definitions for data flowing between pipeline stages in the top-level structure portio...
bool allowEarlyMemIssue
Allow mem refs to leave their FUs before reaching the head of the in flight insts queue if their depe...
Execute function unit descriptions and pipeline implementations.
bool isInbetweenInsts(ThreadID thread_id) const
Are we between instructions? Can we be interrupted?
unsigned int memoryCommitLimit
Number of memory instructions that can be committed per cycle.
void doInstCommitAccounting(MinorDynInstPtr inst)
Do the stats handling and instruction count and PC event events related to the new instruction/op cou...
bool instIsHeadInst(MinorDynInstPtr inst)
Returns true if the given instruction is at the head of the inFlightInsts instruction queue...
MinorCPU & cpu
Pointer back to the containing CPU.
A collection of MinorFUs.
void setDrainState(ThreadID thread_id, DrainState state)
Set the drain state (with useful debugging messages)
ExecuteThreadInfo(const ExecuteThreadInfo &other)
bool setTraceTimeOnCommit
Modify instruction trace times on commit.
unsigned int memoryIssueLimit
Number of memory ops that can be issued per cycle.
void tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch)
Generate Branch data based (into branch) on an observed (or not) change in PC while executing an inst...
LSQ & getLSQ()
To allow ExecContext to find the LSQ.
unsigned int issue(ThreadID thread_id)
Try and issue instructions from the inputBuffer.
unsigned int commitLimit
Number of instructions that can be committed per cycle.
ThreadID getCommittingThread()
Use the current threading policy to determine the next thread to decode from.
Id for lines and instructions.
Queue< QueuedInst, ReportTraitsAdaptor< QueuedInst > > * inFlightInsts
In-order instructions either in FUs or the LSQ.
std::vector< FUPipeline * > funcUnits
The execution functional units.
Wrapper for a queue type to act as a pipeline stage input queue.
unsigned int numFuncUnits
Number of functional units to produce.
InstSeqNum lastPredictionSeqNum
A prediction number for use where one isn't available from an instruction.
Derived SenderState to carry data access info.
InstSeqNum streamSeqNum
Source of sequence number for instuction streams.
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
Execute(const std::string &name_, MinorCPU &cpu_, MinorCPUParams ¶ms, Latch< ForwardInstData >::Output inp_, Latch< BranchData >::Input out_)
ForwardInstData instsBeingCommitted
Structure for reporting insts currently being processed/retired for MinorTrace.
ThreadID getIssuingThread()
bool takeInterrupt(ThreadID thread_id, BranchData &branch)
Act on an interrupt.
unsigned int noCostFUIndex
The FU index of the non-existent costless FU for instructions which pass the MinorDynInst::isNoCostIn...
std::vector< InputBuffer< ForwardInstData > > inputBuffer
Cycles longestFuLatency
Longest latency of any FU, useful for setting up the activity recoder.
bool tryPCEvents(ThreadID thread_id)
Try to act on PC-related events.
A simple instruction scoreboard for tracking dependencies in Execute.
unsigned int inputIndex
Index that we've completed upto in getInput data.
Classes for buffer, queue and FIFO behaviour.
Latch< BranchData >::Input out
Input port carrying stream changes to Fetch1.
MinorFUPool & fuDescriptions
Descriptions of the functional units we want to generate.
LSQ lsq
Dcache port to pass on to the CPU.
bool hasInterrupt(ThreadID thread_id)
Checks if a specific thread has an interrupt.
A load/store queue that allows outstanding reads and writes.
bool processMoreThanOneInput
If true, more than one input line can be processed each cycle if there is room to execute more instru...
ThreadID checkInterrupts(BranchData &branch, bool &interrupted)
Check all threads for possible interrupts.
int16_t ThreadID
Thread index/ID type.
DrainState drainState
State progression for draining NotDraining -> ...
Forward data betwen Execute and Fetch1 carrying change-of-address/stream information.
ThreadID interruptPriority
bool lastCommitWasEndOfMacroop
The last commit was the end of a full instruction so an interrupt can safely happen.
bool instIsRightStream(MinorDynInstPtr inst)
Does the given instruction have the right stream sequence number to be committed? ...
GenericISA::SimplePCState< MachInst > PCState
bool executeMemRefInst(MinorDynInstPtr inst, BranchData &branch, bool &failed_predicate, Fault &fault)
Execute a memory reference instruction.
bool commitInst(MinorDynInstPtr inst, bool early_memory_issue, BranchData &branch, Fault &fault, bool &committed, bool &completed_mem_issue)
Commit a single instruction.
std::vector< ExecuteThreadInfo > executeInfo
std::vector< Scoreboard > scoreboard
Scoreboard of instruction dependencies.
MinorCPU is an in-order CPU model with four fixed pipeline stages:
bool isDrained()
After thread suspension, has Execute been drained of in-flight instructions and memory accesses...
Latch< ForwardInstData >::Output inp
Input port carrying instructions from Decode.
void evaluate()
Pass on input/buffer data to the output if you can.
unsigned int drain()
Like the drain interface on SimObject.
std::shared_ptr< FaultBase > Fault
MinorCPU::MinorCPUPort & getDcachePort()
Returns the DcachePort owned by this Execute to pass upwards.
friend std::ostream & operator<<(std::ostream &os, DrainState state)
unsigned int issueLimit
Number of instructions that can be issued per cycle.
bool setTraceTimeOnIssue
Modify instruction trace times on issue.
Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appro...
Queue< QueuedInst, ReportTraitsAdaptor< QueuedInst > > * inFUMemInsts
Memory ref instructions still in the FUs.
const ForwardInstData * getInput(ThreadID tid)
Get a piece of data to work on from the inputBuffer, or 0 if there is no data.
void updateBranchData(ThreadID tid, BranchData::Reason reason, MinorDynInstPtr inst, const TheISA::PCState &target, BranchData &branch)
Actually create a branch to communicate to Fetch1/Fetch2 and, if that is a stream-changing branch upd...
bool isInterrupted(ThreadID thread_id) const
Has an interrupt been raised.