gem5
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A load/store queue that allows outstanding reads and writes. More...
#include "cpu/minor/buffers.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/pipe_data.hh"
#include "cpu/minor/trace.hh"
Go to the source code of this file.
Classes | |
class | Minor::LSQ |
class | Minor::LSQ::DcachePort |
Exposable data port. More... | |
class | Minor::LSQ::LSQRequest |
Derived SenderState to carry data access info. More... | |
class | Minor::LSQ::SpecialDataRequest |
Special request types that don't actually issue memory requests. More... | |
class | Minor::LSQ::FailedDataRequest |
FailedDataRequest represents requests from instructions that failed their predicates but need to ride the requests/transfers queues to maintain trace ordering. More... | |
class | Minor::LSQ::BarrierDataRequest |
Request for doing barrier accounting in the store buffer. More... | |
class | Minor::LSQ::SingleDataRequest |
SingleDataRequest is used for requests that don't fragment. More... | |
class | Minor::LSQ::SplitDataRequest |
class | Minor::LSQ::SplitDataRequest::TranslationEvent |
Event to step between translations. More... | |
class | Minor::LSQ::StoreBuffer |
Store buffer. More... | |
Namespaces | |
Minor | |
Minor contains all the definitions within the MinorCPU apart from the CPU class itself. | |
Functions | |
PacketPtr | Minor::makePacketForRequest (Request &request, bool isLoad, Packet::SenderState *sender_state=NULL, PacketDataPtr data=NULL) |
Make a suitable packet for the given request. More... | |
A load/store queue that allows outstanding reads and writes.
Definition in file lsq.hh.