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write_queue_entry.cc
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1 /*
2  * Copyright (c) 2012-2013, 2015-2016 ARM Limited
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14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
15  * Copyright (c) 2010 Advanced Micro Devices, Inc.
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40  *
41  * Authors: Erik Hallnor
42  * Dave Greene
43  * Andreas Hansson
44  */
45 
52 
53 #include <algorithm>
54 #include <cassert>
55 #include <string>
56 #include <vector>
57 
58 #include "base/misc.hh"
59 #include "base/types.hh"
60 #include "debug/Cache.hh"
61 #include "mem/cache/cache.hh"
62 #include "sim/core.hh"
63 
64 using namespace std;
65 
66 inline void
68  Counter order)
69 {
70  emplace_back(pkt, readyTime, order);
71 }
72 
73 bool
75 {
76  for (auto& t : *this) {
77  if (pkt->checkFunctional(t.pkt)) {
78  return true;
79  }
80  }
81 
82  return false;
83 }
84 
85 void
86 WriteQueueEntry::TargetList::print(std::ostream &os, int verbosity,
87  const std::string &prefix) const
88 {
89  for (auto& t : *this) {
90  ccprintf(os, "%sFromCPU: ", prefix);
91  t.pkt->print(os, verbosity, "");
92  }
93 }
94 
95 void
96 WriteQueueEntry::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
97  Tick when_ready, Counter _order)
98 {
99  blkAddr = blk_addr;
100  blkSize = blk_size;
101  isSecure = target->isSecure();
102  readyTime = when_ready;
103  order = _order;
104  assert(target);
105  _isUncacheable = target->req->isUncacheable();
106  inService = false;
107 
108  // we should never have more than a single target for cacheable
109  // writes (writebacks and clean evictions)
110  panic_if(!_isUncacheable && !targets.empty(),
111  "Write queue entry %#llx should never have more than one "
112  "cacheable target", blkAddr);
113  panic_if(!((target->isWrite() && _isUncacheable) ||
114  (target->isEviction() && !_isUncacheable)),
115  "Write queue entry %#llx should either be uncacheable write or "
116  "a cacheable eviction");
117 
118  targets.add(target, when_ready, _order);
119 }
120 
121 void
123 {
124  assert(targets.empty());
125  inService = false;
126 }
127 
128 bool
130 {
131  // For printing, we treat the WriteQueueEntry as a whole as single
132  // entity. For other requests, we iterate over the individual
133  // targets since that's where the actual data lies.
134  if (pkt->isPrint()) {
135  pkt->checkFunctional(this, blkAddr, isSecure, blkSize, nullptr);
136  return false;
137  } else {
138  return targets.checkFunctional(pkt);
139  }
140 }
141 
142 bool
144 {
145  return cache.sendWriteQueuePacket(this);
146 }
147 
148 void
149 WriteQueueEntry::print(std::ostream &os, int verbosity,
150  const std::string &prefix) const
151 {
152  ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
153  prefix, blkAddr, blkAddr + blkSize - 1,
154  isSecure ? "s" : "ns",
155  _isUncacheable ? "Unc" : "",
156  inService ? "InSvc" : "");
157 
158  ccprintf(os, "%s Targets:\n", prefix);
159  targets.print(os, verbosity, prefix + " ");
160 }
161 
162 std::string
164 {
165  ostringstream str;
166  print(str);
167  return str.str();
168 }
bool isSecure() const
Definition: packet.hh:661
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
bool isUncacheable() const
Accessor functions for flags.
Definition: request.hh:767
void print(std::ostream &os, int verbosity, const std::string &prefix) const
bool isPrint() const
Definition: packet.hh:529
Write queue entry.
bool isWrite() const
Definition: packet.hh:503
panic_if(!root,"Invalid expression\n")
bool sendPacket(Cache &cache)
Send this queue entry as a downstream packet, with the exact behaviour depending on the specific entr...
std::string print() const
A no-args wrapper of print(std::ostream...) meant to be invoked from DPRINTFs avoiding string overhea...
Bitfield< 17 > os
Definition: misc.hh:804
void deallocate()
Mark this entry as free.
A template-policy based cache.
Definition: cache.hh:74
bool checkFunctional(PacketPtr pkt)
uint64_t Tick
Tick count type.
Definition: types.hh:63
bool sendWriteQueuePacket(WriteQueueEntry *wq_entry)
Similar to sendMSHR, but for a write-queue entry instead.
Definition: cache.cc:2471
const RequestPtr req
A pointer to the original request.
Definition: packet.hh:304
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
bool checkFunctional(PacketPtr pkt)
int64_t Counter
Statistics counter type.
Definition: types.hh:58
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:245
bool checkFunctional(PacketPtr other)
Check a functional request against a memory value stored in another packet (i.e.
Definition: packet.hh:1115
bool isEviction() const
Definition: packet.hh:518
Bitfield< 5 > t
Definition: miscregs.hh:1382
Describes a cache based on template policies.
void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, Tick when_ready, Counter _order)
Allocate a miss to this entry.
void add(PacketPtr pkt, Tick readyTime, Counter order)

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