|
gem5
|
Describes a cache based on template policies. More...
#include <unordered_set>#include "base/misc.hh"#include "enums/Clusivity.hh"#include "mem/cache/base.hh"#include "mem/cache/blk.hh"#include "mem/cache/mshr.hh"#include "mem/cache/tags/base.hh"#include "params/Cache.hh"#include "sim/eventq.hh"Go to the source code of this file.
Classes | |
| class | Cache |
| A template-policy based cache. More... | |
| class | Cache::CpuSidePort |
| The CPU-side port extends the base cache slave port with access functions for functional, atomic and timing requests. More... | |
| class | Cache::CacheReqPacketQueue |
| Override the default behaviour of sendDeferredPacket to enable the memory-side cache port to also send requests based on the current MSHR status. More... | |
| class | Cache::MemSidePort |
| The memory-side port extends the base cache master port with access functions for functional, atomic and timing snoops. More... | |
| class | CacheBlkVisitorWrapper |
| Wrap a method and present it as a cache block visitor. More... | |
| class | CacheBlkIsDirtyVisitor |
| Cache block visitor that determines if there are dirty blocks in a cache. More... | |
Describes a cache based on template policies.
Definition in file cache.hh.