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Namespaces | |
| SimClock | |
| These are variables that are set based on the simulator frequency. | |
| SimClock::Float | |
| SimClock::Int | |
| These variables equal the number of ticks in the unit of time they're named after in a 64 bit integer. | |
Functions | |
| Tick | curTick () |
| The universal simulation clock. More... | |
| void | setClockFrequency (Tick ticksPerSecond) |
| void | setOutputDir (const std::string &dir) |
| void | registerExitCallback (Callback *callback) |
| Register an exit callback. More... | |
| void | doExitCleanup () |
| Do C++ simulator exit processing. More... | |
Variables | |
| const Tick | retryTime = 1000 |
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inline |
The universal simulation clock.
The current simulated tick.
Definition at line 47 of file core.hh.
References _curEventQueue, and EventQueue::getCurTick().
Referenced by DRAMSim2::accessAndRespond(), DRAMCtrl::accessAndRespond(), BaseSetAssoc::accessBlock(), FALRU::accessBlock(), FlashDevice::accessDevice(), FlashDevice::actionComplete(), O3ThreadContext< class >::activate(), SimpleThread::activate(), FullO3CPU< Impl >::activateContext(), ElasticTrace::addDepTraceRecord(), DRAMCtrl::addToReadQueue(), DRAMCtrl::addToWriteQueue(), CacheMemory::allocate(), DefaultFetch< Impl >::buildInst(), BaseXBar::calcPacketTiming(), DistIface::RecvScheduler::calcReceiveTick(), NetworkInterface::calculateVC(), VncInput::captureFrameBuffer(), Sinic::Device::changeConfig(), AlphaISA::Kernel::Statistics::changeMode(), TraceCPU::checkAndSchedExitEvent(), FlashDevice::checkDrain(), DRAMCtrl::Rank::checkDrainDone(), IGbE::chkInterrupt(), Cache::cleanEvictBlk(), BaseCache::CacheSlavePort::clearBlocked(), UFSHostDevice::clearInterrupt(), Intel8254Timer::Counter::CounterEvent::clocksLeft(), Minor::Execute::commit(), DefaultCommit< Impl >::commitHead(), MemTest::completeRequest(), LSQUnit< Impl >::completeStore(), ClockedObject::computeStats(), BaseSetAssoc::computeStats(), DRAMCtrl::Rank::computeStats(), Sinic::Base::cpuInterrupt(), NSGigE::cpuInterrupt(), Sinic::Base::cpuIntrPost(), NSGigE::cpuIntrPost(), IGbE::cpuPostInt(), Shader::curCycle(), X86ISA::GpuTLB::curCycle(), TLBCoalescer::curCycle(), TraceCPU::dcacheRetryRecvd(), DefaultDecode< Impl >::decodeInsts(), PacketQueue::deferredPacketReady(), MessageBuffer::dequeue(), SimpleMemory::dequeue(), Sinic::Device::devIntrChangeMask(), NSGigE::devIntrChangeMask(), Sinic::Device::devIntrPost(), NSGigE::devIntrPost(), Shader::dispatch_workgroups(), DefaultIEW< Impl >::dispatchInsts(), Pl111::dmaDone(), IdeDisk::doDmaDataRead(), IdeDisk::doDmaDataWrite(), IdeDisk::doDmaRead(), IdeDisk::doDmaTransfer(), IdeDisk::doDmaWrite(), DRAMCtrl::doDRAMAccess(), ArmISA::TableWalker::doL1DescriptorWrapper(), ArmISA::TableWalker::doL2DescriptorWrapper(), ArmISA::TableWalker::doLongDescriptorWrapper(), doSimLoop(), ThermalModel::doStep(), StoreTrace::downgrade(), DRAMCtrl::drain(), PCEventQueue::dump(), EventQueue::dump(), CheckerCPU::dumpAndExit(), EtherDump::dumpPacket(), PseudoInst::dumpresetstats(), PseudoInst::dumpstats(), LdsState::earliestReturnTime(), EtherSwitch::Interface::enqueue(), TraceGen::enter(), TrafficGen::enterState(), Event::Event(), Shader::exec(), TraceCPU::ElasticDataGen::execute(), exitSimLoop(), DefaultFetch< Impl >::fetch(), IGbE::DescCache< T >::fetchDescriptors(), IGbE::DescCache< T >::fetchDescriptors1(), ElasticTrace::fetchReqTrace(), UFSHostDevice::finalUTP(), FALRU::findVictim(), Minor::LSQ::SplitDataRequest::finish(), DefaultFetch< Impl >::finishTranslation(), ArmISA::flattenIntRegModeIndex(), DRAMCtrl::Rank::flushCmdList(), getElapsedTimeMicro(), getElapsedTimeNano(), Queue< WriteQueueEntry >::getNext(), Cache::getNextQueueEntry(), MipsISA::haltThread(), MipsISA::handleLockedWrite(), RiscvISA::handleLockedWrite(), Checker< Impl >::handlePendingInt(), MemTraceProbe::handleRequest(), DmaPort::handleResp(), MSHR::handleSnoop(), X86ISA::GpuTLB::handleTranslationReturn(), RubyPort::MemSlavePort::hitCallback(), RubyDirectedTester::hitCallback(), Sequencer::hitCallback(), TraceCPU::icacheRetryRecvd(), Check::initiateAction(), Check::initiateCheck(), Check::initiateFlush(), Check::initiatePrefetch(), QueuedPrefetcher::insert(), BaseSetAssoc::insertBlock(), GPUCoalescer::insertRequest(), BaseSetAssoc::invalidate(), Minor::Execute::issue(), Sequencer::issueRequest(), GPUCoalescer::issueRequest(), X86ISA::GpuTLB::issueTLBLookup(), EtherSwitch::Interface::learnSenderAddr(), GDBListener::listen(), EtherSwitch::Interface::lookupDestPort(), UFSHostDevice::LUNSignal(), PseudoInst::m5checkpoint(), PseudoInst::m5exit(), PseudoInst::m5fail(), VIPERCoalescer::makeRequest(), GPUCoalescer::makeRequest(), MemTest::MemTest(), RubySystem::memWriteback(), DRAMCtrl::minBankPrep(), TraceCPU::FixedRetryGen::nextExecute(), LinearGen::nextPacketTick(), RandomGen::nextPacketTick(), TraceGen::nextPacketTick(), GpuDispatcher::notifyWgCompl(), BaseXBar::Layer< SrcType, DstType >::occupyLayer(), Linux::openSpecialFile(), DistIface::packetOut(), ArmISA::TableWalker::pendingChange(), DVFSHandler::perfLevel(), Stats::periodicStatDump(), IGbE::RxDescCache::pktComplete(), IGbE::TxDescCache::pktComplete(), DistIface::RecvScheduler::popPacket(), IGbE::postInterrupt(), BaseSimpleCPU::preExecute(), Stats::AvgStor::prepare(), Stats::AvgSampleStor::prepare(), Logger::printEpilogue(), MC146818::RTCEvent::process(), GlobalSimLoopExitEvent::process(), Stats::SimTicksReset::process(), MC146818::RTCTickEvent::process(), Uart8250::IntrEvent::process(), Shader::TickEvent::process(), DumpStatsPCEvent::process(), TLBCoalescer::IssueProbeEvent::process(), Stats::StatEvent::process(), GlobalSyncEvent::process(), DistIface::SyncEvent::process(), DRAMCtrl::Rank::processActivateEvent(), DRAMCtrl::processNextReqEvent(), DRAMCtrl::Rank::processPowerEvent(), DRAMCtrl::Rank::processPrechargeEvent(), DRAMCtrl::Rank::processRefreshEvent(), DRAMCtrl::processRespondEvent(), EtherLink::Link::processTxQueue(), DRAMCtrl::Rank::processWakeUpEvent(), ArmISA::TableWalker::processWalk(), ArmISA::TableWalker::processWalkAArch64(), ArmISA::TableWalker::processWalkLPAE(), ArmISA::TableWalker::processWalkWrapper(), MSHR::promoteDeferredTargets(), MemChecker::ByteTracker::pruneTransactions(), EtherSwitch::Interface::PortFifo::push(), ClockedObject::pwrState(), ClockedObject::pwrStateWeights(), pybind_init_core(), PseudoInst::quiesceNs(), Sp804::Timer::read(), PL031::read(), CpuLocalTimer::Timer::read(), RealViewCtrl::read(), LSQUnit< Impl >::read(), UFSHostDevice::readCallback(), DRAMSim2::readComplete(), Pl111::readFramebuffer(), CheckerCPU::readMem(), X86ISA::Interrupts::readReg(), ElasticTrace::recordExecTick(), GPUCoalescer::recordMissLatency(), ElasticTrace::recordToCommTick(), Cache::recvAtomic(), TrafficGen::recvReqRetry(), TLBCoalescer::MemSidePort::recvReqRetry(), SimpleTimingPort::recvTimingReq(), StubSlavePort::recvTimingReq(), RubyPort::MemSlavePort::recvTimingReq(), TLBCoalescer::CpuSidePort::recvTimingReq(), SimpleMemory::recvTimingReq(), MemCheckerMonitor::recvTimingReq(), CommMonitor::recvTimingReq(), DRAMCtrl::recvTimingReq(), RubyPort::MemMasterPort::recvTimingResp(), RubyPort::PioMasterPort::recvTimingResp(), NoncoherentXBar::recvTimingResp(), MemCheckerMonitor::recvTimingResp(), CommMonitor::recvTimingResp(), CoherentXBar::recvTimingResp(), X86ISA::GpuTLB::MemSidePort::recvTimingResp(), Cache::recvTimingResp(), ComputeUnit::DataPort::recvTimingResp(), ComputeUnit::DTLBPort::recvTimingResp(), CoherentXBar::recvTimingSnoopResp(), ElasticTrace::regEtraceListeners(), ElasticTrace::regProbeListeners(), DRAMCtrl::reorderQueue(), Request::Request(), UFSHostDevice::requestHandler(), BankedArray::reserve(), Stats::AvgStor::reset(), Clocked::resetClock(), PseudoInst::resetstats(), Sp804::Timer::restartCounter(), CpuLocalTimer::Timer::restartTimerCounter(), CpuLocalTimer::Timer::restartWatchdogCounter(), MipsISA::restoreThread(), Stats::AvgStor::result(), BasePixelPump::PixelEvent::resume(), DistIface::RecvScheduler::resumeRecvTicks(), PL031::resyncMatch(), EtherTapBase::retransmit(), PseudoInst::rpns(), StatTest::run(), DistIface::SyncNode::run(), DistIface::SyncSwitch::run(), Sinic::Device::rxKick(), NSGigE::rxKick(), CommMonitor::samplePeriodic(), TraceCPU::schedIcacheNext(), schedRelBreak(), PacketQueue::schedSendEvent(), PacketQueue::schedSendTiming(), GpuDispatcher::scheduleDispatch(), MC146818::RTCEvent::scheduleIntr(), Uart8250::IntrEvent::scheduleIntr(), DRAMCtrl::Rank::schedulePowerEvent(), InstructionQueue< Impl >::scheduleReadyInsts(), DRAMCtrl::Rank::scheduleWakeUpEvent(), EtherBus::send(), X86ISA::IntDevice::IntMasterPort::sendMessage(), ComputeUnit::sendRequest(), DRAMSim2::sendResponse(), EtherTapBase::sendSimulated(), ComputeUnit::sendSyncRequest(), MC146818::serialize(), Intel8254Timer::Counter::serialize(), Sinic::Device::serialize(), NSGigE::serialize(), Globals::serialize(), Stats::AvgStor::set(), Request::setAccessLatency(), CheckpointIn::setDir(), SystemCounter::setFreq(), Pl011::setInterrupts(), CacheMemory::setMRU(), X86ISA::Interrupts::setReg(), Intel8254Timer::Counter::CounterEvent::setTo(), Request::setTranslateLatency(), Request::setVirt(), Event::setWhen(), simulate(), DefaultRename< Impl >::sortInsts(), DistIface::SyncEvent::start(), IdeDisk::startDma(), CommMonitor::startup(), BaseKvmCPU::startup(), RubySystem::startup(), MC146818::startup(), ThermalModel::startup(), Intel8254Timer::Counter::startup(), DRAMSim2::startup(), DRAMCtrl::Rank::startup(), DRAMCtrl::startup(), Stats::statElapsedTicks(), Stats::statFinalTick(), StoreTrace::store(), O3ThreadContext< class >::suspend(), SimpleThread::suspend(), BasePixelPump::PixelEvent::suspend(), Kernel::Statistics::swpipl(), takeCheckpoint(), CacheMemory::testCacheAccess(), GarnetSyntheticTraffic::tick(), AtomicSimpleCPU::tick(), IGbE::tick(), DRAMSim2::tick(), BaseKvmCPU::tick(), timesFunc(), Root::timeSync(), Root::timeSyncEnable(), Trace::InstPBTrace::traceInst(), X86ISA::GpuTLB::translationReturn(), EtherLink::Link::transmit(), DistEtherLink::TxLink::transmit(), EtherSwitch::Interface::transmit(), NSGigE::transmit(), BankedArray::tryAccess(), CacheMemory::tryCacheAccess(), SerialLink::SerialLinkSlavePort::trySendTiming(), Bridge::BridgeSlavePort::trySendTiming(), SerialLink::SerialLinkMasterPort::trySendTiming(), Bridge::BridgeMasterPort::trySendTiming(), EtherLink::Link::txDone(), Sinic::Device::txKick(), NSGigE::txKick(), Sinic::Device::unserialize(), NSGigE::unserialize(), Clocked::update(), TrafficGen::update(), ElasticTrace::updateCommitOrderDep(), ArchTimer::updateCounter(), Stats::updateEvents(), DefaultIEW< Impl >::updateExeInstStats(), VGic::updateIntState(), Pl390::updateIntState(), Pl050::updateIntStatus(), ElasticTrace::updateIssueOrderDep(), X86ISA::GpuTLB::updatePageFootprint(), TLBCoalescer::updatePhysAddresses(), CommMonitor::MonitorStats::updateReqStats(), Checker< Impl >::validateExecution(), Checker< Impl >::validateInst(), Checker< Impl >::validateState(), SystemCounter::value(), Checker< Impl >::verify(), HDLcd::virtRefresh(), RubyDirectedTester::wakeup(), GPUCoalescer::wakeup(), RubyTester::wakeup(), ArmISA::TableWalker::walk(), System::workItemBegin(), System::workItemEnd(), Uart8250::write(), AlphaBackdoor::write(), PL031::write(), EnergyCtrl::write(), GpuDispatcher::write(), UFSHostDevice::write(), IGbE::DescCache< T >::writeback(), IGbE::DescCache< T >::writeback1(), Cache::writebackBlk(), LSQUnit< Impl >::writebackStores(), DRAMSim2::writeComplete(), MC146818::writeData(), UFSHostDevice::writeDevice(), CheckerCPU::writeMem(), and MipsISA::yieldThread().
| void doExitCleanup | ( | ) |
Do C++ simulator exit processing.
Exported to Python to be invoked when simulator terminates via Python's atexit mechanism.
Definition at line 126 of file core.cc.
References CallbackQueue::clear(), exitCallbacks(), and CallbackQueue::process().
Referenced by pybind_init_core().
| void registerExitCallback | ( | Callback * | callback | ) |
| void setClockFrequency | ( | Tick | ticksPerSecond | ) |
Definition at line 73 of file core.cc.
References SimClock::Frequency, SimClock::Float::GHZ, SimClock::Float::Hz, SimClock::Float::kHz, SimClock::Float::MHz, SimClock::Int::ms, SimClock::Int::ns, SimClock::Int::ps, SimClock::Int::s, and SimClock::Int::us.
Referenced by pybind_init_core().
| void setOutputDir | ( | const std::string & | dir | ) |
| const Tick retryTime = 1000 |
Definition at line 49 of file core.hh.
Referenced by EtherTapBase::retransmit(), EtherTapBase::sendSimulated(), EtherSwitch::Interface::transmit(), and NSGigE::transmit().