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arch
power
isa.hh
Go to the documentation of this file.
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/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* Copyright (c) 2009 The University of Edinburgh
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Timothy M. Jones
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*/
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#ifndef __ARCH_POWER_ISA_HH__
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#define __ARCH_POWER_ISA_HH__
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#include "
arch/power/registers.hh
"
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#include "
arch/power/types.hh
"
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#include "
base/misc.hh
"
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#include "
sim/sim_object.hh
"
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struct
PowerISAParams;
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class
ThreadContext
;
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class
Checkpoint;
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class
EventManager
;
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namespace
PowerISA
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{
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class
ISA
:
public
SimObject
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{
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protected
:
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MiscReg
dummy
;
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MiscReg
miscRegs
[
NumMiscRegs
];
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public
:
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typedef
PowerISAParams
Params
;
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void
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clear
()
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{
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}
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MiscReg
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readMiscRegNoEffect
(
int
misc_reg)
const
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{
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fatal
(
"Power does not currently have any misc regs defined\n"
);
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return
dummy
;
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}
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MiscReg
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readMiscReg
(
int
misc_reg,
ThreadContext
*tc)
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{
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fatal
(
"Power does not currently have any misc regs defined\n"
);
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return
dummy
;
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}
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void
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setMiscRegNoEffect
(
int
misc_reg,
const
MiscReg
&
val
)
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{
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fatal
(
"Power does not currently have any misc regs defined\n"
);
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}
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void
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setMiscReg
(
int
misc_reg,
const
MiscReg
&
val
,
ThreadContext
*tc)
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{
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fatal
(
"Power does not currently have any misc regs defined\n"
);
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}
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int
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flattenIntIndex
(
int
reg
)
const
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{
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return
reg
;
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}
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int
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flattenFloatIndex
(
int
reg
)
const
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{
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return
reg
;
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}
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// dummy
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int
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flattenCCIndex
(
int
reg
)
const
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{
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return
reg
;
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}
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int
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flattenMiscIndex
(
int
reg
)
const
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{
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return
reg
;
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}
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void
startup
(
ThreadContext
*tc) {}
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using
SimObject::startup
;
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const
Params
*
params
()
const
;
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ISA
(
Params
*
p
);
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};
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}
// namespace PowerISA
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#endif // __ARCH_POWER_ISA_HH__
PowerISA::ISA::setMiscReg
void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
Definition:
isa.hh:84
X86ISA::reg
Bitfield< 5, 3 > reg
Definition:
types.hh:89
PowerISA::ISA::Params
PowerISAParams Params
Definition:
isa.hh:56
registers.hh
PowerISA::ISA::dummy
MiscReg dummy
Definition:
isa.hh:52
PowerISA::ISA::clear
void clear()
Definition:
isa.hh:59
PowerISA::ISA::flattenIntIndex
int flattenIntIndex(int reg) const
Definition:
isa.hh:90
PowerISA::ISA::startup
void startup(ThreadContext *tc)
Definition:
isa.hh:114
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Definition:
thread_context.hh:93
X86ISA::val
Bitfield< 63 > val
Definition:
misc.hh:770
misc.hh
PowerISA::ISA::flattenCCIndex
int flattenCCIndex(int reg) const
Definition:
isa.hh:103
PowerISA::NumMiscRegs
const int NumMiscRegs
Definition:
registers.hh:71
PowerISA::ISA::params
const Params * params() const
Definition:
isa.cc:54
fatal
#define fatal(...)
Definition:
misc.hh:163
PowerISA::ISA::miscRegs
MiscReg miscRegs[NumMiscRegs]
Definition:
isa.hh:53
types.hh
PowerISA::ISA::flattenMiscIndex
int flattenMiscIndex(int reg) const
Definition:
isa.hh:109
sim_object.hh
PowerISA::MiscReg
uint64_t MiscReg
Definition:
registers.hh:53
PowerISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
Definition:
isa.hh:78
PowerISA::ISA::flattenFloatIndex
int flattenFloatIndex(int reg) const
Definition:
isa.hh:96
PowerISA::ISA::ISA
ISA(Params *p)
Definition:
isa.cc:47
PowerISA::ISA::readMiscRegNoEffect
MiscReg readMiscRegNoEffect(int misc_reg) const
Definition:
isa.hh:64
MipsISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:325
EventManager
Definition:
eventq.hh:710
SimObject
Abstract superclass for simulation objects.
Definition:
sim_object.hh:94
PowerISA::ISA::readMiscReg
MiscReg readMiscReg(int misc_reg, ThreadContext *tc)
Definition:
isa.hh:71
PowerISA::ISA
Definition:
isa.hh:49
SimObject::startup
virtual void startup()
startup() is the final initialization call before simulation.
Definition:
sim_object.cc:97
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