PowerISA Namespace Reference

Namespaces
	Kernel

Classes
class	Decoder
class	PowerFault
class	UnimplementedOpcodeFault
class	MachineCheckFault
class	AlignmentFault
class	PCDependentDisassembly
	Base class for instructions whose disassembly is not purely a function of the machine instruction (i.e., it depends on the PC). More...
class	BranchPCRel
	Base class for unconditional, PC-relative branches. More...
class	BranchNonPCRel
	Base class for unconditional, non PC-relative branches. More...
class	BranchCond
	Base class for conditional branches. More...
class	BranchPCRelCond
	Base class for conditional, PC-relative branches. More...
class	BranchNonPCRelCond
	Base class for conditional, non PC-relative branches. More...
class	BranchRegCond
	Base class for conditional, register-based branches. More...
class	CondLogicOp
	Class for condition register logical operations. More...
class	CondMoveOp
	Class for condition register move operations. More...
class	FloatOp
	Base class for floating point operations. More...
class	IntOp
	We provide a base class for integer operations and then inherit for several other classes. More...
class	IntImmOp
	Class for integer immediate (signed and unsigned) operations. More...
class	IntShiftOp
	Class for integer operations with a shift. More...
class	IntRotateOp
	Class for integer rotate operations. More...
class	MemOp
	Base class for memory operations. More...
class	MemDispOp
	Class for memory operations with displacement. More...
class	MiscOp
	Class for misc operations. More...
class	PowerStaticInst
class	Interrupts
class	ISA
struct	VAddr
struct	PTE
union	AnyReg
class	RemoteGDB
class	ProcessInfo
class	StackTrace
struct	TlbEntry
class	TLB

Typedefs
typedef uint8_t	RegIndex
typedef uint64_t	IntReg
typedef uint64_t	FloatRegBits
typedef double	FloatReg
typedef uint64_t	MiscReg
typedef uint8_t	CCReg
typedef uint32_t	MachInst

Enumerations
enum	MiscRegIndex { NUM_MISCREGS = 0 }
enum	MiscIntRegNums {   INTREG_CR = NumIntArchRegs, INTREG_XER, INTREG_LR, INTREG_CTR,   INTREG_FPSCR, INTREG_RSV, INTREG_RSV_LEN, INTREG_RSV_ADDR }

Functions
template<class XC >
void	handleLockedSnoop (XC *xc, PacketPtr pkt, Addr cacheBlockMask)
template<class XC >
void	handleLockedRead (XC *xc, Request *req)
template<class XC >
void	handleLockedSnoopHit (XC *xc)
template<class XC >
bool	handleLockedWrite (XC *xc, Request *req, Addr cacheBlockMask)
	BitUnion32 (Cr) SubBitUnion(cr0
	EndSubBitUnion (cr0) Bitfield< 27
	EndBitUnion (Cr) BitUnion32(Xer) Bitfield< 31 > so
	EndBitUnion (Xer) BitUnion32(Fpscr) Bitfield< 31 > fx
	SubBitUnion (fprf, 16, 12) Bitfield< 16 > c
	SubBitUnion (fpcc, 15, 12) Bitfield< 15 > fl
	EndSubBitUnion (fpcc) EndSubBitUnion(fprf) Bitfield< 10 > vxsqrt
	BitUnion32 (ExtMachInst) Bitfield< 25
void	copyRegs (ThreadContext *src, ThreadContext *dest)
uint64_t	getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp)
void	skipFunction (ThreadContext *tc)
void	initCPU (ThreadContext *tc, int cpuId)
PCState	buildRetPC (const PCState &curPC, const PCState &callPC)
template<class TC >
void	zeroRegisters (TC *tc)
	Function to ensure ISA semantics about 0 registers. More...
void	startupCPU (ThreadContext *tc, int cpuId)
static void	copyMiscRegs (ThreadContext *src, ThreadContext *dest)
void	advancePC (PCState &pc, const StaticInstPtr &inst)
static bool	inUserMode (ThreadContext *tc)
uint64_t	getExecutingAsid (ThreadContext *tc)
Addr	vtophys (Addr vaddr)
Addr	vtophys (ThreadContext *tc, Addr vaddr)
Addr	PteAddr (Addr a)

Variables
StaticInstPtr	decodeInst (ExtMachInst)
const Addr	PageShift = 12
const Addr	PageBytes = ULL(1) << PageShift
const Addr	Page_Mask = ~(PageBytes - 1)
const Addr	PageOffset = PageBytes - 1
const Addr	PteShift = 3
const Addr	NPtePageShift = PageShift - PteShift
const Addr	NPtePage = ULL(1) << NPtePageShift
const Addr	PteMask = NPtePage - 1
const int	MachineBytes = 4
const ExtMachInst	NoopMachInst = 0x60000000
const bool	HasUnalignedMemAcc = true
const bool	CurThreadInfoImplemented = false
const int	CurThreadInfoReg = -1
const char *const	miscRegName [NUM_MISCREGS]
Bitfield< 31 >	lt
Bitfield< 30 >	gt
Bitfield< 29 >	eq
Bitfield< 28 >	so
	cr1
Bitfield< 30 >	ov
Bitfield< 29 >	ca
Bitfield< 30 >	fex
Bitfield< 29 >	vx
Bitfield< 28 >	ox
Bitfield< 27 >	ux
Bitfield< 26 >	zx
Bitfield< 25 >	xx
Bitfield< 24 >	vxsnan
Bitfield< 23 >	vxisi
Bitfield< 22 >	vxidi
Bitfield< 21 >	vxzdz
Bitfield< 20 >	vximz
Bitfield< 19 >	vxvc
Bitfield< 18 >	fr
Bitfield< 17 >	fi
Bitfield< 14 >	fg
Bitfield< 13 >	fe
Bitfield< 12 >	fu
Bitfield< 9 >	vxcvi
Bitfield< 8 >	ve
Bitfield< 7 >	oe
Bitfield< 6 >	ue
Bitfield< 5 >	ze
Bitfield< 4 >	xe
Bitfield< 3 >	ni
Bitfield< 2, 1 >	rn
const int	MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1
const int	NumIntArchRegs = 32
const int	NumIntSpecialRegs = 9
const int	NumFloatArchRegs = 32
const int	NumFloatSpecialRegs = 0
const int	NumInternalProcRegs = 0
const int	NumIntRegs = NumIntArchRegs + NumIntSpecialRegs
const int	NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs
const int	NumCCRegs = 0
const int	NumMiscRegs = NUM_MISCREGS
const int	ReturnValueReg = 3
const int	ArgumentReg0 = 3
const int	ArgumentReg1 = 4
const int	ArgumentReg2 = 5
const int	ArgumentReg3 = 6
const int	ArgumentReg4 = 7
const int	FramePointerReg = 31
const int	StackPointerReg = 1
const int	ZeroReg = NumIntRegs - 1
const int	SyscallNumReg = 0
const int	SyscallPseudoReturnReg = 3
const int	SyscallSuccessReg = 3
const int	FP_Reg_Base = NumIntRegs
const int	CC_Reg_Base = FP_Reg_Base + NumFloatRegs
const int	Misc_Reg_Base = CC_Reg_Base + NumCCRegs
const int	Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
	rs
Bitfield< 20, 16 >	ra
Bitfield< 15, 11 >	sh
Bitfield< 10, 6 >	mb
Bitfield< 5, 1 >	me
Bitfield< 15, 0 >	si
Bitfield< 15, 0 >	d
Bitfield< 20, 11 >	spr
Bitfield< 25, 2 >	li
Bitfield< 1 >	aa
Bitfield< 25, 23 >	bf
Bitfield< 15, 2 >	bd
Bitfield< 25, 21 >	bo
Bitfield< 20, 16 >	bi
Bitfield< 20, 18 >	bfa
Bitfield< 0 >	rc31
Bitfield< 25, 21 >	bt
Bitfield< 20, 16 >	ba
Bitfield< 15, 11 >	bb
Bitfield< 19, 12 >	fxm

Typedef Documentation

typedef uint8_t PowerISA::CCReg

Definition at line 56 of file registers.hh.

typedef double PowerISA::FloatReg

Definition at line 52 of file registers.hh.

typedef uint64_t PowerISA::FloatRegBits

Definition at line 51 of file registers.hh.

typedef uint64_t PowerISA::IntReg

Definition at line 48 of file registers.hh.

typedef uint32_t PowerISA::MachInst

Definition at line 41 of file types.hh.

typedef uint64_t PowerISA::MiscReg

Definition at line 53 of file registers.hh.

typedef uint8_t PowerISA::RegIndex

Definition at line 46 of file registers.hh.

Enumeration Type Documentation

enum PowerISA::MiscIntRegNums

Enumerator
INTREG_CR
INTREG_XER
INTREG_LR
INTREG_CTR
INTREG_FPSCR
INTREG_RSV
INTREG_RSV_LEN
INTREG_RSV_ADDR

Definition at line 102 of file registers.hh.

enum PowerISA::MiscRegIndex

Enumerator
NUM_MISCREGS

Definition at line 39 of file miscregs.hh.

Function Documentation

void PowerISA::advancePC ( PCState &  pc, const StaticInstPtr &  inst  )

inline

Definition at line 76 of file utility.hh.

PowerISA::BitUnion32

(

ExtMachInst

)

PowerISA::BitUnion32

(

Cr

)

PCState PowerISA::buildRetPC ( const PCState &  curPC, const PCState &  callPC  )

inline

Definition at line 45 of file utility.hh.

static void PowerISA::copyMiscRegs ( ThreadContext *  src, ThreadContext *  dest  )

inlinestatic

Definition at line 69 of file utility.hh.

Referenced by copyRegs().

void PowerISA::copyRegs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

Definition at line 42 of file utility.cc.

References copyMiscRegs(), ArmISA::i, NumCCRegs, NumFloatRegs, NumIntRegs, ThreadContext::pcState(), ThreadContext::readFloatRegBits(), ThreadContext::readIntReg(), ThreadContext::setFloatRegBits(), and ThreadContext::setIntReg().

PowerISA::EndBitUnion

(

Cr

)

PowerISA::EndBitUnion

(

Xer

)

PowerISA::EndSubBitUnion

(

cr0

)

PowerISA::EndSubBitUnion

(

fpcc

)

uint64_t PowerISA::getArgument	(	ThreadContext *	tc,
		int &	number,
		uint16_t	size,
		bool	fp
	)

Definition at line 63 of file utility.cc.

References panic.

uint64_t PowerISA::getExecutingAsid ( ThreadContext *  tc )

inline

Definition at line 90 of file utility.hh.

template<class XC >

void PowerISA::handleLockedRead ( XC *  xc, Request *  req  )

inline

Definition at line 58 of file locked_mem.hh.

template<class XC >

void PowerISA::handleLockedSnoop ( XC *  xc, PacketPtr  pkt, Addr  cacheBlockMask  )

inline

Definition at line 52 of file locked_mem.hh.

template<class XC >

void PowerISA::handleLockedSnoopHit ( XC *  xc )

inline

Definition at line 64 of file locked_mem.hh.

template<class XC >

bool PowerISA::handleLockedWrite ( XC *  xc, Request *  req, Addr  cacheBlockMask  )

inline

Definition at line 70 of file locked_mem.hh.

void PowerISA::initCPU	(	ThreadContext *	tc,
		int	cpuId
	)

Definition at line 76 of file utility.cc.

References panic.

static bool PowerISA::inUserMode ( ThreadContext *  tc )

inlinestatic

Definition at line 84 of file utility.hh.

Addr PowerISA::PteAddr ( Addr  a )

inline

Definition at line 50 of file vtophys.hh.

References PteMask, and PteShift.

Referenced by PowerISA::VAddr::level1(), PowerISA::VAddr::level2(), and PowerISA::VAddr::level3().

void PowerISA::skipFunction

(

ThreadContext *

tc

)

Definition at line 70 of file utility.cc.

References panic.

void PowerISA::startupCPU ( ThreadContext *  tc, int  cpuId  )

inline

Definition at line 60 of file utility.hh.

References ThreadContext::activate().

PowerISA::SubBitUnion	(	fprf	,
		16	,
		12
	)

PowerISA::SubBitUnion	(	fpcc	,
		15	,
		12
	)

Addr PowerISA::vtophys ( Addr  vaddr )

inline

Definition at line 36 of file vtophys.cc.

References DPRINTF, fatal, AlphaISA::IsK0Seg(), AlphaISA::IsUSeg(), AlphaISA::K0Seg2Phys(), panic, and RiscvISA::vaddr.

Referenced by BaseSimpleCPU::dbg_vtophys(), CheckerCPU::dbg_vtophys(), FSTranslatingPortProxy::memsetBlob(), FSTranslatingPortProxy::readBlob(), RiscvISA::vtophys(), Sinic::Device::write(), and FSTranslatingPortProxy::writeBlob().

Addr PowerISA::vtophys ( ThreadContext *  tc, Addr  vaddr  )

inline

Definition at line 42 of file vtophys.cc.

References addr, betoh(), bits(), DPRINTF, fatal, ThreadContext::getDTBPtr(), ThreadContext::getITBPtr(), ThreadContext::getPhysProxy(), SparcISA::TLB::GetTsbPtr(), SparcISA::hpriv, AlphaISA::IPR_PALtemp20, AlphaISA::IsK0Seg(), AlphaISA::K0Seg2Phys(), AlphaISA::kernel_pte_lookup(), X86ISA::logBytes, SparcISA::TLB::lookup(), ArmISA::mask, SparcISA::MISCREG_TLB_DATA, NoFault, AlphaISA::VAddr::offset(), AlphaISA::PageTableEntry::paddr(), AlphaISA::PalMax, panic, AlphaISA::PcPAL(), SparcISA::PageTableEntry::populate(), SparcISA::TlbEntry::pte, BaseTLB::Read, PortProxy::read(), ThreadContext::readMiscRegNoEffect(), X86ISA::Walker::startFunctional(), MipsISA::tbe, SparcISA::PageTableEntry::translate(), ULL, SparcISA::TteTag::va(), MipsISA::vaddr, SparcISA::VAddrAMask, SparcISA::TteTag::valid(), AlphaISA::PageTableEntry::valid(), RiscvISA::vtophys(), and X86ISA::x.

template<class TC >

void PowerISA::zeroRegisters

(

TC *

tc

)

Function to ensure ISA semantics about 0 registers.

Parameters

tc	The thread context.

Variable Documentation

Bitfield<1> PowerISA::aa

Definition at line 61 of file types.hh.

const int PowerISA::ArgumentReg0 = 3

Definition at line 75 of file registers.hh.

const int PowerISA::ArgumentReg1 = 4

Definition at line 76 of file registers.hh.

const int PowerISA::ArgumentReg2 = 5

Definition at line 77 of file registers.hh.

const int PowerISA::ArgumentReg3 = 6

Definition at line 78 of file registers.hh.

const int PowerISA::ArgumentReg4 = 7

Definition at line 79 of file registers.hh.

Bitfield<20, 16> PowerISA::ba

Definition at line 74 of file types.hh.

Bitfield<15, 11> PowerISA::bb

Definition at line 75 of file types.hh.

Referenced by ControlFlowInfo::connectBasicBlocks().

Bitfield<15, 2> PowerISA::bd

Definition at line 63 of file types.hh.

Bitfield<25, 23> PowerISA::bf

Definition at line 62 of file types.hh.

Referenced by PowerISA::PowerStaticInst::insertCRField().

Bitfield<20, 18> PowerISA::bfa

Definition at line 66 of file types.hh.

Bitfield<20, 16> PowerISA::bi

Definition at line 65 of file types.hh.

Referenced by LTAGE::btbUpdate(), LTAGE::getGHR(), LTAGE::predict(), LTAGE::squash(), LTAGE::update(), and LTAGE::updateHistories().

Bitfield<25, 21> PowerISA::bo

Definition at line 64 of file types.hh.

Bitfield<25, 21> PowerISA::bt

Definition at line 73 of file types.hh.

Bitfield<29> PowerISA::ca

Definition at line 59 of file miscregs.hh.

const int PowerISA::CC_Reg_Base = FP_Reg_Base + NumFloatRegs

Definition at line 92 of file registers.hh.

PowerISA::cr1

Definition at line 53 of file miscregs.hh.

const bool PowerISA::CurThreadInfoImplemented = false

Definition at line 72 of file isa_traits.hh.

const int PowerISA::CurThreadInfoReg = -1

Definition at line 73 of file isa_traits.hh.

Bitfield<15, 0> PowerISA::d

Definition at line 56 of file types.hh.

StaticInstPtr PowerISA::decodeInst(ExtMachInst)

Bitfield<29> PowerISA::eq

Definition at line 50 of file miscregs.hh.

Referenced by abortHandler(), ThermalModel::doStep(), ThermalResistor::getEquation(), ThermalDomain::getEquation(), ThermalCapacitor::getEquation(), LinearSystem::operator[](), pybind_init_event(), BaseRemoteGDB::scheduleInstCommitEvent(), and LinearSystem::toStr().

Bitfield<13> PowerISA::fe

Definition at line 83 of file miscregs.hh.

Bitfield<30> PowerISA::fex

Definition at line 64 of file miscregs.hh.

Bitfield<14> PowerISA::fg

Definition at line 82 of file miscregs.hh.

Bitfield<17> PowerISA::fi

Definition at line 77 of file miscregs.hh.

const int PowerISA::FP_Reg_Base = NumIntRegs

Definition at line 91 of file registers.hh.

Bitfield<18> PowerISA::fr

Definition at line 76 of file miscregs.hh.

const int PowerISA::FramePointerReg = 31

Definition at line 80 of file registers.hh.

Bitfield<12> PowerISA::fu

Definition at line 84 of file miscregs.hh.

Referenced by Minor::Execute::commit(), Minor::Execute::evaluate(), Minor::Execute::Execute(), FUPool::FUPool(), Minor::Execute::getCommittingThread(), and Minor::Execute::issue().

Bitfield<19, 12> PowerISA::fxm

Definition at line 78 of file types.hh.

Bitfield<30> PowerISA::gt

Definition at line 49 of file miscregs.hh.

const bool PowerISA::HasUnalignedMemAcc = true

Definition at line 70 of file isa_traits.hh.

Bitfield<25, 2> PowerISA::li

Definition at line 60 of file types.hh.

Bitfield<31> PowerISA::lt

Definition at line 47 of file miscregs.hh.

const int PowerISA::MachineBytes = 4

Definition at line 64 of file isa_traits.hh.

const int PowerISA::Max_Reg_Index = Misc_Reg_Base + NumMiscRegs

Definition at line 94 of file registers.hh.

const int PowerISA::MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1

Definition at line 44 of file registers.hh.

Bitfield<10, 6> PowerISA::mb

Definition at line 51 of file types.hh.

Referenced by PowerISA::IntRotateOp::generateDisassembly().

Bitfield< 5, 1> PowerISA::me

Definition at line 52 of file types.hh.

Referenced by PowerISA::IntRotateOp::generateDisassembly().

const int PowerISA::Misc_Reg_Base = CC_Reg_Base + NumCCRegs

Definition at line 93 of file registers.hh.

const char* const PowerISA::miscRegName[NUM_MISCREGS]

Initial value:

= {
}

Definition at line 43 of file miscregs.hh.

Bitfield<3> PowerISA::ni

Definition at line 94 of file miscregs.hh.

Referenced by TCPIface::establishConnection(), GarnetNetwork::GarnetNetwork(), GarnetNetwork::get_router_id(), and TCPIface::TCPIface().

const ExtMachInst PowerISA::NoopMachInst = 0x60000000

Definition at line 67 of file isa_traits.hh.

const Addr PowerISA::NPtePage = ULL(1) << NPtePageShift

Definition at line 61 of file isa_traits.hh.

const Addr PowerISA::NPtePageShift = PageShift - PteShift

Definition at line 60 of file isa_traits.hh.

Referenced by PowerISA::VAddr::level1(), and PowerISA::VAddr::level2().

const int PowerISA::NumCCRegs = 0

Definition at line 70 of file registers.hh.

Referenced by copyRegs().

const int PowerISA::NumFloatArchRegs = 32

Definition at line 64 of file registers.hh.

Referenced by PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), and PowerISA::RemoteGDB::PowerGdbRegCache::setRegs().

const int PowerISA::NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs

Definition at line 69 of file registers.hh.

Referenced by copyRegs().

const int PowerISA::NumFloatSpecialRegs = 0

Definition at line 65 of file registers.hh.

const int PowerISA::NumIntArchRegs = 32

Definition at line 59 of file registers.hh.

Referenced by PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), and PowerISA::RemoteGDB::PowerGdbRegCache::setRegs().

const int PowerISA::NumInternalProcRegs = 0

Definition at line 66 of file registers.hh.

const int PowerISA::NumIntRegs = NumIntArchRegs + NumIntSpecialRegs

Definition at line 68 of file registers.hh.

Referenced by copyRegs().

const int PowerISA::NumIntSpecialRegs = 9

Definition at line 63 of file registers.hh.

const int PowerISA::NumMiscRegs = NUM_MISCREGS

Definition at line 71 of file registers.hh.

Bitfield< 10 > PowerISA::oe

Definition at line 90 of file miscregs.hh.

Bitfield<30> PowerISA::ov

Definition at line 58 of file miscregs.hh.

Bitfield<28> PowerISA::ox

Definition at line 66 of file miscregs.hh.

const Addr PowerISA::Page_Mask = ~(PageBytes - 1)

Definition at line 56 of file isa_traits.hh.

Referenced by PowerISA::VAddr::page().

const Addr PowerISA::PageBytes = ULL(1) << PageShift

Definition at line 55 of file isa_traits.hh.

Referenced by PowerProcess::argsInit().

const Addr PowerISA::PageOffset = PageBytes - 1

Definition at line 57 of file isa_traits.hh.

Referenced by PowerISA::VAddr::offset().

const Addr PowerISA::PageShift = 12

Definition at line 54 of file isa_traits.hh.

Referenced by PowerISA::VAddr::level1(), PowerISA::VAddr::level2(), PowerISA::VAddr::level3(), and PowerISA::VAddr::vpn().

const Addr PowerISA::PteMask = NPtePage - 1

Definition at line 62 of file isa_traits.hh.

Referenced by PteAddr().

const Addr PowerISA::PteShift = 3

Definition at line 59 of file isa_traits.hh.

Referenced by PteAddr().

Bitfield<20, 16> PowerISA::ra

Definition at line 47 of file types.hh.

Referenced by FreebsdArmSystem::initState(), and AlphaISA::StackTrace::trace().

Bitfield<0> PowerISA::rc31

Definition at line 69 of file types.hh.

const int PowerISA::ReturnValueReg = 3

Definition at line 74 of file registers.hh.

Bitfield<2,1> PowerISA::rn

Definition at line 95 of file miscregs.hh.

PowerISA::rs

Definition at line 46 of file types.hh.

Bitfield<15, 11> PowerISA::sh

Definition at line 50 of file types.hh.

Bitfield<15, 0> PowerISA::si

Definition at line 55 of file types.hh.

Referenced by GenericISA::BasicDecodeCache::decode(), and MathExprPowerModel::getStatValue().

Bitfield<28> PowerISA::so

Definition at line 51 of file miscregs.hh.

Bitfield<20, 11> PowerISA::spr

Definition at line 59 of file types.hh.

const int PowerISA::StackPointerReg = 1

Definition at line 81 of file registers.hh.

const int PowerISA::SyscallNumReg = 0

Definition at line 86 of file registers.hh.

const int PowerISA::SyscallPseudoReturnReg = 3

Definition at line 87 of file registers.hh.

const int PowerISA::SyscallSuccessReg = 3

Definition at line 88 of file registers.hh.

Bitfield<6> PowerISA::ue

Definition at line 91 of file miscregs.hh.

Bitfield<27> PowerISA::ux

Definition at line 67 of file miscregs.hh.

Bitfield<8> PowerISA::ve

Definition at line 89 of file miscregs.hh.

Bitfield<29> PowerISA::vx

Definition at line 65 of file miscregs.hh.

Referenced by ArmISA::VldMultOp64::VldMultOp64(), ArmISA::VldSingleOp64::VldSingleOp64(), ArmISA::VstMultOp64::VstMultOp64(), and ArmISA::VstSingleOp64::VstSingleOp64().

Bitfield<9> PowerISA::vxcvi

Definition at line 88 of file miscregs.hh.

Bitfield<22> PowerISA::vxidi

Definition at line 72 of file miscregs.hh.

Bitfield<20> PowerISA::vximz

Definition at line 74 of file miscregs.hh.

Bitfield<23> PowerISA::vxisi

Definition at line 71 of file miscregs.hh.

Bitfield<24> PowerISA::vxsnan

Definition at line 70 of file miscregs.hh.

Bitfield<19> PowerISA::vxvc

Definition at line 75 of file miscregs.hh.

Bitfield<21> PowerISA::vxzdz

Definition at line 73 of file miscregs.hh.

Bitfield<4> PowerISA::xe

Definition at line 93 of file miscregs.hh.

Referenced by main().

Bitfield<25> PowerISA::xx

Definition at line 69 of file miscregs.hh.

Bitfield<5> PowerISA::ze

Definition at line 92 of file miscregs.hh.

const int PowerISA::ZeroReg = NumIntRegs - 1

Definition at line 84 of file registers.hh.

Bitfield<26> PowerISA::zx

Definition at line 68 of file miscregs.hh.