CS/ECE 752 Advanced Computer Architecture I Fall 2008 Section 1 Instructor David A. Wood and T. A. Khai Tran URL: http://www.cs.wisc.edu/~david/courses/cs752/Fall2008/

Homework 4 // Due at Lecture Wednesday, Nov 19

Problem 1 (20 points)

H&P, 4th edition, Question 5.2

Problem 2 (40 points)

H&P, 4th edition, Question 5.18
Plot the results as in figure 5.33 and describe how you can determine the answers to the different questions.

Problem 3 (40 points)

Consider a virtual memory system with the following properties:

• 53 bit virtual address (byte addressable)
• 8-KByte pages
• 41-bit physical byte addresses
• 128GBytes of physical memory
• 1-MByte cache that is 8-way set-associative and is accessed with physical addresses
• a 64 entry TLB

1. What is the total size of the page table for each process on this machine, assuming that the valid, protection, dirty, and use bits take a total of 4 bits, and that all of the virtual pages are in use? (Assume that disk addresses are not stored in the page table). Calculate both the minimum number of bits needed to hold the information and the "typical" storage assuming a page table entry is rounded up to the next power of two number of bytes. (10 points)
2. Draw a diagram of the hardware in the memory system including the cache and TLB. Make sure you show how different fields of the address (i.e. which bits) are used to access the cache and TLB. Use Figure C.24 in H&P as a model for your diagram. (10 points)
3. Explain how a memory access proceeds through the memory system for each of the following scenarios: cache hit, cache miss, TLB hit, and TLB miss. (20 points)