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Reader 2This reader may still change slightly, and, if so, I will send email notice of changes. H&P is John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Third Edition, 2002. HJ&S is Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi, Readings in Computer Architecture, Morgan Kaufmann Publishers, 2000. VectorsH&P Appendix G: Vector Processors. URL http://books.elsevier.com/companions/1558605967/appendices/1558605967-appe ndix-g.pdf. Richard M. Russell. The Cray-1 Computer System, Communications of the ACM, January 1978. Reprinted in HJ&S pp. 40-49. CachesH&P Chapter 5.1-5.2 Norman P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, Proc. International Symposium on Computer Architecture , June 1990. Reprinted in HJ&S pp. 395-404. David H. Albonesi, Selective Cache Ways: On-demand Cache Resource Allocation, Proc. International Symposium on Microarchitecture (MICRO), 1999. Online PDF for University of Wisconsin only. Changkyu Kim, Doug Burger, and Stephen W. Keckler. An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches, Proc. Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2002. Online PDF for University of Wisconsin only. MemoryH&P Chapter 5.3 - 5.7 The PC Guide: DRAM Technologies, http://www.pcguide.com/ref/ram/tech.htm URL http://www.pcguide.com/ref/ram/tech.htm and ten Next pages (reference). Brinda Ganesh, Aamer Jaleel, David Wang, Bruce Jacob, Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling, HPCA 2007. PDF Bruce Jacob and Trevor Mudge. Virtual Memory on Contemporary Processors, IEEE Micro, vol. 18, no. 4, 1998. Online PDF for University of Wisconsin only. Wen-Hann Wang, Jean-Loup Baer, and Henry M. Levy. Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy, Proc. International Symposium on Computer Architecture , June 1989. Reprinted in HJ&S pp. 434-442. StorageH&P Chapter 6.1-6.6 David A. Patterson, Garth Gibson, and Randy H. Katz. A Case for Redundant Arrays of Inexpensive Disks (RAID), Proc. ACM SIGMOD Conference, June 1988. Reprinted in HJ&S pp. 474-481. Multithreading and MultiprocessorsH&P Chapter 4 Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, and Rebecca L. Stamm. Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Proc. 23rd Annual International Symposium on Computer Architecture, May 1996. Reprinted in HJ&S pp. 350-361. H&P Chapter 6 Sections 6.1, 6.3, & 6.8. Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun, Niagara: A 32-Way Multithreaded Sparc Processor, IEEE Micro, March-April 2005, pp. 21-29. Online PDF for University of Wisconsin only. James Laudon, UltraSPARC T1: A 32-threaded CMP for Servers, Talk to Wisconsin CS/ECE 757 Class, March 30, 2006 (reference). Online PDF for University of Wisconsin only. MiscellaneousJohn Owens, Streaming Architectures and Technology Trends (Chapter 29) GPU Gems 2, Nvidia Web Page, 2005. Online PDF. Emmett Kilgariff and Randima Fernando. The GeForce 6 Series GPU Architecture (Chapter 30) GPU Gems 2, Nvidia Web Page, 2005 (reference). Online PDF. Keith Adams and Ole Ageson. A Comparison of Software and Hardware Techniques for x86 Virtualization, Procedings of ASPLOS 2006, October 2006. Online PDF for University of Wisconsin only. Matthew Adiletta, Mark Rosenbluth, Debra Bernstein, Gilbert Wolrich, and Hugh Wilkinson. The Next Generation of Intel IXP Network Processors, Intel Technical Journal (ITJ), Volume 6, Issue 3, August 15, 2002 (reference). Online PDF. Additional readingSanvido, M. A. A.; Chu, F. R.; Kulkarni, A.; Selinger, R., "nand Flash Memory and Its Role in Storage Architectures," Proceedings of the IEEE , vol.96, no.11, pp.1864-1874, Nov. 2008 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4694025&isnumber=4694715 |