CS/ECE 752 Advanced Computer Architecture I Spring 2006 Section 1 Instructor Mark D. Hill and T. A. Ahmed Ghanem URL: http://www.cs.wisc.edu/~markhill/cs752/Spring2006/

Homework 1 // Due at Lecture Wed Feb 1

H&P is John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Third Edition, 2002.

Disclaimer: To avoid being too much work, homeworks only sample course material. Exams also sample course material and will include questions on material not covered in homeworks. Homeworks will tend to cover material related to the text, reviews focus on papers, and exams on both.

Problem 1 (8 points)

H&P Problem 1.2 with the following change: Make vector mode 5 times faster than normal modes (instead of 10 times).

Problem 2 (4 points)

H&P Problem 1.11 with the following change: Compare Harmonic and Arithmetic means instead.

Problem 3 (4 points)

H&P Problem 2.5.(a)

Problem 4 (4 points)

As transistor sizes become smaller with technology, the electrical charge they hold lessens.  As a result, logic devices, such as SRAMS, gates, and latches, become more sensitive to random alpha particle and neutron particle strikes that can hit a transistor and invert the state of the logic device.

Such transient errors are a serious unpredictable threat to the correct execution of a program.   However, some storage cells that are affected by transient faults will inevitably not affect the correct execution of a program.  For example, if a strike occurs to the storage cell of a NOP instruction's unused operand field (and not its opcode field), the error will not affect the correct-path instruction execution.  Determining the susceptibility of a logic device to these strikes is helpful to microprocessor designers gauging the amount of error protection/correction the processor needs for reliable behavior.

Researchers have defined the following terms related to characterizing faults:

• An Architectually Correct Execution (ACE) instruction is an instruction whose results may potentially affect the output of the program and thus it is imperative particle strikes do not negatively alter the instruction's encoding.

• The Architectual Vulnerability Factor (AVF), is the fraction of time an ACE instruction is present in a logic device.

A given system has a 64-entry Instruction Queue.  From observation, two instructions are fetched (on average) each cycle and remain in the queue for an average of 18 cycles.  One out of every 4 instructions are ACE instructions.  What is the average AVF of a single instruction queue entry?

Problem 5 (10 points)

ARM instruction set architecure (ISA) is one of the most widely used ISAs. ARM chips are mainly targeted towards embedded applications like modems, cellular phones, and automobiles.

a) In two-three paragraphs, describe ARMv5e (or newer) ISA. Your description should include: instruction set length, operand types, memory addressing modes, immediate types, and any special features (like special instructions, explicit or implicit condition codes).

b) THUMB is an extension to the ARM architecture. In one or two paragraphs describe the main differences between ARM and THUMB ISA. The comparison should include: instruction set length, memory addressing modes, immediate types, and special features.

Note: This is information is not in your text or assigned readings.