CS/ECE 752 Advanced Computer Architecture I Spring 2006 Section 1 Instructor Mark D. Hill and T. A. Ahmed Ghanem URL: http://www.cs.wisc.edu/~markhill/cs752/Spring2006/

Homework 2 // Due at Lecture Fri Feb 17

Problem 1 (10 points)

H&P Problem 5.4abcde (not f) with the following changes: processor runs at 2 GHz (instead of 1.1) and in (e), the new processor runs at 3 GHz.

Problem 2 (6 points)

H&P Problem 5.18

Problem 3 (10 points)

Considering Micron memory chips, compare between SDRAM-133, DDR-266, and DDR2-533 in the following aspects:

a) Maximum Bandwidth.

b) Memory Structure (Banks, Rows, Columns, Width).

c) The minimum time to Zero Memory.

Note: Use the following product line for all of the chips: 256MB (64*4), Lead Free with 60-ball Pin Count.

Problem 4 (10 points)

(This problem is important well beyond the points we assign to it, because it begins our gentle ramp for teaching you about simulators, in general, and SimpleScalar, in particular.)

Using a CS Unix/Linux machine, download and install the Simplescalar v 3.0 Source code from http://www.simplescalar.com/. Descriptions for the Integer Benchmarks and Floating Point Benchmarks can be found at the Standard Performance Evaluation Corporation's website. To run the benchmarks, the command line arguments for each benchmark must be specified after the executables name. The command line options necessary for each benchmark are at /unsup/spec2000/benchspec/benchmark.cmdlines. From there, the associated Alpha executables and data files for the integer benchmarks and floating point benchmarks are in the CINT2000 and CFP2000 directories respectively.

a) The benchmarks have initialization phases at the beginning of their execution that run only once. Researchers tend to avoid collecting data from this region because it is not representative of the entire program. Choose a benchmark and find the likely end of its initialization period by observing its IPC in sim-outorder while it executes. Describe which benchmark you chose, your methodology, and your results. You might consider fast-forwarding to a certain instruction and limiting the number of instructions run at any one time. Assume the initialization period to be a factor of at least 10 million.

b) Using the performance of gcc in sim-outorder Use the following basic configuration:

Two Level Cache:
	L1 instruction cache: 8K 2-way set associative with 64 byte lines.
	L1 data cache: 8K 2-way set associative with 32 byte lines. 
	L2 unified cache: 128K 4-way set associative unified L2 cache with 64 byte lines.
	Branch prediction: use the default branch prediction settings.

report the IPC and the cache hierarchy miss rates if:

Two Level Cache using LRU replacement policy:
	L1 instruction cache: 8K 4-way set associative with 64 byte lines.
	L1 data cache: 8K 4-way set associative with 32 byte lines. 
	L2 unified cache: 128K 8-way set associative unified L2 cache with 64 byte lines.