CS/ECE 752 Advanced Computer Architecture I Spring 2006 Section 1 Instructor Mark D. Hill and T. A. Ahmed Ghanem URL: http://www.cs.wisc.edu/~markhill/cs752/Spring2006/

Homework 4 // Due at Lecture Mon Apr 3

Problem 1 (15 points)

Construct and fill the folowing tables:
1) ROB
2) Reservation Stations
3) Map Table
4) Free List
5) CDB
  for an R10K processor executing the following code:

loop: 	ldf X(r1),f1
  	ldf X(r2),f2
	mulf f0,f1,f2
	stf f0,X(r1)
	addi r1,4,r1
	addi r2,4,r2
	subi r3,1,r3
	BNQZ r3,loop

Assumptions:
1) The processor can retire one instruction at a time.
2) The processor can issue one instruction at a time.
3) Floating Point, load and store operations take 2 cycles to execute.
4) Integer operations take 1 cycle to execute.
5) Function units are not pipelined.
6) Branch prediction is perfect and the above loop is repeated twice.
7) There are only 12 physical registers and they can be used to store floating point and integer values.
8) There are only 8 ROB slots available and 5 reservation stations.

Tables status at cycle 3:
ROB 
ht 	#	Inst		T	Told	S	X	C
h	1	ldf X(r1),f1	PR#7	PR#2	c2	c3	c5
	2	ldf X(r2),f2	PR#8	PR#3	c3
	
Reservation Stations
#	FU	Busy	op	T	T1	T2
1	ALU	N	
2	L/S1	Y	ldf	PR#7	-	PR#4+
3	L/S2	N
4	FP1	N
5	FP2	N

Map Table
f0	PR#1+
f1	PR#7
f2	PR#8
r1	PR#4+
r2	PR#5+
r3	PR#6+

Free List
PR#9,PR#10,PR#11,PR#12

7th  ROB slot:
ht	#	Inst		T	Told	S	X	C
	7	subi		PR#12	PR#6	c13	c14	c15

Reference: The MIPS R10000 SuperScalar MicroProcessor By Kenneth C. Yeager

Problem 2 (10 points)

H&P Problem 7.7 parts a, b, and c only.

Problem 3 (5 points)

The following code segment, consisting of six instructions, needs to be executed 64 times 
for the evaluation of vector arithmetic expression: D(I)= A(I)+B(I)*C(I) 
for 0<=I<=63:
	load r1, B(i)
	load r2, C(i)
	mul r1,r1,r2
	load r3, A(i)
	add r3,r3,r1
	sto D(i), r3
where r1,r2, and r3 are CPU registers. Assume four cycles for each load or store, two cycles for add, 
and eight cycles for multiply on either a uniprocessor or a single PE in an SIMD machine.

	a) Calculate the total number of CPU cycles needed to execute the above code 64 times 
	on an in-order uniprocessor, ignoring all other delays.
	
	b) Consider using an SIMD prcoessor with 64 PEs to execute the above vector operations 
	in six synchronized vector instructions over 64-component vector data and both driven 
	by the same-speed clock.Calculate the total execution time on the SIMD machine, 
	ignoring instruction broadcast and other delays.
	
	c) What is the speedup gain of the SIMD processor over the uniprocessor one?