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gem5
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gem5
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#include <dyn_inst.hh>
Public Types | |
| enum | { MaxInstSrcRegs = TheISA::MaxInstSrcRegs, MaxInstDestRegs = TheISA::MaxInstDestRegs } |
| typedef Impl::O3CPU | O3CPU |
| Typedef for the CPU. More... | |
| typedef TheISA::MachInst | MachInst |
| Binary machine instruction type. More... | |
| typedef TheISA::ExtMachInst | ExtMachInst |
| Extended machine instruction type. More... | |
| typedef TheISA::RegIndex | RegIndex |
| Logical register index type. More... | |
| typedef TheISA::IntReg | IntReg |
| Integer register index type. More... | |
| typedef TheISA::FloatReg | FloatReg |
| typedef TheISA::FloatRegBits | FloatRegBits |
| typedef TheISA::CCReg | CCReg |
| typedef TheISA::MiscReg | MiscReg |
| Misc register index type. More... | |
 Public Types inherited from BaseDynInst< Impl > | |
| enum | { MaxInstSrcRegs = TheISA::MaxInstSrcRegs, MaxInstDestRegs = TheISA::MaxInstDestRegs } |
| typedef Impl::CPUType | ImplCPU |
| typedef ImplCPU::ImplState | ImplState |
| typedef TheISA::RegIndex | RegIndex |
| typedef Impl::DynInstPtr | DynInstPtr |
| typedef RefCountingPtr < BaseDynInst< Impl > > | BaseDynInstPtr |
| typedef std::list< DynInstPtr > ::iterator | ListIt |
| Public Types inherited from ExecContext | |
| typedef TheISA::IntReg | IntReg |
| typedef TheISA::PCState | PCState |
| typedef TheISA::FloatReg | FloatReg |
| typedef TheISA::FloatRegBits | FloatRegBits |
| typedef TheISA::MiscReg | MiscReg |
| typedef TheISA::CCReg | CCReg |
Public Member Functions | |
| BaseO3DynInst (const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, O3CPU *cpu) | |
| BaseDynInst constructor given a binary instruction. More... | |
| BaseO3DynInst (const StaticInstPtr &_staticInst, const StaticInstPtr &_macroop) | |
| BaseDynInst constructor given a static inst pointer. More... | |
| ~BaseO3DynInst () | |
| Fault | execute () |
| Executes the instruction. More... | |
| Fault | initiateAcc () |
| Initiates the access. More... | |
| Fault | completeAcc (PacketPtr pkt) |
| Completes the access. More... | |
| MiscReg | readMiscReg (int misc_reg) |
| Reads a misc. More... | |
| void | setMiscReg (int misc_reg, const MiscReg &val) |
| Sets a misc. More... | |
| TheISA::MiscReg | readMiscRegOperand (const StaticInst *si, int idx) |
| Reads a misc. More... | |
| void | setMiscRegOperand (const StaticInst *si, int idx, const MiscReg &val) |
| Sets a misc. More... | |
| void | updateMiscRegs () |
| Called at the commit stage to update the misc. More... | |
| void | forwardOldRegs () |
| Fault | hwrei () |
| Calls hardware return from error interrupt. More... | |
| void | trap (const Fault &fault) |
| Traps to handle specified fault. More... | |
| bool | simPalCheck (int palFunc) |
| Check for special simulator handling of specific PAL calls. More... | |
| void | syscall (int64_t callnum, Fault *fault) |
| Emulates a syscall. More... | |
| IntReg | readIntRegOperand (const StaticInst *si, int idx) |
| Reads an integer register. More... | |
| FloatReg | readFloatRegOperand (const StaticInst *si, int idx) |
| Reads a floating point register of single register width. More... | |
| FloatRegBits | readFloatRegOperandBits (const StaticInst *si, int idx) |
| Reads a floating point register in its binary format, instead of by value. More... | |
| CCReg | readCCRegOperand (const StaticInst *si, int idx) |
| void | setIntRegOperand (const StaticInst *si, int idx, IntReg val) |
| void | setFloatRegOperand (const StaticInst *si, int idx, FloatReg val) |
| Records an fp register being set to a value. More... | |
| void | setFloatRegOperandBits (const StaticInst *si, int idx, FloatRegBits val) |
| Records an fp register being set to an integer value. More... | |
| void | setCCRegOperand (const StaticInst *si, int idx, CCReg val) |
| Records a CC register being set to a value. More... | |
| MiscReg | readRegOtherThread (int misc_reg, ThreadID tid) |
| void | setRegOtherThread (int misc_reg, MiscReg val, ThreadID tid) |
| Fault | calcEA () |
| Calculates EA part of a memory instruction. More... | |
| Fault | memAccess () |
| Does the memory access part of a memory instruction. More... | |
| Public Member Functions inherited from BaseDynInst< Impl > | |
| BaseCPU * | getCpuPtr () |
| void | recordResult (bool f) |
| Records changes to result? More... | |
| bool | effAddrValid () const |
| Is the effective virtual address valid. More... | |
| bool | memOpDone () const |
| Whether or not the memory operation is done. More... | |
| void | memOpDone (bool f) |
| void | demapPage (Addr vaddr, uint64_t asn) |
| Invalidate a page in the DTLB and ITLB. More... | |
| void | demapInstPage (Addr vaddr, uint64_t asn) |
| void | demapDataPage (Addr vaddr, uint64_t asn) |
| Fault | initiateMemRead (Addr addr, unsigned size, Request::Flags flags) |
| Fault | writeMem (uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res) |
| void | splitRequest (RequestPtr req, RequestPtr &sreqLow, RequestPtr &sreqHigh) |
| Splits a request in two if it crosses a dcache block. More... | |
| void | initiateTranslation (RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, uint64_t *res, BaseTLB::Mode mode) |
| Initiate a DTB address translation. More... | |
| void | finishTranslation (WholeTranslationState *state) |
| Finish a DTB address translation. More... | |
| bool | translationStarted () const |
| True if the DTB address translation has started. More... | |
| void | translationStarted (bool f) |
| bool | translationCompleted () const |
| True if the DTB address translation has completed. More... | |
| void | translationCompleted (bool f) |
| bool | possibleLoadViolation () const |
| True if this address was found to match a previous load and they issued out of order. More... | |
| void | possibleLoadViolation (bool f) |
| bool | hitExternalSnoop () const |
| True if the address hit a external snoop while sitting in the LSQ. More... | |
| void | hitExternalSnoop (bool f) |
| bool | isTranslationDelayed () const |
| Returns true if the DTB address translation is being delayed due to a hw page table walk. More... | |
| PhysRegIndex | renamedDestRegIdx (int idx) const |
| Returns the physical register index of the i'th destination register. More... | |
| PhysRegIndex | renamedSrcRegIdx (int idx) const |
| Returns the physical register index of the i'th source register. More... | |
| TheISA::RegIndex | flattenedDestRegIdx (int idx) const |
| Returns the flattened register index of the i'th destination register. More... | |
| PhysRegIndex | prevDestRegIdx (int idx) const |
| Returns the physical register index of the previous physical register that remapped to the same logical register index. More... | |
| void | renameDestReg (int idx, PhysRegIndex renamed_dest, PhysRegIndex previous_rename) |
| Renames a destination register to a physical register. More... | |
| void | renameSrcReg (int idx, PhysRegIndex renamed_src) |
| Renames a source logical register to the physical register which has/will produce that logical register's result. More... | |
| void | flattenDestReg (int idx, TheISA::RegIndex flattened_dest) |
| Flattens a destination architectural register index into a logical index. More... | |
| BaseDynInst (const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu) | |
| BaseDynInst constructor given a binary instruction. More... | |
| BaseDynInst (const StaticInstPtr &staticInst, const StaticInstPtr ¯oop) | |
| BaseDynInst constructor given a StaticInst pointer. More... | |
| ~BaseDynInst () | |
| BaseDynInst destructor. More... | |
| void | dump () |
| Dumps out contents of this BaseDynInst. More... | |
| void | dump (std::string &outstring) |
| Dumps out contents of this BaseDynInst into given string. More... | |
| int | cpuId () const |
| Read this CPU's ID. More... | |
| uint32_t | socketId () const |
| Read this CPU's Socket ID. More... | |
| MasterID | masterId () const |
| Read this CPU's data requestor ID. More... | |
| ContextID | contextId () const |
| Read this context's system-wide ID. More... | |
| Fault | getFault () const |
| Returns the fault type. More... | |
| bool | doneTargCalc () |
| Checks whether or not this instruction has had its branch target calculated yet. More... | |
| void | setPredTarg (const TheISA::PCState &_predPC) |
| Set the predicted target of this current instruction. More... | |
| const TheISA::PCState & | readPredTarg () |
| Addr | predInstAddr () |
| Returns the predicted PC immediately after the branch. More... | |
| Addr | predNextInstAddr () |
| Returns the predicted PC two instructions after the branch. More... | |
| Addr | predMicroPC () |
| Returns the predicted micro PC after the branch. More... | |
| bool | readPredTaken () |
| Returns whether the instruction was predicted taken or not. More... | |
| void | setPredTaken (bool predicted_taken) |
| bool | mispredicted () |
| Returns whether the instruction mispredicted. More... | |
| bool | isNop () const |
| bool | isMemRef () const |
| bool | isLoad () const |
| bool | isStore () const |
| bool | isStoreConditional () const |
| bool | isInstPrefetch () const |
| bool | isDataPrefetch () const |
| bool | isInteger () const |
| bool | isFloating () const |
| bool | isControl () const |
| bool | isCall () const |
| bool | isReturn () const |
| bool | isDirectCtrl () const |
| bool | isIndirectCtrl () const |
| bool | isCondCtrl () const |
| bool | isUncondCtrl () const |
| bool | isCondDelaySlot () const |
| bool | isThreadSync () const |
| bool | isSerializing () const |
| bool | isSerializeBefore () const |
| bool | isSerializeAfter () const |
| bool | isSquashAfter () const |
| bool | isMemBarrier () const |
| bool | isWriteBarrier () const |
| bool | isNonSpeculative () const |
| bool | isQuiesce () const |
| bool | isIprAccess () const |
| bool | isUnverifiable () const |
| bool | isSyscall () const |
| bool | isMacroop () const |
| bool | isMicroop () const |
| bool | isDelayedCommit () const |
| bool | isLastMicroop () const |
| bool | isFirstMicroop () const |
| bool | isMicroBranch () const |
| void | setSerializeBefore () |
| Temporarily sets this instruction as a serialize before instruction. More... | |
| void | clearSerializeBefore () |
| Clears the serializeBefore part of this instruction. More... | |
| bool | isTempSerializeBefore () |
| Checks if this serializeBefore is only temporarily set. More... | |
| void | setSerializeAfter () |
| Temporarily sets this instruction as a serialize after instruction. More... | |
| void | clearSerializeAfter () |
| Clears the serializeAfter part of this instruction. More... | |
| bool | isTempSerializeAfter () |
| Checks if this serializeAfter is only temporarily set. More... | |
| void | setSerializeHandled () |
| Sets the serialization part of this instruction as handled. More... | |
| bool | isSerializeHandled () |
| Checks if the serialization part of this instruction has been handled. More... | |
| OpClass | opClass () const |
| Returns the opclass of this instruction. More... | |
| TheISA::PCState | branchTarget () const |
| Returns the branch target address. More... | |
| int8_t | numSrcRegs () const |
| Returns the number of source registers. More... | |
| int8_t | numDestRegs () const |
| Returns the number of destination registers. More... | |
| int8_t | numFPDestRegs () const |
| int8_t | numIntDestRegs () const |
| int8_t | numCCDestRegs () const |
| RegIndex | destRegIdx (int i) const |
| Returns the logical register index of the i'th destination register. More... | |
| RegIndex | srcRegIdx (int i) const |
| Returns the logical register index of the i'th source register. More... | |
| template<class T > | |
| void | popResult (T &t) |
| Pops a result off the instResult queue. More... | |
| template<class T > | |
| void | readResult (T &t) |
| Read the most recent result stored by this instruction. More... | |
| template<class T > | |
| void | setResult (T t) |
| Pushes a result onto the instResult queue. More... | |
| void | markSrcRegReady () |
| Records that one of the source registers is ready. More... | |
| void | markSrcRegReady (RegIndex src_idx) |
| Marks a specific register as ready. More... | |
| bool | isReadySrcRegIdx (int idx) const |
| Returns if a source register is ready. More... | |
| void | setCompleted () |
| Sets this instruction as completed. More... | |
| bool | isCompleted () const |
| Returns whether or not this instruction is completed. More... | |
| void | setResultReady () |
| Marks the result as ready. More... | |
| bool | isResultReady () const |
| Returns whether or not the result is ready. More... | |
| void | setCanIssue () |
| Sets this instruction as ready to issue. More... | |
| bool | readyToIssue () const |
| Returns whether or not this instruction is ready to issue. More... | |
| void | clearCanIssue () |
| Clears this instruction being able to issue. More... | |
| void | setIssued () |
| Sets this instruction as issued from the IQ. More... | |
| bool | isIssued () const |
| Returns whether or not this instruction has issued. More... | |
| void | clearIssued () |
| Clears this instruction as being issued. More... | |
| void | setExecuted () |
| Sets this instruction as executed. More... | |
| bool | isExecuted () const |
| Returns whether or not this instruction has executed. More... | |
| void | setCanCommit () |
| Sets this instruction as ready to commit. More... | |
| void | clearCanCommit () |
| Clears this instruction as being ready to commit. More... | |
| bool | readyToCommit () const |
| Returns whether or not this instruction is ready to commit. More... | |
| void | setAtCommit () |
| bool | isAtCommit () |
| void | setCommitted () |
| Sets this instruction as committed. More... | |
| bool | isCommitted () const |
| Returns whether or not this instruction is committed. More... | |
| void | setSquashed () |
| Sets this instruction as squashed. More... | |
| bool | isSquashed () const |
| Returns whether or not this instruction is squashed. More... | |
| void | setInIQ () |
| Sets this instruction as a entry the IQ. More... | |
| void | clearInIQ () |
| Sets this instruction as a entry the IQ. More... | |
| bool | isInIQ () const |
| Returns whether or not this instruction has issued. More... | |
| void | setSquashedInIQ () |
| Sets this instruction as squashed in the IQ. More... | |
| bool | isSquashedInIQ () const |
| Returns whether or not this instruction is squashed in the IQ. More... | |
| void | setInLSQ () |
| Sets this instruction as a entry the LSQ. More... | |
| void | removeInLSQ () |
| Sets this instruction as a entry the LSQ. More... | |
| bool | isInLSQ () const |
| Returns whether or not this instruction is in the LSQ. More... | |
| void | setSquashedInLSQ () |
| Sets this instruction as squashed in the LSQ. More... | |
| bool | isSquashedInLSQ () const |
| Returns whether or not this instruction is squashed in the LSQ. More... | |
| void | setInROB () |
| Sets this instruction as a entry the ROB. More... | |
| void | clearInROB () |
| Sets this instruction as a entry the ROB. More... | |
| bool | isInROB () const |
| Returns whether or not this instruction is in the ROB. More... | |
| void | setSquashedInROB () |
| Sets this instruction as squashed in the ROB. More... | |
| bool | isSquashedInROB () const |
| Returns whether or not this instruction is squashed in the ROB. More... | |
| TheISA::PCState | pcState () const |
| Read the PC state of this instruction. More... | |
| void | pcState (const TheISA::PCState &val) |
| Set the PC state of this instruction. More... | |
| Addr | instAddr () const |
| Read the PC of this instruction. More... | |
| Addr | nextInstAddr () const |
| Read the PC of the next instruction. More... | |
| Addr | microPC () const |
| Read the micro PC of this instruction. More... | |
| bool | readPredicate () |
| void | setPredicate (bool val) |
| void | setASID (short addr_space_id) |
| Sets the ASID. More... | |
| void | setTid (ThreadID tid) |
| Sets the thread id. More... | |
| void | setThreadState (ImplState *state) |
| Sets the pointer to the thread state. More... | |
| ThreadContext * | tcBase () |
| Returns the thread context. More... | |
| void | setEA (Addr ea) |
| Sets the effective address. More... | |
| Addr | getEA () const |
| Returns the effective address. More... | |
| bool | doneEACalc () |
| Returns whether or not the eff. More... | |
| bool | eaSrcsReady () |
| Returns whether or not the eff. More... | |
| bool | strictlyOrdered () const |
| Is this instruction's memory access strictly ordered? More... | |
| bool | hasRequest () |
| Has this instruction generated a memory request. More... | |
| ListIt & | getInstListIt () |
| Returns iterator to this instruction in the list of all insts. More... | |
| void | setInstListIt (ListIt _instListIt) |
| Sets iterator for this instruction in the list of all insts. More... | |
| unsigned int | readStCondFailures () const |
| Returns the number of consecutive store conditional failures. More... | |
| void | setStCondFailures (unsigned int sc_failures) |
| Sets the number of consecutive store conditional failures. More... | |
| void | armMonitor (Addr address) |
| bool | mwait (PacketPtr pkt) |
| void | mwaitAtomic (ThreadContext *tc) |
| AddressMonitor * | getAddrMonitor () |
| Public Member Functions inherited from ExecContext | |
| virtual Fault | readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags) |
| Perform an atomic memory read operation. More... | |
| virtual Fault | initiateMemRead (Addr addr, unsigned int size, Request::Flags flags) |
| Initiate a timing memory read operation. More... | |
| virtual Fault | writeMem (uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res)=0 |
| For atomic-mode contexts, perform an atomic memory write operation. More... | |
| Public Member Functions inherited from RefCounted | |
| RefCounted () | |
| We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More... | |
| virtual | ~RefCounted () |
| We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More... | |
| void | incref () |
| Increment the reference count. More... | |
| void | decref () |
| Decrement the reference count and destroy the object if all references are gone. More... | |
Protected Attributes | |
| std::array< MiscReg, TheISA::MaxMiscDestRegs > | _destMiscRegVal |
| Values to be written to the destination misc. More... | |
| std::array< short, TheISA::MaxMiscDestRegs > | _destMiscRegIdx |
| Indexes of the destination misc. More... | |
| uint8_t | _numDestMiscRegs |
| Number of destination misc. More... | |
| Protected Attributes inherited from BaseDynInst< Impl > | |
| std::queue< Result > | instResult |
| The result of the instruction; assumes an instruction can have many destination registers. More... | |
| TheISA::PCState | pc |
| PC state for this instruction. More... | |
| std::bitset< MaxFlags > | instFlags |
| std::bitset< NumStatus > | status |
| The status of this BaseDynInst. More... | |
| std::bitset< MaxInstSrcRegs > | _readySrcRegIdx |
| Whether or not the source register is ready. More... | |
| std::array< TheISA::RegIndex, TheISA::MaxInstDestRegs > | _flatDestRegIdx |
| Flattened register index of the destination registers of this instruction. More... | |
| std::array< PhysRegIndex, TheISA::MaxInstDestRegs > | _destRegIdx |
| Physical register index of the destination registers of this instruction. More... | |
| std::array< PhysRegIndex, TheISA::MaxInstSrcRegs > | _srcRegIdx |
| Physical register index of the source registers of this instruction. More... | |
| std::array< PhysRegIndex, TheISA::MaxInstDestRegs > | _prevDestRegIdx |
| Physical register index of the previous producers of the architected destinations. More... | |
Private Member Functions | |
| void | initVars () |
| Initializes variables. More... | |
Additional Inherited Members | |
| Public Attributes inherited from BaseDynInst< Impl > | |
| InstSeqNum | seqNum |
| The sequence number of the instruction. More... | |
| const StaticInstPtr | staticInst |
| The StaticInst used by this BaseDynInst. More... | |
| ImplCPU * | cpu |
| Pointer to the Impl's CPU object. More... | |
| ImplState * | thread |
| Pointer to the thread state. More... | |
| Fault | fault |
| The kind of fault this instruction has generated. More... | |
| Trace::InstRecord * | traceData |
| InstRecord that tracks this instructions. More... | |
| ThreadID | threadNumber |
| The thread this instruction is from. More... | |
| ListIt | instListIt |
| Iterator pointing to this BaseDynInst in the list of all insts. More... | |
| TheISA::PCState | predPC |
| Predicted PC state after this instruction. More... | |
| const StaticInstPtr | macroop |
| The Macroop if one exists. More... | |
| uint8_t | readyRegs |
| How many source registers are ready. More... | |
| Addr | effAddr |
| The effective virtual address (lds & stores only). More... | |
| Addr | physEffAddrLow |
| The effective physical address. More... | |
| Addr | physEffAddrHigh |
| The effective physical address of the second request for a split request. More... | |
| unsigned | memReqFlags |
| The memory request flags (from translation). More... | |
| short | asid |
| data address space ID, for loads & stores. More... | |
| uint8_t | effSize |
| The size of the request. More... | |
| uint8_t * | memData |
| Pointer to the data for the memory access. More... | |
| int16_t | lqIdx |
| Load queue index. More... | |
| int16_t | sqIdx |
| Store queue index. More... | |
| RequestPtr | savedReq |
| Saved memory requests (needed when the DTB address translation is delayed due to a hw page table walk). More... | |
| RequestPtr | savedSreqLow |
| RequestPtr | savedSreqHigh |
| RequestPtr | reqToVerify |
| Protected Types inherited from BaseDynInst< Impl > | |
| enum | Status { IqEntry, RobEntry, LsqEntry, Completed, ResultReady, CanIssue, Issued, Executed, CanCommit, AtCommit, Committed, Squashed, SquashedInIQ, SquashedInLSQ, SquashedInROB, RecoverInst, BlockingInst, ThreadsyncWait, SerializeBefore, SerializeAfter, SerializeHandled, NumStatus } |
| enum | Flags { TranslationStarted, TranslationCompleted, PossibleLoadViolation, HitExternalSnoop, EffAddrValid, RecordResult, Predicate, PredTaken, EACalcDone, IsStrictlyOrdered, ReqMade, MemOpDone, MaxFlags } |
Definition at line 60 of file dyn_inst.hh.
| typedef TheISA::CCReg BaseO3DynInst< Impl >::CCReg |
Definition at line 76 of file dyn_inst.hh.
| typedef TheISA::ExtMachInst BaseO3DynInst< Impl >::ExtMachInst |
Extended machine instruction type.
Definition at line 69 of file dyn_inst.hh.
| typedef TheISA::FloatReg BaseO3DynInst< Impl >::FloatReg |
Definition at line 74 of file dyn_inst.hh.
| typedef TheISA::FloatRegBits BaseO3DynInst< Impl >::FloatRegBits |
Definition at line 75 of file dyn_inst.hh.
| typedef TheISA::IntReg BaseO3DynInst< Impl >::IntReg |
Integer register index type.
Definition at line 73 of file dyn_inst.hh.
| typedef TheISA::MachInst BaseO3DynInst< Impl >::MachInst |
Binary machine instruction type.
Definition at line 67 of file dyn_inst.hh.
| typedef TheISA::MiscReg BaseO3DynInst< Impl >::MiscReg |
Misc register index type.
Definition at line 79 of file dyn_inst.hh.
| typedef Impl::O3CPU BaseO3DynInst< Impl >::O3CPU |
Typedef for the CPU.
Definition at line 64 of file dyn_inst.hh.
| typedef TheISA::RegIndex BaseO3DynInst< Impl >::RegIndex |
Logical register index type.
Definition at line 71 of file dyn_inst.hh.
| anonymous enum |
| Enumerator | |
|---|---|
| MaxInstSrcRegs | |
| MaxInstDestRegs | |
Definition at line 81 of file dyn_inst.hh.
| BaseO3DynInst< Impl >::BaseO3DynInst | ( | const StaticInstPtr & | staticInst, |
| const StaticInstPtr & | macroop, | ||
| TheISA::PCState | pc, | ||
| TheISA::PCState | predPC, | ||
| InstSeqNum | seq_num, | ||
| O3CPU * | cpu | ||
| ) |
BaseDynInst constructor given a binary instruction.
Definition at line 52 of file dyn_inst_impl.hh.
References BaseO3DynInst< Impl >::initVars().
| BaseO3DynInst< Impl >::BaseO3DynInst | ( | const StaticInstPtr & | _staticInst, |
| const StaticInstPtr & | _macroop | ||
| ) |
BaseDynInst constructor given a static inst pointer.
Definition at line 62 of file dyn_inst_impl.hh.
References BaseO3DynInst< Impl >::initVars().
| BaseO3DynInst< Impl >::~BaseO3DynInst | ( | ) |
Definition at line 69 of file dyn_inst_impl.hh.
References DPRINTFR, DTRACE, and X86ISA::val.
|
inline |
Calculates EA part of a memory instruction.
Currently unused, though it may be useful in the future if we want to split memory operations into EA calculation and memory access parts.
Definition at line 321 of file dyn_inst.hh.
References StaticInst::eaCompInst(), StaticInst::execute(), BaseDynInst< Impl >::staticInst, and BaseDynInst< Impl >::traceData.
| Fault BaseO3DynInst< Impl >::completeAcc | ( | PacketPtr | pkt | ) |
Completes the access.
Only valid for memory operations.
Definition at line 176 of file dyn_inst_impl.hh.
References Request::getExtraData(), and Packet::req.
| Fault BaseO3DynInst< Impl >::execute | ( | ) |
Executes the instruction.
Definition at line 140 of file dyn_inst_impl.hh.
|
inline |
Definition at line 207 of file dyn_inst.hh.
References CCRegClass, BaseDynInst< Impl >::cpu, StaticInst::destRegIdx(), FloatRegClass, RefCountingPtr< T >::get(), IntRegClass, MiscRegClass, BaseDynInst< Impl >::numDestRegs(), BaseDynInst< Impl >::prevDestRegIdx(), regIdxToClass(), BaseO3DynInst< Impl >::setCCRegOperand(), BaseO3DynInst< Impl >::setFloatRegOperandBits(), BaseO3DynInst< Impl >::setIntRegOperand(), and BaseDynInst< Impl >::staticInst.
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virtual |
Calls hardware return from error interrupt.
Implements ExecContext.
Definition at line 200 of file dyn_inst_impl.hh.
References CPA::available(), CPA::cpa(), AlphaISA::IPR_EXC_ADDR, NoFault, pc, and CPA::swAutoBegin().
| Fault BaseO3DynInst< Impl >::initiateAcc | ( | ) |
Initiates the access.
Only valid for memory operations.
Definition at line 158 of file dyn_inst_impl.hh.
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private |
Initializes variables.
Definition at line 107 of file dyn_inst_impl.hh.
References ArmISA::i.
Referenced by BaseO3DynInst< Impl >::BaseO3DynInst().
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inline |
Does the memory access part of a memory instruction.
Currently unused, though it may be useful in the future if we want to split memory operations into EA calculation and memory access parts.
Definition at line 330 of file dyn_inst.hh.
References StaticInst::execute(), StaticInst::memAccInst(), BaseDynInst< Impl >::staticInst, and BaseDynInst< Impl >::traceData.
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inlinevirtual |
Implements ExecContext.
Definition at line 270 of file dyn_inst.hh.
References BaseDynInst< Impl >::_srcRegIdx, and BaseDynInst< Impl >::cpu.
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inlinevirtual |
Reads a floating point register of single register width.
Implements ExecContext.
Definition at line 260 of file dyn_inst.hh.
References BaseDynInst< Impl >::_srcRegIdx, and BaseDynInst< Impl >::cpu.
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inlinevirtual |
Reads a floating point register in its binary format, instead of by value.
Implements ExecContext.
Definition at line 265 of file dyn_inst.hh.
References BaseDynInst< Impl >::_srcRegIdx, and BaseDynInst< Impl >::cpu.
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inlinevirtual |
Reads an integer register.
Implements ExecContext.
Definition at line 255 of file dyn_inst.hh.
References BaseDynInst< Impl >::_srcRegIdx, and BaseDynInst< Impl >::cpu.
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inlinevirtual |
Reads a misc.
register, including any side-effects the read might have as defined by the architecture.
Implements ExecContext.
Definition at line 141 of file dyn_inst.hh.
References BaseDynInst< Impl >::cpu, and BaseDynInst< Impl >::threadNumber.
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inlinevirtual |
Reads a misc.
register, including any side-effects the read might have as defined by the architecture.
Implements ExecContext.
Definition at line 173 of file dyn_inst.hh.
References BaseDynInst< Impl >::cpu, AlphaISA::Misc_Reg_Base, StaticInst::srcRegIdx(), and BaseDynInst< Impl >::threadNumber.
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inlinevirtual |
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inlinevirtual |
Records a CC register being set to a value.
Reimplemented from BaseDynInst< Impl >.
Definition at line 297 of file dyn_inst.hh.
References BaseDynInst< Impl >::_destRegIdx, BaseDynInst< Impl >::cpu, and BaseDynInst< Impl >::setCCRegOperand().
Referenced by BaseO3DynInst< Impl >::forwardOldRegs().
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inlinevirtual |
Records an fp register being set to a value.
Reimplemented from BaseDynInst< Impl >.
Definition at line 284 of file dyn_inst.hh.
References BaseDynInst< Impl >::_destRegIdx, BaseDynInst< Impl >::cpu, and BaseDynInst< Impl >::setFloatRegOperand().
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inlinevirtual |
Records an fp register being set to an integer value.
Reimplemented from BaseDynInst< Impl >.
Definition at line 290 of file dyn_inst.hh.
References BaseDynInst< Impl >::_destRegIdx, BaseDynInst< Impl >::cpu, and BaseDynInst< Impl >::setFloatRegOperandBits().
Referenced by BaseO3DynInst< Impl >::forwardOldRegs().
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inlinevirtual |
Reimplemented from BaseDynInst< Impl >.
Definition at line 278 of file dyn_inst.hh.
References BaseDynInst< Impl >::_destRegIdx, BaseDynInst< Impl >::cpu, and BaseDynInst< Impl >::setIntRegOperand().
Referenced by BaseO3DynInst< Impl >::forwardOldRegs().
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inlinevirtual |
Sets a misc.
register, including any side-effects the write might have as defined by the architecture.
Writes to misc. registers are recorded and deferred until the commit stage, when updateMiscRegs() is called. First, check if the misc reg has been written before and update its value to be committed instead of making a new entry. If not, make a new entry and record the write.
Implements ExecContext.
Definition at line 149 of file dyn_inst.hh.
References BaseO3DynInst< Impl >::_destMiscRegIdx, BaseO3DynInst< Impl >::_destMiscRegVal, BaseO3DynInst< Impl >::_numDestMiscRegs, AlphaISA::MaxMiscDestRegs, and X86ISA::val.
Referenced by BaseO3DynInst< Impl >::setMiscRegOperand().
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inlinevirtual |
Sets a misc.
register, including any side-effects the write might have as defined by the architecture.
Implements ExecContext.
Definition at line 183 of file dyn_inst.hh.
References StaticInst::destRegIdx(), AlphaISA::Misc_Reg_Base, and BaseO3DynInst< Impl >::setMiscReg().
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inlinevirtual |
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virtual |
Check for special simulator handling of specific PAL calls.
If return value is false, actual PAL call will be suppressed.
Implements ExecContext.
Definition at line 235 of file dyn_inst_impl.hh.
References panic.
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virtual |
Emulates a syscall.
Implements ExecContext.
Definition at line 245 of file dyn_inst_impl.hh.
References FullSystem, and panic.
| void BaseO3DynInst< Impl >::trap | ( | const Fault & | fault | ) |
Traps to handle specified fault.
Definition at line 228 of file dyn_inst_impl.hh.
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inline |
Called at the commit stage to update the misc.
registers.
Definition at line 191 of file dyn_inst.hh.
References BaseO3DynInst< Impl >::_destMiscRegIdx, BaseO3DynInst< Impl >::_destMiscRegVal, BaseO3DynInst< Impl >::_numDestMiscRegs, BaseDynInst< Impl >::cpu, ArmISA::i, and BaseDynInst< Impl >::thread.
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protected |
Indexes of the destination misc.
registers. They are needed to defer the write accesses to the misc. registers until the commit stage, when the instruction is out of its speculative state.
Definition at line 119 of file dyn_inst.hh.
Referenced by BaseO3DynInst< Impl >::setMiscReg(), and BaseO3DynInst< Impl >::updateMiscRegs().
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protected |
Values to be written to the destination misc.
registers.
Definition at line 113 of file dyn_inst.hh.
Referenced by BaseO3DynInst< Impl >::setMiscReg(), and BaseO3DynInst< Impl >::updateMiscRegs().
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protected |
Number of destination misc.
registers.
Definition at line 122 of file dyn_inst.hh.
Referenced by BaseO3DynInst< Impl >::setMiscReg(), and BaseO3DynInst< Impl >::updateMiscRegs().