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cpuid.cc
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1 /*
2  * Copyright (c) 2008 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  *
28  * Authors: Gabe Black
29  */
30 
31 #include "arch/x86/cpuid.hh"
32 
33 #include "base/bitfield.hh"
34 #include "cpu/thread_context.hh"
35 
36 namespace X86ISA {
41  };
42 
53 
54  /*
55  * The following are defined by the spec but not yet implemented
56  */
57 /* // Function 9 is reserved
58  SVMInfo = 10,
59  // Functions 11-24 are reserved
60  TLB1GBPageInfo = 25,
61  PerformanceInfo,*/
62 
64  };
65 
66  static const int vendorStringSize = 13;
67  static const char vendorString[vendorStringSize] = "M5 Simulator";
68  static const int nameStringSize = 48;
69  static const char nameString[nameStringSize] = "Fake M5 x86_64 CPU";
70 
71  uint64_t
72  stringToRegister(const char *str)
73  {
74  uint64_t reg = 0;
75  for (int pos = 3; pos >=0; pos--) {
76  reg <<= 8;
77  reg |= str[pos];
78  }
79  return reg;
80  }
81 
82  bool
83  doCpuid(ThreadContext * tc, uint32_t function,
84  uint32_t index, CpuidResult &result)
85  {
86  uint16_t family = bits(function, 31, 16);
87  uint16_t funcNum = bits(function, 15, 0);
88  if (family == 0x8000) {
89  // The extended functions
90  switch (funcNum) {
92  assert(vendorStringSize >= 12);
93  result = CpuidResult(
94  0x80000000 + NumExtendedCpuidFuncs - 1,
98  break;
100  result = CpuidResult(0x00020f51, 0x00000405,
101  0xe3d3fbff, 0x00000001);
102  break;
103  case NameString1:
104  case NameString2:
105  case NameString3:
106  {
107  // Zero fill anything beyond the end of the string. This
108  // should go away once the string is a vetted parameter.
109  char cleanName[nameStringSize];
110  memset(cleanName, '\0', nameStringSize);
111  strncpy(cleanName, nameString, nameStringSize);
112 
113  int offset = (funcNum - NameString1) * 16;
114  assert(nameStringSize >= offset + 16);
115  result = CpuidResult(
116  stringToRegister(cleanName + offset + 0),
117  stringToRegister(cleanName + offset + 4),
118  stringToRegister(cleanName + offset + 12),
119  stringToRegister(cleanName + offset + 8));
120  }
121  break;
122  case L1CacheAndTLB:
123  result = CpuidResult(0xff08ff08, 0xff20ff20,
124  0x40020140, 0x40020140);
125  break;
126  case L2L3CacheAndL2TLB:
127  result = CpuidResult(0x00000000, 0x42004200,
128  0x00000000, 0x04008140);
129  break;
130  case APMInfo:
131  result = CpuidResult(0x80000018, 0x68747541,
132  0x69746e65, 0x444d4163);
133  break;
134  case LongModeAddressSize:
135  result = CpuidResult(0x00003030, 0x00000000,
136  0x00000000, 0x00000000);
137  break;
138 /* case SVMInfo:
139  case TLB1GBPageInfo:
140  case PerformanceInfo:*/
141  default:
142  warn("x86 cpuid family 0x8000: unimplemented function %u",
143  funcNum);
144  return false;
145  }
146  } else if (family == 0x0000) {
147  // The standard functions
148  switch (funcNum) {
150  assert(vendorStringSize >= 12);
151  result = CpuidResult(
156  break;
157  case FamilyModelStepping:
158  result = CpuidResult(0x00020f51, 0x00000805,
159  0xe7dbfbff, 0x04000209);
160  break;
161  default:
162  warn("x86 cpuid family 0x0000: unimplemented function %u",
163  funcNum);
164  return false;
165  }
166  } else {
167  warn("x86 cpuid: unknown family %#x", family);
168  return false;
169  }
170 
171  return true;
172  }
173 } // namespace X86ISA
offset
Definition: misc.hh:977
static const char nameString[nameStringSize]
Definition: cpuid.cc:69
Bitfield< 5, 3 > reg
Definition: types.hh:89
Bitfield< 5, 3 > index
Definition: types.hh:95
StandardCpuidFunction
Definition: cpuid.cc:37
ThreadContext is the external interface to all thread state for anything outside of the CPU...
static const char vendorString[vendorStringSize]
Definition: cpuid.cc:67
#define warn(...)
Definition: misc.hh:219
ExtendedCpuidFunctions
Definition: cpuid.cc:43
uint64_t stringToRegister(const char *str)
Definition: cpuid.cc:72
bool doCpuid(ThreadContext *tc, uint32_t function, uint32_t index, CpuidResult &result)
Definition: cpuid.cc:83
static const int nameStringSize
Definition: cpuid.cc:68
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it...
Definition: bitfield.hh:67
static const int vendorStringSize
Definition: cpuid.cc:66

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