exec_context.hh

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/*
 * Copyright (c) 2014 ARM Limited
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2002-2005 The Regents of The University of Michigan
 * Copyright (c) 2015 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 *
 * Authors: Kevin Lim
 *          Andreas Sandberg
 */

#ifndef __CPU_EXEC_CONTEXT_HH__
#define __CPU_EXEC_CONTEXT_HH__

#include "arch/registers.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/static_inst_fwd.hh"
#include "cpu/translation.hh"
#include "mem/request.hh"

class ExecContext {
  public:
    typedef TheISA::IntReg IntReg;
    typedef TheISA::PCState PCState;
    typedef TheISA::FloatReg FloatReg;
    typedef TheISA::FloatRegBits FloatRegBits;
    typedef TheISA::MiscReg MiscReg;

    typedef TheISA::CCReg CCReg;

  public:
    virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0;

    virtual void setIntRegOperand(const StaticInst *si,
                                  int idx, IntReg val) = 0;

    virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0;

    virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si,
                                                 int idx) = 0;

    virtual void setFloatRegOperand(const StaticInst *si,
                                    int idx, FloatReg val) = 0;

    virtual void setFloatRegOperandBits(const StaticInst *si,
                                        int idx, FloatRegBits val) = 0;

    virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
    virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
    virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
    virtual void setMiscRegOperand(const StaticInst *si,
                                   int idx, const MiscReg &val) = 0;

    virtual MiscReg readMiscReg(int misc_reg) = 0;

    virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;

    virtual PCState pcState() const = 0;
    virtual void pcState(const PCState &val) = 0;
    virtual void setEA(Addr EA) = 0;
    virtual Addr getEA() const = 0;

    virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
                          Request::Flags flags)
    {
        panic("ExecContext::readMem() should be overridden\n");
    }

    virtual Fault initiateMemRead(Addr addr, unsigned int size,
                                  Request::Flags flags)
    {
        panic("ExecContext::initiateMemRead() should be overridden\n");
    }

    virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
                           Request::Flags flags, uint64_t *res) = 0;

    virtual void setStCondFailures(unsigned int sc_failures) = 0;

    virtual unsigned int readStCondFailures() const = 0;

    virtual void syscall(int64_t callnum, Fault *fault) = 0;

    virtual ThreadContext *tcBase() = 0;

    virtual Fault hwrei() = 0;

    virtual bool simPalCheck(int palFunc) = 0;

    virtual bool readPredicate() = 0;
    virtual void setPredicate(bool val) = 0;

    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
    virtual void armMonitor(Addr address) = 0;
    virtual bool mwait(PacketPtr pkt) = 0;
    virtual void mwaitAtomic(ThreadContext *tc) = 0;
    virtual AddressMonitor *getAddrMonitor() = 0;

#if THE_ISA == MIPS_ISA
    virtual MiscReg readRegOtherThread(int regIdx,
                                       ThreadID tid = InvalidThreadID) = 0;
    virtual void setRegOtherThread(int regIdx, MiscReg val,
                                   ThreadID tid = InvalidThreadID) = 0;
#endif

};

#endif // __CPU_EXEC_CONTEXT_HH__