generators.hh

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/*
 * Copyright (c) 2012-2013 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
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 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Thomas Grass
 *          Andreas Hansson
 *          Sascha Bischoff
 *          Neha Agarwal
 */

#ifndef __CPU_TRAFFIC_GEN_GENERATORS_HH__
#define __CPU_TRAFFIC_GEN_GENERATORS_HH__

#include "base/bitfield.hh"
#include "base/intmath.hh"
#include "mem/packet.hh"
#include "proto/protoio.hh"

class BaseGen
{

  protected:

    const std::string _name;

    const MasterID masterID;

    PacketPtr getPacket(Addr addr, unsigned size, const MemCmd& cmd,
                        Request::FlagsType flags = 0);

  public:

    const Tick duration;

    BaseGen(const std::string& _name, MasterID master_id, Tick _duration);

    virtual ~BaseGen() { }

    std::string name() const { return _name; }

    virtual void enter() = 0;

    virtual PacketPtr getNextPacket() = 0;

    virtual void exit() { };

    virtual Tick nextPacketTick(bool elastic, Tick delay) const = 0;

};

class IdleGen : public BaseGen
{

  public:

    IdleGen(const std::string& _name, MasterID master_id, Tick _duration)
        : BaseGen(_name, master_id, _duration)
    { }

    void enter() { }

    PacketPtr getNextPacket() { return NULL; }

    Tick nextPacketTick(bool elastic, Tick delay) const { return MaxTick; }
};

class LinearGen : public BaseGen
{

  public:

    LinearGen(const std::string& _name, MasterID master_id, Tick _duration,
              Addr start_addr, Addr end_addr, Addr _blocksize,
              Tick min_period, Tick max_period,
              uint8_t read_percent, Addr data_limit)
        : BaseGen(_name, master_id, _duration),
          startAddr(start_addr), endAddr(end_addr),
          blocksize(_blocksize), minPeriod(min_period),
          maxPeriod(max_period), readPercent(read_percent),
          dataLimit(data_limit), nextAddr(startAddr), dataManipulated(0)
    { }

    void enter();

    PacketPtr getNextPacket();

    Tick nextPacketTick(bool elastic, Tick delay) const;

  private:

    const Addr startAddr;

    const Addr endAddr;

    const Addr blocksize;

    const Tick minPeriod;
    const Tick maxPeriod;

    const uint8_t readPercent;

    const Addr dataLimit;

    Addr nextAddr;

    Addr dataManipulated;
};

class RandomGen : public BaseGen
{

  public:

    RandomGen(const std::string& _name, MasterID master_id, Tick _duration,
              Addr start_addr, Addr end_addr, Addr _blocksize,
              Tick min_period, Tick max_period,
              uint8_t read_percent, Addr data_limit)
        : BaseGen(_name, master_id, _duration),
          startAddr(start_addr), endAddr(end_addr),
          blocksize(_blocksize), minPeriod(min_period),
          maxPeriod(max_period), readPercent(read_percent),
          dataLimit(data_limit), dataManipulated(0)
    { }

    void enter();

    PacketPtr getNextPacket();

    Tick nextPacketTick(bool elastic, Tick delay) const;

  protected:

    const Addr startAddr;

    const Addr endAddr;

    const Addr blocksize;

    const Tick minPeriod;
    const Tick maxPeriod;

    const uint8_t readPercent;

    const Addr dataLimit;

    Addr dataManipulated;
};

class DramGen : public RandomGen
{

  public:

    DramGen(const std::string& _name, MasterID master_id, Tick _duration,
            Addr start_addr, Addr end_addr, Addr _blocksize,
            Tick min_period, Tick max_period,
            uint8_t read_percent, Addr data_limit,
            unsigned int num_seq_pkts, unsigned int page_size,
            unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
            unsigned int addr_mapping,
            unsigned int nbr_of_ranks)
        : RandomGen(_name, master_id, _duration, start_addr, end_addr,
          _blocksize, min_period, max_period, read_percent, data_limit),
          numSeqPkts(num_seq_pkts), countNumSeqPkts(0), addr(0),
          isRead(true), pageSize(page_size),
          pageBits(floorLog2(page_size / _blocksize)),
          bankBits(floorLog2(nbr_of_banks_DRAM)),
          blockBits(floorLog2(_blocksize)),
          nbrOfBanksDRAM(nbr_of_banks_DRAM),
          nbrOfBanksUtil(nbr_of_banks_util), addrMapping(addr_mapping),
          rankBits(floorLog2(nbr_of_ranks)),
          nbrOfRanks(nbr_of_ranks)
    {
        if (addrMapping != 1 && addrMapping != 0) {
            addrMapping = 1;
            warn("Unknown address mapping specified, using RoRaBaCoCh\n");
        }
    }

    PacketPtr getNextPacket();

    void genStartAddr(unsigned int new_bank , unsigned int new_rank);

  protected:

    const unsigned int numSeqPkts;

    unsigned int countNumSeqPkts;

    Addr addr;

    bool isRead;

    const unsigned int pageSize;

    const unsigned int pageBits;

    const unsigned int bankBits;

    const unsigned int blockBits;

    const unsigned int nbrOfBanksDRAM;

    const unsigned int nbrOfBanksUtil;

    unsigned int addrMapping;

    const unsigned int rankBits;

    const unsigned int nbrOfRanks;

};

class DramRotGen : public DramGen
{

  public:

    DramRotGen(const std::string& _name, MasterID master_id, Tick _duration,
            Addr start_addr, Addr end_addr, Addr _blocksize,
            Tick min_period, Tick max_period,
            uint8_t read_percent, Addr data_limit,
            unsigned int num_seq_pkts, unsigned int page_size,
            unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
            unsigned int addr_mapping,
            unsigned int nbr_of_ranks,
            unsigned int max_seq_count_per_rank)
        : DramGen(_name, master_id, _duration, start_addr, end_addr,
          _blocksize, min_period, max_period, read_percent, data_limit,
          num_seq_pkts, page_size, nbr_of_banks_DRAM,
          nbr_of_banks_util, addr_mapping,
          nbr_of_ranks),
          maxSeqCountPerRank(max_seq_count_per_rank),
          nextSeqCount(0)
    {
        // Rotating traffic generation can only support a read
        // percentage of 0, 50, or 100
        if (readPercent != 50  && readPercent != 100 && readPercent != 0) {
           fatal("%s: Unsupported read percentage for DramRotGen: %d",
                 _name, readPercent);
        }
    }

    PacketPtr getNextPacket();

  private:
    const unsigned int maxSeqCountPerRank;

    unsigned int nextSeqCount;
};

class TraceGen : public BaseGen
{

  private:

    struct TraceElement {

        MemCmd cmd;

        Addr addr;

        Addr blocksize;

        Tick tick;

        Request::FlagsType flags;

        bool isValid() const {
            return cmd != MemCmd::InvalidCmd;
        }

        void clear() {
            cmd = MemCmd::InvalidCmd;
        }
    };

    class InputStream
    {

      private:

        ProtoInputStream trace;

      public:

        InputStream(const std::string& filename);

        void reset();

        void init();

        bool read(TraceElement& element);
    };

  public:

    TraceGen(const std::string& _name, MasterID master_id, Tick _duration,
             const std::string& trace_file, Addr addr_offset)
        : BaseGen(_name, master_id, _duration),
          trace(trace_file),
          tickOffset(0),
          addrOffset(addr_offset),
          traceComplete(false)
    {
    }

    void enter();

    PacketPtr getNextPacket();

    void exit();

    Tick nextPacketTick(bool elastic, Tick delay) const;

  private:

    InputStream trace;

    TraceElement currElement;
    TraceElement nextElement;

    mutable Tick tickOffset;

    Addr addrOffset;

    bool traceComplete;
};

#endif