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decoder.hh
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30 
31 #ifndef __ARCH_RISCV_DECODER_HH__
32 #define __ARCH_RISCV_DECODER_HH__
33 
35 #include "arch/riscv/types.hh"
36 #include "base/misc.hh"
37 #include "base/types.hh"
38 #include "cpu/static_inst.hh"
39 
40 namespace RiscvISA
41 {
42 
43 class ISA;
44 class Decoder
45 {
46  protected:
47  //The extended machine instruction being generated
49  bool instDone;
50 
51  public:
52  Decoder(ISA* isa = nullptr) : instDone(false)
53  {}
54 
55  void
57  {
58  }
59 
60  void
62  {
63  instDone = false;
64  }
65 
66  //Use this to give data to the decoder. This should be used
67  //when there is control flow.
68  void
69  moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
70  {
71  emi = inst;
72  instDone = true;
73  }
74 
75  bool
77  {
78  return true;
79  }
80 
81  bool
83  {
84  return instDone;
85  }
86 
87  void takeOverFrom(Decoder *old) {}
88 
89  protected:
92 
93  public:
95 
101  {
102  return defaultCache.decode(this, mach_inst, addr);
103  }
104 
107  {
108  if (!instDone)
109  return nullptr;
110  instDone = false;
111  return decode(emi, nextPC.instAddr());
112  }
113 };
114 
115 } // namespace RiscvISA
116 
117 #endif // __ARCH_RISCV_DECODER_HH__
StaticInstPtr decode(RiscvISA::PCState &nextPC)
Definition: decoder.hh:106
Decoder(ISA *isa=nullptr)
Definition: decoder.hh:52
uint32_t MachInst
Definition: types.hh:53
bool instReady()
Definition: decoder.hh:82
void process()
Definition: decoder.hh:56
ip6_addr_t addr
Definition: inet.hh:335
uint64_t ExtMachInst
Definition: types.hh:54
Addr instAddr() const
Returns the memory address the bytes of this instruction came from.
Definition: types.hh:60
Bitfield< 4 > pc
StaticInstPtr decodeInst(ExtMachInst mach_inst)
void takeOverFrom(Decoder *old)
Definition: decoder.hh:87
static GenericISA::BasicDecodeCache defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:91
void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
Definition: decoder.hh:69
StaticInstPtr decode(TheISA::Decoder *const decoder, TheISA::ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decode_cache.cc:42
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.hh:100
ExtMachInst emi
Definition: decoder.hh:48
bool needMoreBytes()
Definition: decoder.hh:76

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