Project Overview
SmartNICs (DPUs/IPUs) have evolved far beyond packet processors. They now integrate multicore CPUs, programmable datapath processors, DMA engines, cryptographic accelerators, memory hierarchies, and hardware virtualization, effectively becoming independent computing platforms attached to the network. Yet today’s systems continue to treat SmartNICs as packet offload engines, exposing only low-level programming interfaces that underutilize their computational capabilities.
The CleanNIC (Clean-Slate SmartNIC) project rethinks SmartNICs as a systems platform. We redesign their programming abstractions, runtime systems, virtualization mechanisms, communication interfaces, and datapath architecture, spanning the entire software stack from hardware characterization and debugging to RPC runtimes, secure execution, I/O virtualization, and programmable datapaths. Our goal is to transform SmartNICs into efficient, programmable, and general-purpose execution platforms for future cloud and distributed systems.
Challenges
Although modern SmartNICs have evolved into powerful computing platforms, existing software stacks continue to treat them as traditional NICs. This mismatch leads to several challenges:
- Limited visibility. Minimal insight into internal hardware behavior hinders performance analysis, debugging, and optimization.
- Poor programmability. Low-level, vendor-specific programming models make application development difficult and limit portability.
- Rigid communication abstractions. Packet- and transport-centric interfaces do not match the RPC- and message-oriented semantics of modern distributed applications.
- Legacy virtualization. Coarse-grained I/O virtualization mechanisms fail to support the scalability and flexibility required by cloud-native workloads.
- Fixed datapaths. Hardware-defined processing pipelines limit software-defined scheduling, parallelism, and extensibility for diverse traffic profiles.
Our Approach
Our insight is that system-level abstractions tailored to modern cloud applications are essential to fully unlocking the computational capabilities of SmartNICs. We ask: What are the right abstractions, runtimes, and system architectures for SmartNICs to become general-purpose computing platforms? In this project, we have touched the SmartNIC software stack spanning hardware characterization and observability, debugging infrastructure, programming models, RPC runtimes, secure execution, I/O virtualization, and programmable datapath architectures.
Here are the systems we have built.
- SID realizes software-interposed datapath via Elastic QPs for rack-scale interconnects (SIGCOMM’26).
- SG-IOV introduces socket-granular I/O virtualization to offload container networks (ASPLOS’26).
- SCR provides a framework enabling packet-granular software control over the harware transport (NSDI’25).
- RpcNIC is a software-hardware co-designed SmartNIC-native accelerator for the RPC stack (HPCA’25).
- BenchBF3 characterizes the capabilities of the BlueFiled-3 SmartNIC (ICNP’24).
- LogNIC develops a high-level architectural performance model for SmartNICs (MICRO’23).